1 /* $NetBSD: acpi_cpu_md.c,v 1.69 2011/11/15 07:20:30 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.69 2011/11/15 07:20:30 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpufreq.h> 35 #include <sys/device.h> 36 #include <sys/kcore.h> 37 #include <sys/sysctl.h> 38 #include <sys/xcall.h> 39 40 #include <x86/cpu.h> 41 #include <x86/cpufunc.h> 42 #include <x86/cputypes.h> 43 #include <x86/cpuvar.h> 44 #include <x86/cpu_msr.h> 45 #include <x86/machdep.h> 46 47 #include <dev/acpi/acpica.h> 48 #include <dev/acpi/acpi_cpu.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <machine/acpi_machdep.h> 54 55 /* 56 * Intel IA32_MISC_ENABLE. 57 */ 58 #define MSR_MISC_ENABLE_EST __BIT(16) 59 #define MSR_MISC_ENABLE_TURBO __BIT(38) 60 61 /* 62 * AMD C1E. 63 */ 64 #define MSR_CMPHALT 0xc0010055 65 66 #define MSR_CMPHALT_SMI __BIT(27) 67 #define MSR_CMPHALT_C1E __BIT(28) 68 #define MSR_CMPHALT_BMSTS __BIT(29) 69 70 /* 71 * AMD families 10h, 11h, 12h, and 14h. 72 */ 73 #define MSR_10H_LIMIT 0xc0010061 74 #define MSR_10H_CONTROL 0xc0010062 75 #define MSR_10H_STATUS 0xc0010063 76 #define MSR_10H_CONFIG 0xc0010064 77 78 /* 79 * AMD family 0Fh. 80 */ 81 #define MSR_0FH_CONTROL 0xc0010041 82 #define MSR_0FH_STATUS 0xc0010042 83 84 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 85 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 86 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 87 88 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 89 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 90 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 91 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 92 93 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 94 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 95 96 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 97 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 98 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 99 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 100 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 101 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 102 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 103 104 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 105 106 static char native_idle_text[16]; 107 void (*native_idle)(void) = NULL; 108 109 static int acpicpu_md_quirk_piix4(const struct pci_attach_args *); 110 static void acpicpu_md_pstate_hwf_reset(void *, void *); 111 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 112 uint32_t *); 113 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 114 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 115 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 116 uint32_t, uint32_t); 117 static int acpicpu_md_pstate_sysctl_init(void); 118 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 119 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 120 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 121 122 extern struct acpicpu_softc **acpicpu_sc; 123 static struct sysctllog *acpicpu_log = NULL; 124 125 struct cpu_info * 126 acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 127 { 128 struct cpufeature_attach_args *cfaa = aux; 129 130 if (strcmp(cfaa->name, "frequency") != 0) 131 return NULL; 132 133 return cfaa->ci; 134 } 135 136 struct cpu_info * 137 acpicpu_md_attach(device_t parent, device_t self, void *aux) 138 { 139 struct cpufeature_attach_args *cfaa = aux; 140 141 return cfaa->ci; 142 } 143 144 uint32_t 145 acpicpu_md_flags(void) 146 { 147 struct cpu_info *ci = curcpu(); 148 struct pci_attach_args pa; 149 uint32_t family, val = 0; 150 uint32_t regs[4]; 151 uint64_t msr; 152 153 if (acpi_md_ncpus() == 1) 154 val |= ACPICPU_FLAG_C_BM; 155 156 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 157 val |= ACPICPU_FLAG_C_FFH; 158 159 /* 160 * By default, assume that the local APIC timer 161 * as well as TSC are stalled during C3 sleep. 162 */ 163 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 164 165 switch (cpu_vendor) { 166 167 case CPUVENDOR_IDT: 168 169 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 170 val |= ACPICPU_FLAG_P_FFH; 171 172 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 173 val |= ACPICPU_FLAG_T_FFH; 174 175 break; 176 177 case CPUVENDOR_INTEL: 178 179 /* 180 * Bus master control and arbitration should be 181 * available on all supported Intel CPUs (to be 182 * sure, this is double-checked later from the 183 * firmware data). These flags imply that it is 184 * not necessary to flush caches before C3 state. 185 */ 186 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 187 188 /* 189 * Check if we can use "native", MSR-based, 190 * access. If not, we have to resort to I/O. 191 */ 192 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 193 val |= ACPICPU_FLAG_P_FFH; 194 195 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 196 val |= ACPICPU_FLAG_T_FFH; 197 198 /* 199 * Check whether MSR_APERF, MSR_MPERF, and Turbo 200 * Boost are available. Also see if we might have 201 * an invariant local APIC timer ("ARAT"). 202 */ 203 if (cpuid_level >= 0x06) { 204 205 x86_cpuid(0x00000006, regs); 206 207 if ((regs[2] & CPUID_DSPM_HWF) != 0) 208 val |= ACPICPU_FLAG_P_HWF; 209 210 if ((regs[0] & CPUID_DSPM_IDA) != 0) 211 val |= ACPICPU_FLAG_P_TURBO; 212 213 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 214 val &= ~ACPICPU_FLAG_C_APIC; 215 } 216 217 /* 218 * Detect whether TSC is invariant. If it is not, 219 * we keep the flag to note that TSC will not run 220 * at constant rate. Depending on the CPU, this may 221 * affect P- and T-state changes, but especially 222 * relevant are C-states; with variant TSC, states 223 * larger than C1 may completely stop the counter. 224 */ 225 x86_cpuid(0x80000000, regs); 226 227 if (regs[0] >= 0x80000007) { 228 229 x86_cpuid(0x80000007, regs); 230 231 if ((regs[3] & __BIT(8)) != 0) 232 val &= ~ACPICPU_FLAG_C_TSC; 233 } 234 235 break; 236 237 case CPUVENDOR_AMD: 238 239 x86_cpuid(0x80000000, regs); 240 241 if (regs[0] < 0x80000007) 242 break; 243 244 x86_cpuid(0x80000007, regs); 245 246 family = CPUID2FAMILY(ci->ci_signature); 247 248 if (family == 0xf) 249 family += CPUID2EXTFAMILY(ci->ci_signature); 250 251 switch (family) { 252 253 case 0x0f: 254 255 /* 256 * Evaluate support for the "FID/VID 257 * algorithm" also used by powernow(4). 258 */ 259 if ((regs[3] & CPUID_APM_FID) == 0) 260 break; 261 262 if ((regs[3] & CPUID_APM_VID) == 0) 263 break; 264 265 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 266 break; 267 268 case 0x10: 269 case 0x11: 270 271 if (rdmsr_safe(MSR_CMPHALT, &msr) != EFAULT) 272 val |= ACPICPU_FLAG_C_C1E; 273 274 /* FALLTHROUGH */ 275 276 case 0x12: 277 case 0x14: /* AMD Fusion */ 278 279 /* 280 * Like with Intel, detect invariant TSC, 281 * MSR-based P-states, and AMD's "turbo" 282 * (Core Performance Boost), respectively. 283 */ 284 if ((regs[3] & CPUID_APM_TSC) != 0) 285 val &= ~ACPICPU_FLAG_C_TSC; 286 287 if ((regs[3] & CPUID_APM_HWP) != 0) 288 val |= ACPICPU_FLAG_P_FFH; 289 290 if ((regs[3] & CPUID_APM_CPB) != 0) 291 val |= ACPICPU_FLAG_P_TURBO; 292 293 /* 294 * Also check for APERF and MPERF, 295 * first available in the family 10h. 296 */ 297 if (cpuid_level >= 0x06) { 298 299 x86_cpuid(0x00000006, regs); 300 301 if ((regs[2] & CPUID_DSPM_HWF) != 0) 302 val |= ACPICPU_FLAG_P_HWF; 303 } 304 305 break; 306 } 307 308 break; 309 } 310 311 /* 312 * There are several erratums for PIIX4. 313 */ 314 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 315 val |= ACPICPU_FLAG_PIIX4; 316 317 return val; 318 } 319 320 static int 321 acpicpu_md_quirk_piix4(const struct pci_attach_args *pa) 322 { 323 324 /* 325 * XXX: The pci_find_device(9) function only 326 * deals with attached devices. Change this 327 * to use something like pci_device_foreach(). 328 */ 329 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 330 return 0; 331 332 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 333 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 334 return 1; 335 336 return 0; 337 } 338 339 void 340 acpicpu_md_quirk_c1e(void) 341 { 342 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 343 uint64_t val; 344 345 val = rdmsr(MSR_CMPHALT); 346 347 if ((val & c1e) != 0) 348 wrmsr(MSR_CMPHALT, val & ~c1e); 349 } 350 351 int 352 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 353 { 354 const size_t size = sizeof(native_idle_text); 355 struct acpicpu_cstate *cs; 356 bool ipi = false; 357 int i; 358 359 /* 360 * Save the cpu_idle(9) loop used by default. 361 */ 362 x86_cpu_idle_get(&native_idle, native_idle_text, size); 363 364 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 365 366 cs = &sc->sc_cstate[i]; 367 368 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 369 ipi = true; 370 break; 371 } 372 } 373 374 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 375 376 return 0; 377 } 378 379 int 380 acpicpu_md_cstate_stop(void) 381 { 382 static char text[16]; 383 void (*func)(void); 384 uint64_t xc; 385 bool ipi; 386 387 x86_cpu_idle_get(&func, text, sizeof(text)); 388 389 if (func == native_idle) 390 return EALREADY; 391 392 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 393 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 394 395 /* 396 * Run a cross-call to ensure that all CPUs are 397 * out from the ACPI idle-loop before detachment. 398 */ 399 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 400 xc_wait(xc); 401 402 return 0; 403 } 404 405 /* 406 * Called with interrupts enabled. 407 */ 408 void 409 acpicpu_md_cstate_enter(int method, int state) 410 { 411 struct cpu_info *ci = curcpu(); 412 413 KASSERT(ci->ci_ilevel == IPL_NONE); 414 415 switch (method) { 416 417 case ACPICPU_C_STATE_FFH: 418 419 x86_monitor(&ci->ci_want_resched, 0, 0); 420 421 if (__predict_false(ci->ci_want_resched != 0)) 422 return; 423 424 x86_mwait((state - 1) << 4, 0); 425 break; 426 427 case ACPICPU_C_STATE_HALT: 428 429 x86_disable_intr(); 430 431 if (__predict_false(ci->ci_want_resched != 0)) { 432 x86_enable_intr(); 433 return; 434 } 435 436 x86_stihlt(); 437 break; 438 } 439 } 440 441 int 442 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 443 { 444 uint64_t xc, val; 445 446 switch (cpu_vendor) { 447 448 case CPUVENDOR_IDT: 449 case CPUVENDOR_INTEL: 450 451 /* 452 * Make sure EST is enabled. 453 */ 454 if ((sc->sc_flags & ACPICPU_FLAG_P_FFH) != 0) { 455 456 val = rdmsr(MSR_MISC_ENABLE); 457 458 if ((val & MSR_MISC_ENABLE_EST) == 0) { 459 460 val |= MSR_MISC_ENABLE_EST; 461 wrmsr(MSR_MISC_ENABLE, val); 462 val = rdmsr(MSR_MISC_ENABLE); 463 464 if ((val & MSR_MISC_ENABLE_EST) == 0) 465 return ENOTTY; 466 } 467 } 468 } 469 470 /* 471 * Reset the APERF and MPERF counters. 472 */ 473 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 474 xc = xc_broadcast(0, acpicpu_md_pstate_hwf_reset, NULL, NULL); 475 xc_wait(xc); 476 } 477 478 return acpicpu_md_pstate_sysctl_init(); 479 } 480 481 int 482 acpicpu_md_pstate_stop(void) 483 { 484 485 if (acpicpu_log == NULL) 486 return EALREADY; 487 488 sysctl_teardown(&acpicpu_log); 489 acpicpu_log = NULL; 490 491 return 0; 492 } 493 494 int 495 acpicpu_md_pstate_init(struct acpicpu_softc *sc) 496 { 497 struct cpu_info *ci = sc->sc_ci; 498 struct acpicpu_pstate *ps, msr; 499 uint32_t family, i = 0; 500 501 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 502 503 switch (cpu_vendor) { 504 505 case CPUVENDOR_IDT: 506 case CPUVENDOR_INTEL: 507 508 /* 509 * If the so-called Turbo Boost is present, 510 * the P0-state is always the "turbo state". 511 * It is shown as the P1 frequency + 1 MHz. 512 * 513 * For discussion, see: 514 * 515 * Intel Corporation: Intel Turbo Boost Technology 516 * in Intel Core(tm) Microarchitectures (Nehalem) 517 * Based Processors. White Paper, November 2008. 518 */ 519 if (sc->sc_pstate_count >= 2 && 520 (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 521 522 ps = &sc->sc_pstate[0]; 523 524 if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 525 ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 526 } 527 528 msr.ps_control_addr = MSR_PERF_CTL; 529 msr.ps_control_mask = __BITS(0, 15); 530 531 msr.ps_status_addr = MSR_PERF_STATUS; 532 msr.ps_status_mask = __BITS(0, 15); 533 break; 534 535 case CPUVENDOR_AMD: 536 537 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 538 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 539 540 family = CPUID2FAMILY(ci->ci_signature); 541 542 if (family == 0xf) 543 family += CPUID2EXTFAMILY(ci->ci_signature); 544 545 switch (family) { 546 547 case 0x0f: 548 msr.ps_control_addr = MSR_0FH_CONTROL; 549 msr.ps_status_addr = MSR_0FH_STATUS; 550 break; 551 552 case 0x10: 553 case 0x11: 554 case 0x12: 555 case 0x14: /* AMD Fusion */ 556 msr.ps_control_addr = MSR_10H_CONTROL; 557 msr.ps_control_mask = __BITS(0, 2); 558 559 msr.ps_status_addr = MSR_10H_STATUS; 560 msr.ps_status_mask = __BITS(0, 2); 561 break; 562 563 default: 564 /* 565 * If we have an unknown AMD CPU, rely on XPSS. 566 */ 567 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 568 return EOPNOTSUPP; 569 } 570 571 break; 572 573 default: 574 return ENODEV; 575 } 576 577 /* 578 * Fill the P-state structures with MSR addresses that are 579 * known to be correct. If we do not know the addresses, 580 * leave the values intact. If a vendor uses XPSS, we do 581 * not necessarily need to do anything to support new CPUs. 582 */ 583 while (i < sc->sc_pstate_count) { 584 585 ps = &sc->sc_pstate[i]; 586 587 if (msr.ps_flags != 0) 588 ps->ps_flags |= msr.ps_flags; 589 590 if (msr.ps_status_addr != 0) 591 ps->ps_status_addr = msr.ps_status_addr; 592 593 if (msr.ps_status_mask != 0) 594 ps->ps_status_mask = msr.ps_status_mask; 595 596 if (msr.ps_control_addr != 0) 597 ps->ps_control_addr = msr.ps_control_addr; 598 599 if (msr.ps_control_mask != 0) 600 ps->ps_control_mask = msr.ps_control_mask; 601 602 i++; 603 } 604 605 return 0; 606 } 607 608 /* 609 * Read the IA32_APERF and IA32_MPERF counters. The first 610 * increments at the rate of the fixed maximum frequency 611 * configured during the boot, whereas APERF counts at the 612 * rate of the actual frequency. Note that the MSRs must be 613 * read without delay, and that only the ratio between 614 * IA32_APERF and IA32_MPERF is architecturally defined. 615 * 616 * The function thus returns the percentage of the actual 617 * frequency in terms of the maximum frequency of the calling 618 * CPU since the last call. A value zero implies an error. 619 * 620 * For further details, refer to: 621 * 622 * Intel Corporation: Intel 64 and IA-32 Architectures 623 * Software Developer's Manual. Section 13.2, Volume 3A: 624 * System Programming Guide, Part 1. July, 2008. 625 * 626 * Advanced Micro Devices: BIOS and Kernel Developer's 627 * Guide (BKDG) for AMD Family 10h Processors. Section 628 * 2.4.5, Revision 3.48, April 2010. 629 */ 630 uint8_t 631 acpicpu_md_pstate_hwf(struct cpu_info *ci) 632 { 633 struct acpicpu_softc *sc; 634 uint64_t aperf, mperf; 635 uint8_t rv = 0; 636 637 sc = acpicpu_sc[ci->ci_acpiid]; 638 639 if (__predict_false(sc == NULL)) 640 return 0; 641 642 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 643 return 0; 644 645 aperf = sc->sc_pstate_aperf; 646 mperf = sc->sc_pstate_mperf; 647 648 x86_disable_intr(); 649 650 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 651 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 652 653 x86_enable_intr(); 654 655 aperf = sc->sc_pstate_aperf - aperf; 656 mperf = sc->sc_pstate_mperf - mperf; 657 658 if (__predict_true(mperf != 0)) 659 rv = (aperf * 100) / mperf; 660 661 return rv; 662 } 663 664 static void 665 acpicpu_md_pstate_hwf_reset(void *arg1, void *arg2) 666 { 667 struct cpu_info *ci = curcpu(); 668 struct acpicpu_softc *sc; 669 670 sc = acpicpu_sc[ci->ci_acpiid]; 671 672 if (__predict_false(sc == NULL)) 673 return; 674 675 x86_disable_intr(); 676 677 wrmsr(MSR_APERF, 0); 678 wrmsr(MSR_MPERF, 0); 679 680 x86_enable_intr(); 681 682 sc->sc_pstate_aperf = 0; 683 sc->sc_pstate_mperf = 0; 684 } 685 686 int 687 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 688 { 689 struct acpicpu_pstate *ps = NULL; 690 uint64_t val; 691 uint32_t i; 692 693 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 694 return acpicpu_md_pstate_fidvid_get(sc, freq); 695 696 /* 697 * Pick any P-state for the status address. 698 */ 699 for (i = 0; i < sc->sc_pstate_count; i++) { 700 701 ps = &sc->sc_pstate[i]; 702 703 if (__predict_true(ps->ps_freq != 0)) 704 break; 705 } 706 707 if (__predict_false(ps == NULL)) 708 return ENODEV; 709 710 if (__predict_false(ps->ps_status_addr == 0)) 711 return EINVAL; 712 713 val = rdmsr(ps->ps_status_addr); 714 715 if (__predict_true(ps->ps_status_mask != 0)) 716 val = val & ps->ps_status_mask; 717 718 /* 719 * Search for the value from known P-states. 720 */ 721 for (i = 0; i < sc->sc_pstate_count; i++) { 722 723 ps = &sc->sc_pstate[i]; 724 725 if (__predict_false(ps->ps_freq == 0)) 726 continue; 727 728 if (val == ps->ps_status) { 729 *freq = ps->ps_freq; 730 return 0; 731 } 732 } 733 734 /* 735 * If the value was not found, try APERF/MPERF. 736 * The state is P0 if the return value is 100 %. 737 */ 738 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 739 740 KASSERT(sc->sc_pstate_count > 0); 741 KASSERT(sc->sc_pstate[0].ps_freq != 0); 742 743 if (acpicpu_md_pstate_hwf(sc->sc_ci) == 100) { 744 *freq = sc->sc_pstate[0].ps_freq; 745 return 0; 746 } 747 } 748 749 return EIO; 750 } 751 752 int 753 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 754 { 755 uint64_t val = 0; 756 757 if (__predict_false(ps->ps_control_addr == 0)) 758 return EINVAL; 759 760 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 761 return acpicpu_md_pstate_fidvid_set(ps); 762 763 /* 764 * If the mask is set, do a read-modify-write. 765 */ 766 if (__predict_true(ps->ps_control_mask != 0)) { 767 val = rdmsr(ps->ps_control_addr); 768 val &= ~ps->ps_control_mask; 769 } 770 771 val |= ps->ps_control; 772 773 wrmsr(ps->ps_control_addr, val); 774 DELAY(ps->ps_latency); 775 776 return 0; 777 } 778 779 static int 780 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 781 { 782 struct acpicpu_pstate *ps; 783 uint32_t fid, i, vid; 784 uint32_t cfid, cvid; 785 int rv; 786 787 /* 788 * AMD family 0Fh needs special treatment. 789 * While it wants to use ACPI, it does not 790 * comply with the ACPI specifications. 791 */ 792 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 793 794 if (rv != 0) 795 return rv; 796 797 for (i = 0; i < sc->sc_pstate_count; i++) { 798 799 ps = &sc->sc_pstate[i]; 800 801 if (__predict_false(ps->ps_freq == 0)) 802 continue; 803 804 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 805 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 806 807 if (cfid == fid && cvid == vid) { 808 *freq = ps->ps_freq; 809 return 0; 810 } 811 } 812 813 return EIO; 814 } 815 816 static int 817 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 818 { 819 const uint64_t ctrl = ps->ps_control; 820 uint32_t cfid, cvid, fid, i, irt; 821 uint32_t pll, vco_cfid, vco_fid; 822 uint32_t val, vid, vst; 823 int rv; 824 825 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 826 827 if (rv != 0) 828 return rv; 829 830 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 831 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 832 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 833 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 834 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 835 836 vst = vst * 20; 837 pll = pll * 1000 / 5; 838 irt = 10 * __BIT(irt); 839 840 /* 841 * Phase 1. 842 */ 843 while (cvid > vid) { 844 845 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 846 val = (val > cvid) ? 0 : cvid - val; 847 848 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 849 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 850 851 if (rv != 0) 852 return rv; 853 } 854 855 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 856 857 for (; i > 0 && cvid > 0; --i) { 858 859 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 860 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 861 862 if (rv != 0) 863 return rv; 864 } 865 866 /* 867 * Phase 2. 868 */ 869 if (cfid != fid) { 870 871 vco_fid = FID_TO_VCO_FID(fid); 872 vco_cfid = FID_TO_VCO_FID(cfid); 873 874 while (abs(vco_fid - vco_cfid) > 2) { 875 876 if (fid <= cfid) 877 val = cfid - 2; 878 else { 879 val = (cfid > 6) ? cfid + 2 : 880 FID_TO_VCO_FID(cfid) + 2; 881 } 882 883 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 884 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 885 886 if (rv != 0) 887 return rv; 888 889 vco_cfid = FID_TO_VCO_FID(cfid); 890 } 891 892 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 893 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 894 895 if (rv != 0) 896 return rv; 897 } 898 899 /* 900 * Phase 3. 901 */ 902 if (cvid != vid) { 903 904 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 905 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 906 907 if (rv != 0) 908 return rv; 909 } 910 911 return 0; 912 } 913 914 static int 915 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 916 { 917 int i = ACPICPU_P_STATE_RETRY * 100; 918 uint64_t val; 919 920 do { 921 val = rdmsr(MSR_0FH_STATUS); 922 923 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 924 925 if (i == 0) 926 return EAGAIN; 927 928 if (cfid != NULL) 929 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 930 931 if (cvid != NULL) 932 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 933 934 return 0; 935 } 936 937 static void 938 acpicpu_md_pstate_fidvid_write(uint32_t fid, 939 uint32_t vid, uint32_t cnt, uint32_t tmo) 940 { 941 uint64_t val = 0; 942 943 val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 944 val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 945 val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 946 val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 947 948 wrmsr(MSR_0FH_CONTROL, val); 949 DELAY(tmo); 950 } 951 952 int 953 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 954 { 955 struct acpicpu_tstate *ts; 956 uint64_t val; 957 uint32_t i; 958 959 val = rdmsr(MSR_THERM_CONTROL); 960 961 for (i = 0; i < sc->sc_tstate_count; i++) { 962 963 ts = &sc->sc_tstate[i]; 964 965 if (ts->ts_percent == 0) 966 continue; 967 968 if (val == ts->ts_status) { 969 *percent = ts->ts_percent; 970 return 0; 971 } 972 } 973 974 return EIO; 975 } 976 977 int 978 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 979 { 980 uint64_t val; 981 uint8_t i; 982 983 val = ts->ts_control; 984 val = val & __BITS(1, 4); 985 986 wrmsr(MSR_THERM_CONTROL, val); 987 988 if (ts->ts_status == 0) { 989 DELAY(ts->ts_latency); 990 return 0; 991 } 992 993 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 994 995 val = rdmsr(MSR_THERM_CONTROL); 996 997 if (val == ts->ts_status) 998 return 0; 999 1000 DELAY(ts->ts_latency); 1001 } 1002 1003 return EAGAIN; 1004 } 1005 1006 /* 1007 * A kludge for backwards compatibility. 1008 */ 1009 static int 1010 acpicpu_md_pstate_sysctl_init(void) 1011 { 1012 const struct sysctlnode *fnode, *mnode, *rnode; 1013 const char *str; 1014 int rv; 1015 1016 switch (cpu_vendor) { 1017 1018 case CPUVENDOR_IDT: 1019 case CPUVENDOR_INTEL: 1020 str = "est"; 1021 break; 1022 1023 case CPUVENDOR_AMD: 1024 str = "powernow"; 1025 break; 1026 1027 default: 1028 return ENODEV; 1029 } 1030 1031 1032 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1033 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1034 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1035 1036 if (rv != 0) 1037 goto fail; 1038 1039 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1040 0, CTLTYPE_NODE, str, NULL, 1041 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1042 1043 if (rv != 0) 1044 goto fail; 1045 1046 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1047 0, CTLTYPE_NODE, "frequency", NULL, 1048 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1049 1050 if (rv != 0) 1051 goto fail; 1052 1053 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1054 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1055 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1056 1057 if (rv != 0) 1058 goto fail; 1059 1060 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1061 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1062 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1063 1064 if (rv != 0) 1065 goto fail; 1066 1067 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1068 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1069 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1070 1071 if (rv != 0) 1072 goto fail; 1073 1074 return 0; 1075 1076 fail: 1077 if (acpicpu_log != NULL) { 1078 sysctl_teardown(&acpicpu_log); 1079 acpicpu_log = NULL; 1080 } 1081 1082 return rv; 1083 } 1084 1085 static int 1086 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1087 { 1088 struct sysctlnode node; 1089 uint32_t freq; 1090 int err; 1091 1092 freq = cpufreq_get(curcpu()); 1093 1094 if (freq == 0) 1095 return ENXIO; 1096 1097 node = *rnode; 1098 node.sysctl_data = &freq; 1099 1100 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1101 1102 if (err != 0 || newp == NULL) 1103 return err; 1104 1105 return 0; 1106 } 1107 1108 static int 1109 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1110 { 1111 struct sysctlnode node; 1112 uint32_t freq; 1113 int err; 1114 1115 freq = cpufreq_get(curcpu()); 1116 1117 if (freq == 0) 1118 return ENXIO; 1119 1120 node = *rnode; 1121 node.sysctl_data = &freq; 1122 1123 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1124 1125 if (err != 0 || newp == NULL) 1126 return err; 1127 1128 cpufreq_set_all(freq); 1129 1130 return 0; 1131 } 1132 1133 static int 1134 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1135 { 1136 struct cpu_info *ci = curcpu(); 1137 struct acpicpu_softc *sc; 1138 struct sysctlnode node; 1139 char buf[1024]; 1140 size_t len; 1141 uint32_t i; 1142 int err; 1143 1144 sc = acpicpu_sc[ci->ci_acpiid]; 1145 1146 if (sc == NULL) 1147 return ENXIO; 1148 1149 (void)memset(&buf, 0, sizeof(buf)); 1150 1151 mutex_enter(&sc->sc_mtx); 1152 1153 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1154 1155 if (sc->sc_pstate[i].ps_freq == 0) 1156 continue; 1157 1158 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1159 sc->sc_pstate[i].ps_freq, 1160 i < (sc->sc_pstate_count - 1) ? " " : ""); 1161 } 1162 1163 mutex_exit(&sc->sc_mtx); 1164 1165 node = *rnode; 1166 node.sysctl_data = buf; 1167 1168 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1169 1170 if (err != 0 || newp == NULL) 1171 return err; 1172 1173 return 0; 1174 } 1175 1176