1 /* $NetBSD: acpi_cpu_md.c,v 1.61 2011/06/12 10:11:52 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.61 2011/06/12 10:11:52 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/kcore.h> 36 #include <sys/sysctl.h> 37 #include <sys/xcall.h> 38 39 #include <x86/cpu.h> 40 #include <x86/cpufunc.h> 41 #include <x86/cputypes.h> 42 #include <x86/cpuvar.h> 43 #include <x86/cpu_msr.h> 44 #include <x86/machdep.h> 45 46 #include <dev/acpi/acpica.h> 47 #include <dev/acpi/acpi_cpu.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <machine/acpi_machdep.h> 53 54 /* 55 * Intel IA32_MISC_ENABLE. 56 */ 57 #define MSR_MISC_ENABLE_EST __BIT(16) 58 #define MSR_MISC_ENABLE_TURBO __BIT(38) 59 60 /* 61 * AMD C1E. 62 */ 63 #define MSR_CMPHALT 0xc0010055 64 65 #define MSR_CMPHALT_SMI __BIT(27) 66 #define MSR_CMPHALT_C1E __BIT(28) 67 #define MSR_CMPHALT_BMSTS __BIT(29) 68 69 /* 70 * AMD families 10h, 11h, and 14h 71 */ 72 #define MSR_10H_LIMIT 0xc0010061 73 #define MSR_10H_CONTROL 0xc0010062 74 #define MSR_10H_STATUS 0xc0010063 75 #define MSR_10H_CONFIG 0xc0010064 76 77 /* 78 * AMD family 0Fh. 79 */ 80 #define MSR_0FH_CONTROL 0xc0010041 81 #define MSR_0FH_STATUS 0xc0010042 82 83 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 84 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 85 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 86 87 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 88 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 89 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 90 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 91 92 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 93 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 94 95 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 96 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 97 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 98 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 99 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 100 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 101 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 102 103 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 104 105 static char native_idle_text[16]; 106 void (*native_idle)(void) = NULL; 107 108 static int acpicpu_md_quirk_piix4(const struct pci_attach_args *); 109 static void acpicpu_md_pstate_hwf_reset(void *, void *); 110 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 111 uint32_t *); 112 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 113 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 114 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 115 uint32_t, uint32_t); 116 static int acpicpu_md_pstate_sysctl_init(void); 117 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 118 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 119 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 120 121 extern struct acpicpu_softc **acpicpu_sc; 122 static struct sysctllog *acpicpu_log = NULL; 123 124 struct cpu_info * 125 acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct cpufeature_attach_args *cfaa = aux; 128 129 if (strcmp(cfaa->name, "frequency") != 0) 130 return NULL; 131 132 return cfaa->ci; 133 } 134 135 struct cpu_info * 136 acpicpu_md_attach(device_t parent, device_t self, void *aux) 137 { 138 struct cpufeature_attach_args *cfaa = aux; 139 140 return cfaa->ci; 141 } 142 143 uint32_t 144 acpicpu_md_flags(void) 145 { 146 struct cpu_info *ci = curcpu(); 147 struct pci_attach_args pa; 148 uint32_t family, val = 0; 149 uint32_t regs[4]; 150 151 if (acpi_md_ncpus() == 1) 152 val |= ACPICPU_FLAG_C_BM; 153 154 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 155 val |= ACPICPU_FLAG_C_FFH; 156 157 /* 158 * By default, assume that the local APIC timer 159 * as well as TSC are stalled during C3 sleep. 160 */ 161 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 162 163 switch (cpu_vendor) { 164 165 case CPUVENDOR_IDT: 166 167 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 168 val |= ACPICPU_FLAG_P_FFH; 169 170 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 171 val |= ACPICPU_FLAG_T_FFH; 172 173 break; 174 175 case CPUVENDOR_INTEL: 176 177 /* 178 * Bus master control and arbitration should be 179 * available on all supported Intel CPUs (to be 180 * sure, this is double-checked later from the 181 * firmware data). These flags imply that it is 182 * not necessary to flush caches before C3 state. 183 */ 184 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 185 186 /* 187 * Check if we can use "native", MSR-based, 188 * access. If not, we have to resort to I/O. 189 */ 190 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 191 val |= ACPICPU_FLAG_P_FFH; 192 193 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 194 val |= ACPICPU_FLAG_T_FFH; 195 196 /* 197 * Check whether MSR_APERF, MSR_MPERF, and Turbo 198 * Boost are available. Also see if we might have 199 * an invariant local APIC timer ("ARAT"). 200 */ 201 if (cpuid_level >= 0x06) { 202 203 x86_cpuid(0x00000006, regs); 204 205 if ((regs[2] & CPUID_DSPM_HWF) != 0) 206 val |= ACPICPU_FLAG_P_HWF; 207 208 if ((regs[0] & CPUID_DSPM_IDA) != 0) 209 val |= ACPICPU_FLAG_P_TURBO; 210 211 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 212 val &= ~ACPICPU_FLAG_C_APIC; 213 } 214 215 /* 216 * Detect whether TSC is invariant. If it is not, 217 * we keep the flag to note that TSC will not run 218 * at constant rate. Depending on the CPU, this may 219 * affect P- and T-state changes, but especially 220 * relevant are C-states; with variant TSC, states 221 * larger than C1 may completely stop the counter. 222 */ 223 x86_cpuid(0x80000000, regs); 224 225 if (regs[0] >= 0x80000007) { 226 227 x86_cpuid(0x80000007, regs); 228 229 if ((regs[3] & __BIT(8)) != 0) 230 val &= ~ACPICPU_FLAG_C_TSC; 231 } 232 233 break; 234 235 case CPUVENDOR_AMD: 236 237 x86_cpuid(0x80000000, regs); 238 239 if (regs[0] < 0x80000007) 240 break; 241 242 x86_cpuid(0x80000007, regs); 243 244 family = CPUID2FAMILY(ci->ci_signature); 245 246 if (family == 0xf) 247 family += CPUID2EXTFAMILY(ci->ci_signature); 248 249 switch (family) { 250 251 case 0x0f: 252 253 /* 254 * Evaluate support for the "FID/VID 255 * algorithm" also used by powernow(4). 256 */ 257 if ((regs[3] & CPUID_APM_FID) == 0) 258 break; 259 260 if ((regs[3] & CPUID_APM_VID) == 0) 261 break; 262 263 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 264 break; 265 266 case 0x10: 267 case 0x11: 268 val |= ACPICPU_FLAG_C_C1E; 269 /* FALLTHROUGH */ 270 271 case 0x14: /* AMD Fusion */ 272 273 /* 274 * Like with Intel, detect invariant TSC, 275 * MSR-based P-states, and AMD's "turbo" 276 * (Core Performance Boost), respectively. 277 */ 278 if ((regs[3] & CPUID_APM_TSC) != 0) 279 val &= ~ACPICPU_FLAG_C_TSC; 280 281 if ((regs[3] & CPUID_APM_HWP) != 0) 282 val |= ACPICPU_FLAG_P_FFH; 283 284 if ((regs[3] & CPUID_APM_CPB) != 0) 285 val |= ACPICPU_FLAG_P_TURBO; 286 287 /* 288 * Also check for APERF and MPERF, 289 * first available in the family 10h. 290 */ 291 if (cpuid_level >= 0x06) { 292 293 x86_cpuid(0x00000006, regs); 294 295 if ((regs[2] & CPUID_DSPM_HWF) != 0) 296 val |= ACPICPU_FLAG_P_HWF; 297 } 298 299 break; 300 } 301 302 break; 303 } 304 305 /* 306 * There are several erratums for PIIX4. 307 */ 308 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 309 val |= ACPICPU_FLAG_PIIX4; 310 311 return val; 312 } 313 314 static int 315 acpicpu_md_quirk_piix4(const struct pci_attach_args *pa) 316 { 317 318 /* 319 * XXX: The pci_find_device(9) function only 320 * deals with attached devices. Change this 321 * to use something like pci_device_foreach(). 322 */ 323 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 324 return 0; 325 326 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 327 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 328 return 1; 329 330 return 0; 331 } 332 333 void 334 acpicpu_md_quirk_c1e(void) 335 { 336 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 337 uint64_t val; 338 339 val = rdmsr(MSR_CMPHALT); 340 341 if ((val & c1e) != 0) 342 wrmsr(MSR_CMPHALT, val & ~c1e); 343 } 344 345 int 346 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 347 { 348 const size_t size = sizeof(native_idle_text); 349 struct acpicpu_cstate *cs; 350 bool ipi = false; 351 int i; 352 353 /* 354 * Save the cpu_idle(9) loop used by default. 355 */ 356 x86_cpu_idle_get(&native_idle, native_idle_text, size); 357 358 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 359 360 cs = &sc->sc_cstate[i]; 361 362 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 363 ipi = true; 364 break; 365 } 366 } 367 368 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 369 370 return 0; 371 } 372 373 int 374 acpicpu_md_cstate_stop(void) 375 { 376 uint64_t xc; 377 bool ipi; 378 379 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 380 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 381 382 /* 383 * Run a cross-call to ensure that all CPUs are 384 * out from the ACPI idle-loop before detachment. 385 */ 386 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 387 xc_wait(xc); 388 389 return 0; 390 } 391 392 /* 393 * Called with interrupts disabled. 394 * Caller should enable interrupts after return. 395 */ 396 void 397 acpicpu_md_cstate_enter(int method, int state) 398 { 399 struct cpu_info *ci = curcpu(); 400 401 switch (method) { 402 403 case ACPICPU_C_STATE_FFH: 404 405 x86_enable_intr(); 406 x86_monitor(&ci->ci_want_resched, 0, 0); 407 408 if (__predict_false(ci->ci_want_resched != 0)) 409 return; 410 411 x86_mwait((state - 1) << 4, 0); 412 break; 413 414 case ACPICPU_C_STATE_HALT: 415 416 if (__predict_false(ci->ci_want_resched != 0)) 417 return; 418 419 x86_stihlt(); 420 break; 421 } 422 } 423 424 int 425 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 426 { 427 uint64_t xc; 428 429 /* 430 * Reset the APERF and MPERF counters. 431 */ 432 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 433 xc = xc_broadcast(0, acpicpu_md_pstate_hwf_reset, NULL, NULL); 434 xc_wait(xc); 435 } 436 437 return acpicpu_md_pstate_sysctl_init(); 438 } 439 440 int 441 acpicpu_md_pstate_stop(void) 442 { 443 if (acpicpu_log != NULL) 444 sysctl_teardown(&acpicpu_log); 445 446 return 0; 447 } 448 449 int 450 acpicpu_md_pstate_init(struct acpicpu_softc *sc) 451 { 452 struct cpu_info *ci = sc->sc_ci; 453 struct acpicpu_pstate *ps, msr; 454 uint32_t family, i = 0; 455 uint64_t val; 456 457 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 458 459 switch (cpu_vendor) { 460 461 case CPUVENDOR_IDT: 462 case CPUVENDOR_INTEL: 463 464 /* 465 * Make sure EST is enabled. 466 */ 467 if ((sc->sc_flags & ACPICPU_FLAG_P_FFH) != 0) { 468 469 val = rdmsr(MSR_MISC_ENABLE); 470 471 if ((val & MSR_MISC_ENABLE_EST) == 0) { 472 473 val |= MSR_MISC_ENABLE_EST; 474 wrmsr(MSR_MISC_ENABLE, val); 475 val = rdmsr(MSR_MISC_ENABLE); 476 477 if ((val & MSR_MISC_ENABLE_EST) == 0) 478 return ENOTTY; 479 } 480 } 481 482 /* 483 * If the so-called Turbo Boost is present, 484 * the P0-state is always the "turbo state". 485 * It is shown as the P1 frequency + 1 MHz. 486 * 487 * For discussion, see: 488 * 489 * Intel Corporation: Intel Turbo Boost Technology 490 * in Intel Core(tm) Microarchitectures (Nehalem) 491 * Based Processors. White Paper, November 2008. 492 */ 493 if (sc->sc_pstate_count >= 2 && 494 (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 495 496 ps = &sc->sc_pstate[0]; 497 498 if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 499 ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 500 } 501 502 msr.ps_control_addr = MSR_PERF_CTL; 503 msr.ps_control_mask = __BITS(0, 15); 504 505 msr.ps_status_addr = MSR_PERF_STATUS; 506 msr.ps_status_mask = __BITS(0, 15); 507 break; 508 509 case CPUVENDOR_AMD: 510 511 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 512 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 513 514 family = CPUID2FAMILY(ci->ci_signature); 515 516 if (family == 0xf) 517 family += CPUID2EXTFAMILY(ci->ci_signature); 518 519 switch (family) { 520 521 case 0x0f: 522 msr.ps_control_addr = MSR_0FH_CONTROL; 523 msr.ps_status_addr = MSR_0FH_STATUS; 524 break; 525 526 case 0x10: 527 case 0x11: 528 case 0x14: /* AMD Fusion */ 529 msr.ps_control_addr = MSR_10H_CONTROL; 530 msr.ps_control_mask = __BITS(0, 2); 531 532 msr.ps_status_addr = MSR_10H_STATUS; 533 msr.ps_status_mask = __BITS(0, 2); 534 break; 535 536 default: 537 /* 538 * If we have an unknown AMD CPU, rely on XPSS. 539 */ 540 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 541 return EOPNOTSUPP; 542 } 543 544 break; 545 546 default: 547 return ENODEV; 548 } 549 550 /* 551 * Fill the P-state structures with MSR addresses that are 552 * known to be correct. If we do not know the addresses, 553 * leave the values intact. If a vendor uses XPSS, we do 554 * not necessarily need to do anything to support new CPUs. 555 */ 556 while (i < sc->sc_pstate_count) { 557 558 ps = &sc->sc_pstate[i]; 559 560 if (msr.ps_flags != 0) 561 ps->ps_flags |= msr.ps_flags; 562 563 if (msr.ps_status_addr != 0) 564 ps->ps_status_addr = msr.ps_status_addr; 565 566 if (msr.ps_status_mask != 0) 567 ps->ps_status_mask = msr.ps_status_mask; 568 569 if (msr.ps_control_addr != 0) 570 ps->ps_control_addr = msr.ps_control_addr; 571 572 if (msr.ps_control_mask != 0) 573 ps->ps_control_mask = msr.ps_control_mask; 574 575 i++; 576 } 577 578 return 0; 579 } 580 581 /* 582 * Read the IA32_APERF and IA32_MPERF counters. The first 583 * increments at the rate of the fixed maximum frequency 584 * configured during the boot, whereas APERF counts at the 585 * rate of the actual frequency. Note that the MSRs must be 586 * read without delay, and that only the ratio between 587 * IA32_APERF and IA32_MPERF is architecturally defined. 588 * 589 * The function thus returns the percentage of the actual 590 * frequency in terms of the maximum frequency of the calling 591 * CPU since the last call. A value zero implies an error. 592 * 593 * For further details, refer to: 594 * 595 * Intel Corporation: Intel 64 and IA-32 Architectures 596 * Software Developer's Manual. Section 13.2, Volume 3A: 597 * System Programming Guide, Part 1. July, 2008. 598 * 599 * Advanced Micro Devices: BIOS and Kernel Developer's 600 * Guide (BKDG) for AMD Family 10h Processors. Section 601 * 2.4.5, Revision 3.48, April 2010. 602 */ 603 uint8_t 604 acpicpu_md_pstate_hwf(struct cpu_info *ci) 605 { 606 struct acpicpu_softc *sc; 607 uint64_t aperf, mperf; 608 uint8_t rv = 0; 609 610 sc = acpicpu_sc[ci->ci_acpiid]; 611 612 if (__predict_false(sc == NULL)) 613 return 0; 614 615 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 616 return 0; 617 618 aperf = sc->sc_pstate_aperf; 619 mperf = sc->sc_pstate_mperf; 620 621 x86_disable_intr(); 622 623 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 624 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 625 626 x86_enable_intr(); 627 628 aperf = sc->sc_pstate_aperf - aperf; 629 mperf = sc->sc_pstate_mperf - mperf; 630 631 if (__predict_true(mperf != 0)) 632 rv = (aperf * 100) / mperf; 633 634 return rv; 635 } 636 637 static void 638 acpicpu_md_pstate_hwf_reset(void *arg1, void *arg2) 639 { 640 struct cpu_info *ci = curcpu(); 641 struct acpicpu_softc *sc; 642 643 sc = acpicpu_sc[ci->ci_acpiid]; 644 645 if (__predict_false(sc == NULL)) 646 return; 647 648 x86_disable_intr(); 649 650 wrmsr(MSR_APERF, 0); 651 wrmsr(MSR_MPERF, 0); 652 653 x86_enable_intr(); 654 655 sc->sc_pstate_aperf = 0; 656 sc->sc_pstate_mperf = 0; 657 } 658 659 int 660 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 661 { 662 struct acpicpu_pstate *ps = NULL; 663 uint64_t val; 664 uint32_t i; 665 666 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 667 return acpicpu_md_pstate_fidvid_get(sc, freq); 668 669 /* 670 * Pick any P-state for the status address. 671 */ 672 for (i = 0; i < sc->sc_pstate_count; i++) { 673 674 ps = &sc->sc_pstate[i]; 675 676 if (__predict_true(ps->ps_freq != 0)) 677 break; 678 } 679 680 if (__predict_false(ps == NULL)) 681 return ENODEV; 682 683 if (__predict_false(ps->ps_status_addr == 0)) 684 return EINVAL; 685 686 val = rdmsr(ps->ps_status_addr); 687 688 if (__predict_true(ps->ps_status_mask != 0)) 689 val = val & ps->ps_status_mask; 690 691 /* 692 * Search for the value from known P-states. 693 */ 694 for (i = 0; i < sc->sc_pstate_count; i++) { 695 696 ps = &sc->sc_pstate[i]; 697 698 if (__predict_false(ps->ps_freq == 0)) 699 continue; 700 701 if (val == ps->ps_status) { 702 *freq = ps->ps_freq; 703 return 0; 704 } 705 } 706 707 /* 708 * If the value was not found, try APERF/MPERF. 709 * The state is P0 if the return value is 100 %. 710 */ 711 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 712 713 if (acpicpu_md_pstate_hwf(sc->sc_ci) == 100) { 714 *freq = sc->sc_pstate[0].ps_freq; 715 return 0; 716 } 717 } 718 719 return EIO; 720 } 721 722 int 723 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 724 { 725 uint64_t val = 0; 726 727 if (__predict_false(ps->ps_control_addr == 0)) 728 return EINVAL; 729 730 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 731 return acpicpu_md_pstate_fidvid_set(ps); 732 733 /* 734 * If the mask is set, do a read-modify-write. 735 */ 736 if (__predict_true(ps->ps_control_mask != 0)) { 737 val = rdmsr(ps->ps_control_addr); 738 val &= ~ps->ps_control_mask; 739 } 740 741 val |= ps->ps_control; 742 743 wrmsr(ps->ps_control_addr, val); 744 DELAY(ps->ps_latency); 745 746 return 0; 747 } 748 749 static int 750 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 751 { 752 struct acpicpu_pstate *ps; 753 uint32_t fid, i, vid; 754 uint32_t cfid, cvid; 755 int rv; 756 757 /* 758 * AMD family 0Fh needs special treatment. 759 * While it wants to use ACPI, it does not 760 * comply with the ACPI specifications. 761 */ 762 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 763 764 if (rv != 0) 765 return rv; 766 767 for (i = 0; i < sc->sc_pstate_count; i++) { 768 769 ps = &sc->sc_pstate[i]; 770 771 if (__predict_false(ps->ps_freq == 0)) 772 continue; 773 774 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 775 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 776 777 if (cfid == fid && cvid == vid) { 778 *freq = ps->ps_freq; 779 return 0; 780 } 781 } 782 783 return EIO; 784 } 785 786 static int 787 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 788 { 789 const uint64_t ctrl = ps->ps_control; 790 uint32_t cfid, cvid, fid, i, irt; 791 uint32_t pll, vco_cfid, vco_fid; 792 uint32_t val, vid, vst; 793 int rv; 794 795 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 796 797 if (rv != 0) 798 return rv; 799 800 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 801 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 802 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 803 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 804 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 805 806 vst = vst * 20; 807 pll = pll * 1000 / 5; 808 irt = 10 * __BIT(irt); 809 810 /* 811 * Phase 1. 812 */ 813 while (cvid > vid) { 814 815 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 816 val = (val > cvid) ? 0 : cvid - val; 817 818 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 819 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 820 821 if (rv != 0) 822 return rv; 823 } 824 825 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 826 827 for (; i > 0 && cvid > 0; --i) { 828 829 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 830 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 831 832 if (rv != 0) 833 return rv; 834 } 835 836 /* 837 * Phase 2. 838 */ 839 if (cfid != fid) { 840 841 vco_fid = FID_TO_VCO_FID(fid); 842 vco_cfid = FID_TO_VCO_FID(cfid); 843 844 while (abs(vco_fid - vco_cfid) > 2) { 845 846 if (fid <= cfid) 847 val = cfid - 2; 848 else { 849 val = (cfid > 6) ? cfid + 2 : 850 FID_TO_VCO_FID(cfid) + 2; 851 } 852 853 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 854 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 855 856 if (rv != 0) 857 return rv; 858 859 vco_cfid = FID_TO_VCO_FID(cfid); 860 } 861 862 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 863 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 864 865 if (rv != 0) 866 return rv; 867 } 868 869 /* 870 * Phase 3. 871 */ 872 if (cvid != vid) { 873 874 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 875 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 876 877 if (rv != 0) 878 return rv; 879 } 880 881 return 0; 882 } 883 884 static int 885 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 886 { 887 int i = ACPICPU_P_STATE_RETRY * 100; 888 uint64_t val; 889 890 do { 891 val = rdmsr(MSR_0FH_STATUS); 892 893 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 894 895 if (i == 0) 896 return EAGAIN; 897 898 if (cfid != NULL) 899 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 900 901 if (cvid != NULL) 902 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 903 904 return 0; 905 } 906 907 static void 908 acpicpu_md_pstate_fidvid_write(uint32_t fid, 909 uint32_t vid, uint32_t cnt, uint32_t tmo) 910 { 911 uint64_t val = 0; 912 913 val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 914 val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 915 val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 916 val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 917 918 wrmsr(MSR_0FH_CONTROL, val); 919 DELAY(tmo); 920 } 921 922 int 923 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 924 { 925 struct acpicpu_tstate *ts; 926 uint64_t val; 927 uint32_t i; 928 929 val = rdmsr(MSR_THERM_CONTROL); 930 931 for (i = 0; i < sc->sc_tstate_count; i++) { 932 933 ts = &sc->sc_tstate[i]; 934 935 if (ts->ts_percent == 0) 936 continue; 937 938 if (val == ts->ts_status) { 939 *percent = ts->ts_percent; 940 return 0; 941 } 942 } 943 944 return EIO; 945 } 946 947 int 948 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 949 { 950 uint64_t val; 951 uint8_t i; 952 953 val = ts->ts_control; 954 val = val & __BITS(1, 4); 955 956 wrmsr(MSR_THERM_CONTROL, val); 957 958 if (ts->ts_status == 0) { 959 DELAY(ts->ts_latency); 960 return 0; 961 } 962 963 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 964 965 val = rdmsr(MSR_THERM_CONTROL); 966 967 if (val == ts->ts_status) 968 return 0; 969 970 DELAY(ts->ts_latency); 971 } 972 973 return EAGAIN; 974 } 975 976 /* 977 * A kludge for backwards compatibility. 978 */ 979 static int 980 acpicpu_md_pstate_sysctl_init(void) 981 { 982 const struct sysctlnode *fnode, *mnode, *rnode; 983 const char *str; 984 int rv; 985 986 switch (cpu_vendor) { 987 988 case CPUVENDOR_IDT: 989 case CPUVENDOR_INTEL: 990 str = "est"; 991 break; 992 993 case CPUVENDOR_AMD: 994 str = "powernow"; 995 break; 996 997 default: 998 return ENODEV; 999 } 1000 1001 1002 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1003 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1004 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1005 1006 if (rv != 0) 1007 goto fail; 1008 1009 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1010 0, CTLTYPE_NODE, str, NULL, 1011 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1012 1013 if (rv != 0) 1014 goto fail; 1015 1016 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1017 0, CTLTYPE_NODE, "frequency", NULL, 1018 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1019 1020 if (rv != 0) 1021 goto fail; 1022 1023 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1024 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1025 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1026 1027 if (rv != 0) 1028 goto fail; 1029 1030 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1031 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1032 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1033 1034 if (rv != 0) 1035 goto fail; 1036 1037 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1038 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1039 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1040 1041 if (rv != 0) 1042 goto fail; 1043 1044 return 0; 1045 1046 fail: 1047 if (acpicpu_log != NULL) { 1048 sysctl_teardown(&acpicpu_log); 1049 acpicpu_log = NULL; 1050 } 1051 1052 return rv; 1053 } 1054 1055 static int 1056 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1057 { 1058 struct cpu_info *ci = curcpu(); 1059 struct sysctlnode node; 1060 uint32_t freq; 1061 int err; 1062 1063 err = acpicpu_pstate_get(ci, &freq); 1064 1065 if (err != 0) 1066 return err; 1067 1068 node = *rnode; 1069 node.sysctl_data = &freq; 1070 1071 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1072 1073 if (err != 0 || newp == NULL) 1074 return err; 1075 1076 return 0; 1077 } 1078 1079 static int 1080 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1081 { 1082 struct cpu_info *ci = curcpu(); 1083 struct sysctlnode node; 1084 uint32_t freq; 1085 int err; 1086 1087 err = acpicpu_pstate_get(ci, &freq); 1088 1089 if (err != 0) 1090 return err; 1091 1092 node = *rnode; 1093 node.sysctl_data = &freq; 1094 1095 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1096 1097 if (err != 0 || newp == NULL) 1098 return err; 1099 1100 acpicpu_pstate_set(ci, freq); 1101 1102 return 0; 1103 } 1104 1105 static int 1106 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1107 { 1108 struct cpu_info *ci = curcpu(); 1109 struct acpicpu_softc *sc; 1110 struct sysctlnode node; 1111 char buf[1024]; 1112 size_t len; 1113 uint32_t i; 1114 int err; 1115 1116 sc = acpicpu_sc[ci->ci_acpiid]; 1117 1118 if (sc == NULL) 1119 return ENXIO; 1120 1121 (void)memset(&buf, 0, sizeof(buf)); 1122 1123 mutex_enter(&sc->sc_mtx); 1124 1125 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1126 1127 if (sc->sc_pstate[i].ps_freq == 0) 1128 continue; 1129 1130 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1131 sc->sc_pstate[i].ps_freq, 1132 i < (sc->sc_pstate_count - 1) ? " " : ""); 1133 } 1134 1135 mutex_exit(&sc->sc_mtx); 1136 1137 node = *rnode; 1138 node.sysctl_data = buf; 1139 1140 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1141 1142 if (err != 0 || newp == NULL) 1143 return err; 1144 1145 return 0; 1146 } 1147 1148