1 /* $NetBSD: acpi_cpu_md.c,v 1.64 2011/07/13 07:34:55 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.64 2011/07/13 07:34:55 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/kcore.h> 36 #include <sys/sysctl.h> 37 #include <sys/xcall.h> 38 39 #include <x86/cpu.h> 40 #include <x86/cpufunc.h> 41 #include <x86/cputypes.h> 42 #include <x86/cpuvar.h> 43 #include <x86/cpu_msr.h> 44 #include <x86/machdep.h> 45 46 #include <dev/acpi/acpica.h> 47 #include <dev/acpi/acpi_cpu.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <machine/acpi_machdep.h> 53 54 /* 55 * Intel IA32_MISC_ENABLE. 56 */ 57 #define MSR_MISC_ENABLE_EST __BIT(16) 58 #define MSR_MISC_ENABLE_TURBO __BIT(38) 59 60 /* 61 * AMD C1E. 62 */ 63 #define MSR_CMPHALT 0xc0010055 64 65 #define MSR_CMPHALT_SMI __BIT(27) 66 #define MSR_CMPHALT_C1E __BIT(28) 67 #define MSR_CMPHALT_BMSTS __BIT(29) 68 69 /* 70 * AMD families 10h, 11h, and 14h 71 */ 72 #define MSR_10H_LIMIT 0xc0010061 73 #define MSR_10H_CONTROL 0xc0010062 74 #define MSR_10H_STATUS 0xc0010063 75 #define MSR_10H_CONFIG 0xc0010064 76 77 /* 78 * AMD family 0Fh. 79 */ 80 #define MSR_0FH_CONTROL 0xc0010041 81 #define MSR_0FH_STATUS 0xc0010042 82 83 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 84 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 85 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 86 87 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 88 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 89 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 90 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 91 92 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 93 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 94 95 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 96 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 97 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 98 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 99 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 100 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 101 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 102 103 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 104 105 static char native_idle_text[16]; 106 void (*native_idle)(void) = NULL; 107 108 static int acpicpu_md_quirk_piix4(const struct pci_attach_args *); 109 static void acpicpu_md_pstate_hwf_reset(void *, void *); 110 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 111 uint32_t *); 112 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 113 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 114 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 115 uint32_t, uint32_t); 116 static int acpicpu_md_pstate_sysctl_init(void); 117 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 118 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 119 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 120 121 extern struct acpicpu_softc **acpicpu_sc; 122 static struct sysctllog *acpicpu_log = NULL; 123 124 struct cpu_info * 125 acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct cpufeature_attach_args *cfaa = aux; 128 129 if (strcmp(cfaa->name, "frequency") != 0) 130 return NULL; 131 132 return cfaa->ci; 133 } 134 135 struct cpu_info * 136 acpicpu_md_attach(device_t parent, device_t self, void *aux) 137 { 138 struct cpufeature_attach_args *cfaa = aux; 139 140 return cfaa->ci; 141 } 142 143 uint32_t 144 acpicpu_md_flags(void) 145 { 146 struct cpu_info *ci = curcpu(); 147 struct pci_attach_args pa; 148 uint32_t family, val = 0; 149 uint32_t regs[4]; 150 151 if (acpi_md_ncpus() == 1) 152 val |= ACPICPU_FLAG_C_BM; 153 154 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 155 val |= ACPICPU_FLAG_C_FFH; 156 157 /* 158 * By default, assume that the local APIC timer 159 * as well as TSC are stalled during C3 sleep. 160 */ 161 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 162 163 switch (cpu_vendor) { 164 165 case CPUVENDOR_IDT: 166 167 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 168 val |= ACPICPU_FLAG_P_FFH; 169 170 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 171 val |= ACPICPU_FLAG_T_FFH; 172 173 break; 174 175 case CPUVENDOR_INTEL: 176 177 /* 178 * Bus master control and arbitration should be 179 * available on all supported Intel CPUs (to be 180 * sure, this is double-checked later from the 181 * firmware data). These flags imply that it is 182 * not necessary to flush caches before C3 state. 183 */ 184 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 185 186 /* 187 * Check if we can use "native", MSR-based, 188 * access. If not, we have to resort to I/O. 189 */ 190 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 191 val |= ACPICPU_FLAG_P_FFH; 192 193 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 194 val |= ACPICPU_FLAG_T_FFH; 195 196 /* 197 * Check whether MSR_APERF, MSR_MPERF, and Turbo 198 * Boost are available. Also see if we might have 199 * an invariant local APIC timer ("ARAT"). 200 */ 201 if (cpuid_level >= 0x06) { 202 203 x86_cpuid(0x00000006, regs); 204 205 if ((regs[2] & CPUID_DSPM_HWF) != 0) 206 val |= ACPICPU_FLAG_P_HWF; 207 208 if ((regs[0] & CPUID_DSPM_IDA) != 0) 209 val |= ACPICPU_FLAG_P_TURBO; 210 211 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 212 val &= ~ACPICPU_FLAG_C_APIC; 213 } 214 215 /* 216 * Detect whether TSC is invariant. If it is not, 217 * we keep the flag to note that TSC will not run 218 * at constant rate. Depending on the CPU, this may 219 * affect P- and T-state changes, but especially 220 * relevant are C-states; with variant TSC, states 221 * larger than C1 may completely stop the counter. 222 */ 223 x86_cpuid(0x80000000, regs); 224 225 if (regs[0] >= 0x80000007) { 226 227 x86_cpuid(0x80000007, regs); 228 229 if ((regs[3] & __BIT(8)) != 0) 230 val &= ~ACPICPU_FLAG_C_TSC; 231 } 232 233 break; 234 235 case CPUVENDOR_AMD: 236 237 x86_cpuid(0x80000000, regs); 238 239 if (regs[0] < 0x80000007) 240 break; 241 242 x86_cpuid(0x80000007, regs); 243 244 family = CPUID2FAMILY(ci->ci_signature); 245 246 if (family == 0xf) 247 family += CPUID2EXTFAMILY(ci->ci_signature); 248 249 switch (family) { 250 251 case 0x0f: 252 253 /* 254 * Evaluate support for the "FID/VID 255 * algorithm" also used by powernow(4). 256 */ 257 if ((regs[3] & CPUID_APM_FID) == 0) 258 break; 259 260 if ((regs[3] & CPUID_APM_VID) == 0) 261 break; 262 263 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 264 break; 265 266 case 0x10: 267 case 0x11: 268 val |= ACPICPU_FLAG_C_C1E; 269 /* FALLTHROUGH */ 270 271 case 0x14: /* AMD Fusion */ 272 273 /* 274 * Like with Intel, detect invariant TSC, 275 * MSR-based P-states, and AMD's "turbo" 276 * (Core Performance Boost), respectively. 277 */ 278 if ((regs[3] & CPUID_APM_TSC) != 0) 279 val &= ~ACPICPU_FLAG_C_TSC; 280 281 if ((regs[3] & CPUID_APM_HWP) != 0) 282 val |= ACPICPU_FLAG_P_FFH; 283 284 if ((regs[3] & CPUID_APM_CPB) != 0) 285 val |= ACPICPU_FLAG_P_TURBO; 286 287 /* 288 * Also check for APERF and MPERF, 289 * first available in the family 10h. 290 */ 291 if (cpuid_level >= 0x06) { 292 293 x86_cpuid(0x00000006, regs); 294 295 if ((regs[2] & CPUID_DSPM_HWF) != 0) 296 val |= ACPICPU_FLAG_P_HWF; 297 } 298 299 break; 300 } 301 302 break; 303 } 304 305 /* 306 * There are several erratums for PIIX4. 307 */ 308 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 309 val |= ACPICPU_FLAG_PIIX4; 310 311 return val; 312 } 313 314 static int 315 acpicpu_md_quirk_piix4(const struct pci_attach_args *pa) 316 { 317 318 /* 319 * XXX: The pci_find_device(9) function only 320 * deals with attached devices. Change this 321 * to use something like pci_device_foreach(). 322 */ 323 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 324 return 0; 325 326 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 327 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 328 return 1; 329 330 return 0; 331 } 332 333 void 334 acpicpu_md_quirk_c1e(void) 335 { 336 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 337 uint64_t val; 338 339 val = rdmsr(MSR_CMPHALT); 340 341 if ((val & c1e) != 0) 342 wrmsr(MSR_CMPHALT, val & ~c1e); 343 } 344 345 int 346 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 347 { 348 const size_t size = sizeof(native_idle_text); 349 struct acpicpu_cstate *cs; 350 bool ipi = false; 351 int i; 352 353 /* 354 * Save the cpu_idle(9) loop used by default. 355 */ 356 x86_cpu_idle_get(&native_idle, native_idle_text, size); 357 358 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 359 360 cs = &sc->sc_cstate[i]; 361 362 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 363 ipi = true; 364 break; 365 } 366 } 367 368 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 369 370 return 0; 371 } 372 373 int 374 acpicpu_md_cstate_stop(void) 375 { 376 static char text[16]; 377 void (*func)(void); 378 uint64_t xc; 379 bool ipi; 380 381 x86_cpu_idle_get(&func, text, sizeof(text)); 382 383 if (func == native_idle) 384 return EALREADY; 385 386 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 387 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 388 389 /* 390 * Run a cross-call to ensure that all CPUs are 391 * out from the ACPI idle-loop before detachment. 392 */ 393 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 394 xc_wait(xc); 395 396 return 0; 397 } 398 399 /* 400 * Called with interrupts enabled. 401 */ 402 void 403 acpicpu_md_cstate_enter(int method, int state) 404 { 405 struct cpu_info *ci = curcpu(); 406 407 KASSERT(ci->ci_ilevel == IPL_NONE); 408 409 switch (method) { 410 411 case ACPICPU_C_STATE_FFH: 412 413 x86_monitor(&ci->ci_want_resched, 0, 0); 414 415 if (__predict_false(ci->ci_want_resched != 0)) 416 return; 417 418 x86_mwait((state - 1) << 4, 0); 419 break; 420 421 case ACPICPU_C_STATE_HALT: 422 423 x86_disable_intr(); 424 425 if (__predict_false(ci->ci_want_resched != 0)) { 426 x86_enable_intr(); 427 return; 428 } 429 430 x86_stihlt(); 431 break; 432 } 433 } 434 435 int 436 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 437 { 438 uint64_t xc, val; 439 440 switch (cpu_vendor) { 441 442 case CPUVENDOR_IDT: 443 case CPUVENDOR_INTEL: 444 445 /* 446 * Make sure EST is enabled. 447 */ 448 if ((sc->sc_flags & ACPICPU_FLAG_P_FFH) != 0) { 449 450 val = rdmsr(MSR_MISC_ENABLE); 451 452 if ((val & MSR_MISC_ENABLE_EST) == 0) { 453 454 val |= MSR_MISC_ENABLE_EST; 455 wrmsr(MSR_MISC_ENABLE, val); 456 val = rdmsr(MSR_MISC_ENABLE); 457 458 if ((val & MSR_MISC_ENABLE_EST) == 0) 459 return ENOTTY; 460 } 461 } 462 } 463 464 /* 465 * Reset the APERF and MPERF counters. 466 */ 467 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 468 xc = xc_broadcast(0, acpicpu_md_pstate_hwf_reset, NULL, NULL); 469 xc_wait(xc); 470 } 471 472 return acpicpu_md_pstate_sysctl_init(); 473 } 474 475 int 476 acpicpu_md_pstate_stop(void) 477 { 478 479 if (acpicpu_log == NULL) 480 return EALREADY; 481 482 sysctl_teardown(&acpicpu_log); 483 acpicpu_log = NULL; 484 485 return 0; 486 } 487 488 int 489 acpicpu_md_pstate_init(struct acpicpu_softc *sc) 490 { 491 struct cpu_info *ci = sc->sc_ci; 492 struct acpicpu_pstate *ps, msr; 493 uint32_t family, i = 0; 494 495 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 496 497 switch (cpu_vendor) { 498 499 case CPUVENDOR_IDT: 500 case CPUVENDOR_INTEL: 501 502 /* 503 * If the so-called Turbo Boost is present, 504 * the P0-state is always the "turbo state". 505 * It is shown as the P1 frequency + 1 MHz. 506 * 507 * For discussion, see: 508 * 509 * Intel Corporation: Intel Turbo Boost Technology 510 * in Intel Core(tm) Microarchitectures (Nehalem) 511 * Based Processors. White Paper, November 2008. 512 */ 513 if (sc->sc_pstate_count >= 2 && 514 (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 515 516 ps = &sc->sc_pstate[0]; 517 518 if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 519 ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 520 } 521 522 msr.ps_control_addr = MSR_PERF_CTL; 523 msr.ps_control_mask = __BITS(0, 15); 524 525 msr.ps_status_addr = MSR_PERF_STATUS; 526 msr.ps_status_mask = __BITS(0, 15); 527 break; 528 529 case CPUVENDOR_AMD: 530 531 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 532 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 533 534 family = CPUID2FAMILY(ci->ci_signature); 535 536 if (family == 0xf) 537 family += CPUID2EXTFAMILY(ci->ci_signature); 538 539 switch (family) { 540 541 case 0x0f: 542 msr.ps_control_addr = MSR_0FH_CONTROL; 543 msr.ps_status_addr = MSR_0FH_STATUS; 544 break; 545 546 case 0x10: 547 case 0x11: 548 case 0x14: /* AMD Fusion */ 549 msr.ps_control_addr = MSR_10H_CONTROL; 550 msr.ps_control_mask = __BITS(0, 2); 551 552 msr.ps_status_addr = MSR_10H_STATUS; 553 msr.ps_status_mask = __BITS(0, 2); 554 break; 555 556 default: 557 /* 558 * If we have an unknown AMD CPU, rely on XPSS. 559 */ 560 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 561 return EOPNOTSUPP; 562 } 563 564 break; 565 566 default: 567 return ENODEV; 568 } 569 570 /* 571 * Fill the P-state structures with MSR addresses that are 572 * known to be correct. If we do not know the addresses, 573 * leave the values intact. If a vendor uses XPSS, we do 574 * not necessarily need to do anything to support new CPUs. 575 */ 576 while (i < sc->sc_pstate_count) { 577 578 ps = &sc->sc_pstate[i]; 579 580 if (msr.ps_flags != 0) 581 ps->ps_flags |= msr.ps_flags; 582 583 if (msr.ps_status_addr != 0) 584 ps->ps_status_addr = msr.ps_status_addr; 585 586 if (msr.ps_status_mask != 0) 587 ps->ps_status_mask = msr.ps_status_mask; 588 589 if (msr.ps_control_addr != 0) 590 ps->ps_control_addr = msr.ps_control_addr; 591 592 if (msr.ps_control_mask != 0) 593 ps->ps_control_mask = msr.ps_control_mask; 594 595 i++; 596 } 597 598 return 0; 599 } 600 601 /* 602 * Read the IA32_APERF and IA32_MPERF counters. The first 603 * increments at the rate of the fixed maximum frequency 604 * configured during the boot, whereas APERF counts at the 605 * rate of the actual frequency. Note that the MSRs must be 606 * read without delay, and that only the ratio between 607 * IA32_APERF and IA32_MPERF is architecturally defined. 608 * 609 * The function thus returns the percentage of the actual 610 * frequency in terms of the maximum frequency of the calling 611 * CPU since the last call. A value zero implies an error. 612 * 613 * For further details, refer to: 614 * 615 * Intel Corporation: Intel 64 and IA-32 Architectures 616 * Software Developer's Manual. Section 13.2, Volume 3A: 617 * System Programming Guide, Part 1. July, 2008. 618 * 619 * Advanced Micro Devices: BIOS and Kernel Developer's 620 * Guide (BKDG) for AMD Family 10h Processors. Section 621 * 2.4.5, Revision 3.48, April 2010. 622 */ 623 uint8_t 624 acpicpu_md_pstate_hwf(struct cpu_info *ci) 625 { 626 struct acpicpu_softc *sc; 627 uint64_t aperf, mperf; 628 uint8_t rv = 0; 629 630 sc = acpicpu_sc[ci->ci_acpiid]; 631 632 if (__predict_false(sc == NULL)) 633 return 0; 634 635 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 636 return 0; 637 638 aperf = sc->sc_pstate_aperf; 639 mperf = sc->sc_pstate_mperf; 640 641 x86_disable_intr(); 642 643 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 644 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 645 646 x86_enable_intr(); 647 648 aperf = sc->sc_pstate_aperf - aperf; 649 mperf = sc->sc_pstate_mperf - mperf; 650 651 if (__predict_true(mperf != 0)) 652 rv = (aperf * 100) / mperf; 653 654 return rv; 655 } 656 657 static void 658 acpicpu_md_pstate_hwf_reset(void *arg1, void *arg2) 659 { 660 struct cpu_info *ci = curcpu(); 661 struct acpicpu_softc *sc; 662 663 sc = acpicpu_sc[ci->ci_acpiid]; 664 665 if (__predict_false(sc == NULL)) 666 return; 667 668 x86_disable_intr(); 669 670 wrmsr(MSR_APERF, 0); 671 wrmsr(MSR_MPERF, 0); 672 673 x86_enable_intr(); 674 675 sc->sc_pstate_aperf = 0; 676 sc->sc_pstate_mperf = 0; 677 } 678 679 int 680 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 681 { 682 struct acpicpu_pstate *ps = NULL; 683 uint64_t val; 684 uint32_t i; 685 686 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 687 return acpicpu_md_pstate_fidvid_get(sc, freq); 688 689 /* 690 * Pick any P-state for the status address. 691 */ 692 for (i = 0; i < sc->sc_pstate_count; i++) { 693 694 ps = &sc->sc_pstate[i]; 695 696 if (__predict_true(ps->ps_freq != 0)) 697 break; 698 } 699 700 if (__predict_false(ps == NULL)) 701 return ENODEV; 702 703 if (__predict_false(ps->ps_status_addr == 0)) 704 return EINVAL; 705 706 val = rdmsr(ps->ps_status_addr); 707 708 if (__predict_true(ps->ps_status_mask != 0)) 709 val = val & ps->ps_status_mask; 710 711 /* 712 * Search for the value from known P-states. 713 */ 714 for (i = 0; i < sc->sc_pstate_count; i++) { 715 716 ps = &sc->sc_pstate[i]; 717 718 if (__predict_false(ps->ps_freq == 0)) 719 continue; 720 721 if (val == ps->ps_status) { 722 *freq = ps->ps_freq; 723 return 0; 724 } 725 } 726 727 /* 728 * If the value was not found, try APERF/MPERF. 729 * The state is P0 if the return value is 100 %. 730 */ 731 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 732 733 if (acpicpu_md_pstate_hwf(sc->sc_ci) == 100) { 734 *freq = sc->sc_pstate[0].ps_freq; 735 return 0; 736 } 737 } 738 739 return EIO; 740 } 741 742 int 743 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 744 { 745 uint64_t val = 0; 746 747 if (__predict_false(ps->ps_control_addr == 0)) 748 return EINVAL; 749 750 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 751 return acpicpu_md_pstate_fidvid_set(ps); 752 753 /* 754 * If the mask is set, do a read-modify-write. 755 */ 756 if (__predict_true(ps->ps_control_mask != 0)) { 757 val = rdmsr(ps->ps_control_addr); 758 val &= ~ps->ps_control_mask; 759 } 760 761 val |= ps->ps_control; 762 763 wrmsr(ps->ps_control_addr, val); 764 DELAY(ps->ps_latency); 765 766 return 0; 767 } 768 769 static int 770 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 771 { 772 struct acpicpu_pstate *ps; 773 uint32_t fid, i, vid; 774 uint32_t cfid, cvid; 775 int rv; 776 777 /* 778 * AMD family 0Fh needs special treatment. 779 * While it wants to use ACPI, it does not 780 * comply with the ACPI specifications. 781 */ 782 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 783 784 if (rv != 0) 785 return rv; 786 787 for (i = 0; i < sc->sc_pstate_count; i++) { 788 789 ps = &sc->sc_pstate[i]; 790 791 if (__predict_false(ps->ps_freq == 0)) 792 continue; 793 794 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 795 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 796 797 if (cfid == fid && cvid == vid) { 798 *freq = ps->ps_freq; 799 return 0; 800 } 801 } 802 803 return EIO; 804 } 805 806 static int 807 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 808 { 809 const uint64_t ctrl = ps->ps_control; 810 uint32_t cfid, cvid, fid, i, irt; 811 uint32_t pll, vco_cfid, vco_fid; 812 uint32_t val, vid, vst; 813 int rv; 814 815 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 816 817 if (rv != 0) 818 return rv; 819 820 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 821 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 822 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 823 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 824 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 825 826 vst = vst * 20; 827 pll = pll * 1000 / 5; 828 irt = 10 * __BIT(irt); 829 830 /* 831 * Phase 1. 832 */ 833 while (cvid > vid) { 834 835 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 836 val = (val > cvid) ? 0 : cvid - val; 837 838 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 839 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 840 841 if (rv != 0) 842 return rv; 843 } 844 845 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 846 847 for (; i > 0 && cvid > 0; --i) { 848 849 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 850 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 851 852 if (rv != 0) 853 return rv; 854 } 855 856 /* 857 * Phase 2. 858 */ 859 if (cfid != fid) { 860 861 vco_fid = FID_TO_VCO_FID(fid); 862 vco_cfid = FID_TO_VCO_FID(cfid); 863 864 while (abs(vco_fid - vco_cfid) > 2) { 865 866 if (fid <= cfid) 867 val = cfid - 2; 868 else { 869 val = (cfid > 6) ? cfid + 2 : 870 FID_TO_VCO_FID(cfid) + 2; 871 } 872 873 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 874 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 875 876 if (rv != 0) 877 return rv; 878 879 vco_cfid = FID_TO_VCO_FID(cfid); 880 } 881 882 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 883 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 884 885 if (rv != 0) 886 return rv; 887 } 888 889 /* 890 * Phase 3. 891 */ 892 if (cvid != vid) { 893 894 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 895 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 896 897 if (rv != 0) 898 return rv; 899 } 900 901 return 0; 902 } 903 904 static int 905 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 906 { 907 int i = ACPICPU_P_STATE_RETRY * 100; 908 uint64_t val; 909 910 do { 911 val = rdmsr(MSR_0FH_STATUS); 912 913 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 914 915 if (i == 0) 916 return EAGAIN; 917 918 if (cfid != NULL) 919 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 920 921 if (cvid != NULL) 922 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 923 924 return 0; 925 } 926 927 static void 928 acpicpu_md_pstate_fidvid_write(uint32_t fid, 929 uint32_t vid, uint32_t cnt, uint32_t tmo) 930 { 931 uint64_t val = 0; 932 933 val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 934 val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 935 val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 936 val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 937 938 wrmsr(MSR_0FH_CONTROL, val); 939 DELAY(tmo); 940 } 941 942 int 943 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 944 { 945 struct acpicpu_tstate *ts; 946 uint64_t val; 947 uint32_t i; 948 949 val = rdmsr(MSR_THERM_CONTROL); 950 951 for (i = 0; i < sc->sc_tstate_count; i++) { 952 953 ts = &sc->sc_tstate[i]; 954 955 if (ts->ts_percent == 0) 956 continue; 957 958 if (val == ts->ts_status) { 959 *percent = ts->ts_percent; 960 return 0; 961 } 962 } 963 964 return EIO; 965 } 966 967 int 968 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 969 { 970 uint64_t val; 971 uint8_t i; 972 973 val = ts->ts_control; 974 val = val & __BITS(1, 4); 975 976 wrmsr(MSR_THERM_CONTROL, val); 977 978 if (ts->ts_status == 0) { 979 DELAY(ts->ts_latency); 980 return 0; 981 } 982 983 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 984 985 val = rdmsr(MSR_THERM_CONTROL); 986 987 if (val == ts->ts_status) 988 return 0; 989 990 DELAY(ts->ts_latency); 991 } 992 993 return EAGAIN; 994 } 995 996 /* 997 * A kludge for backwards compatibility. 998 */ 999 static int 1000 acpicpu_md_pstate_sysctl_init(void) 1001 { 1002 const struct sysctlnode *fnode, *mnode, *rnode; 1003 const char *str; 1004 int rv; 1005 1006 switch (cpu_vendor) { 1007 1008 case CPUVENDOR_IDT: 1009 case CPUVENDOR_INTEL: 1010 str = "est"; 1011 break; 1012 1013 case CPUVENDOR_AMD: 1014 str = "powernow"; 1015 break; 1016 1017 default: 1018 return ENODEV; 1019 } 1020 1021 1022 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1023 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1024 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1025 1026 if (rv != 0) 1027 goto fail; 1028 1029 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1030 0, CTLTYPE_NODE, str, NULL, 1031 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1032 1033 if (rv != 0) 1034 goto fail; 1035 1036 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1037 0, CTLTYPE_NODE, "frequency", NULL, 1038 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1039 1040 if (rv != 0) 1041 goto fail; 1042 1043 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1044 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1045 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1046 1047 if (rv != 0) 1048 goto fail; 1049 1050 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1051 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1052 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1053 1054 if (rv != 0) 1055 goto fail; 1056 1057 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1058 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1059 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1060 1061 if (rv != 0) 1062 goto fail; 1063 1064 return 0; 1065 1066 fail: 1067 if (acpicpu_log != NULL) { 1068 sysctl_teardown(&acpicpu_log); 1069 acpicpu_log = NULL; 1070 } 1071 1072 return rv; 1073 } 1074 1075 static int 1076 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1077 { 1078 struct cpu_info *ci = curcpu(); 1079 struct sysctlnode node; 1080 uint32_t freq; 1081 int err; 1082 1083 err = acpicpu_pstate_get(ci, &freq); 1084 1085 if (err != 0) 1086 return err; 1087 1088 node = *rnode; 1089 node.sysctl_data = &freq; 1090 1091 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1092 1093 if (err != 0 || newp == NULL) 1094 return err; 1095 1096 return 0; 1097 } 1098 1099 static int 1100 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1101 { 1102 struct cpu_info *ci = curcpu(); 1103 struct sysctlnode node; 1104 uint32_t freq; 1105 int err; 1106 1107 err = acpicpu_pstate_get(ci, &freq); 1108 1109 if (err != 0) 1110 return err; 1111 1112 node = *rnode; 1113 node.sysctl_data = &freq; 1114 1115 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1116 1117 if (err != 0 || newp == NULL) 1118 return err; 1119 1120 acpicpu_pstate_set(ci, freq); 1121 1122 return 0; 1123 } 1124 1125 static int 1126 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1127 { 1128 struct cpu_info *ci = curcpu(); 1129 struct acpicpu_softc *sc; 1130 struct sysctlnode node; 1131 char buf[1024]; 1132 size_t len; 1133 uint32_t i; 1134 int err; 1135 1136 sc = acpicpu_sc[ci->ci_acpiid]; 1137 1138 if (sc == NULL) 1139 return ENXIO; 1140 1141 (void)memset(&buf, 0, sizeof(buf)); 1142 1143 mutex_enter(&sc->sc_mtx); 1144 1145 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1146 1147 if (sc->sc_pstate[i].ps_freq == 0) 1148 continue; 1149 1150 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1151 sc->sc_pstate[i].ps_freq, 1152 i < (sc->sc_pstate_count - 1) ? " " : ""); 1153 } 1154 1155 mutex_exit(&sc->sc_mtx); 1156 1157 node = *rnode; 1158 node.sysctl_data = buf; 1159 1160 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1161 1162 if (err != 0 || newp == NULL) 1163 return err; 1164 1165 return 0; 1166 } 1167 1168