1 /* $NetBSD: acpi_cpu_md.c,v 1.58 2011/04/04 20:37:55 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.58 2011/04/04 20:37:55 dyoung Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/kcore.h> 36 #include <sys/sysctl.h> 37 #include <sys/xcall.h> 38 39 #include <x86/cpu.h> 40 #include <x86/cpufunc.h> 41 #include <x86/cputypes.h> 42 #include <x86/cpuvar.h> 43 #include <x86/cpu_msr.h> 44 #include <x86/machdep.h> 45 46 #include <dev/acpi/acpica.h> 47 #include <dev/acpi/acpi_cpu.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <machine/acpi_machdep.h> 53 54 /* 55 * Intel IA32_MISC_ENABLE. 56 */ 57 #define MSR_MISC_ENABLE_EST __BIT(16) 58 #define MSR_MISC_ENABLE_TURBO __BIT(38) 59 60 /* 61 * AMD C1E. 62 */ 63 #define MSR_CMPHALT 0xc0010055 64 65 #define MSR_CMPHALT_SMI __BIT(27) 66 #define MSR_CMPHALT_C1E __BIT(28) 67 #define MSR_CMPHALT_BMSTS __BIT(29) 68 69 /* 70 * AMD families 10h, 11h, and 14h 71 */ 72 #define MSR_10H_LIMIT 0xc0010061 73 #define MSR_10H_CONTROL 0xc0010062 74 #define MSR_10H_STATUS 0xc0010063 75 #define MSR_10H_CONFIG 0xc0010064 76 77 /* 78 * AMD family 0Fh. 79 */ 80 #define MSR_0FH_CONTROL 0xc0010041 81 #define MSR_0FH_STATUS 0xc0010042 82 83 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 84 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 85 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 86 87 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 88 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 89 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 90 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 91 92 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 93 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 94 95 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 96 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 97 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 98 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 99 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 100 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 101 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 102 103 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 104 105 static char native_idle_text[16]; 106 void (*native_idle)(void) = NULL; 107 108 static int acpicpu_md_quirk_piix4(const struct pci_attach_args *); 109 static void acpicpu_md_pstate_hwf_reset(void *, void *); 110 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 111 uint32_t *); 112 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 113 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 114 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 115 uint32_t, uint32_t); 116 static int acpicpu_md_pstate_sysctl_init(void); 117 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 118 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 119 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 120 121 extern struct acpicpu_softc **acpicpu_sc; 122 static struct sysctllog *acpicpu_log = NULL; 123 124 struct cpu_info * 125 acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct cpufeature_attach_args *cfaa = aux; 128 129 if (strcmp(cfaa->name, "frequency") != 0) 130 return NULL; 131 132 return cfaa->ci; 133 } 134 135 struct cpu_info * 136 acpicpu_md_attach(device_t parent, device_t self, void *aux) 137 { 138 struct cpufeature_attach_args *cfaa = aux; 139 140 return cfaa->ci; 141 } 142 143 uint32_t 144 acpicpu_md_cap(void) 145 { 146 struct cpu_info *ci = curcpu(); 147 uint32_t regs[4]; 148 uint32_t val = 0; 149 150 if (cpu_vendor != CPUVENDOR_IDT && 151 cpu_vendor != CPUVENDOR_INTEL) 152 return val; 153 154 /* 155 * Basic SMP C-states (required for e.g. _CST). 156 */ 157 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 158 159 /* 160 * Claim to support dependency coordination. 161 */ 162 val |= ACPICPU_PDC_P_SW | ACPICPU_PDC_C_SW | ACPICPU_PDC_T_SW; 163 164 /* 165 * If MONITOR/MWAIT is available, announce 166 * support for native instructions in all C-states. 167 */ 168 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 169 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 170 171 /* 172 * Set native P- and T-states, if available. 173 */ 174 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 175 val |= ACPICPU_PDC_P_FFH; 176 177 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 178 val |= ACPICPU_PDC_T_FFH; 179 180 /* 181 * Declare support for APERF and MPERF. 182 */ 183 if (cpuid_level >= 0x06) { 184 185 x86_cpuid(0x00000006, regs); 186 187 if ((regs[2] & CPUID_DSPM_HWF) != 0) 188 val |= ACPICPU_PDC_P_HWF; 189 } 190 191 return val; 192 } 193 194 uint32_t 195 acpicpu_md_flags(void) 196 { 197 struct cpu_info *ci = curcpu(); 198 struct pci_attach_args pa; 199 uint32_t family, val = 0; 200 uint32_t regs[4]; 201 202 if (acpi_md_ncpus() == 1) 203 val |= ACPICPU_FLAG_C_BM; 204 205 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 206 val |= ACPICPU_FLAG_C_FFH; 207 208 /* 209 * By default, assume that the local APIC timer 210 * as well as TSC are stalled during C3 sleep. 211 */ 212 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 213 214 switch (cpu_vendor) { 215 216 case CPUVENDOR_IDT: 217 218 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 219 val |= ACPICPU_FLAG_P_FFH; 220 221 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 222 val |= ACPICPU_FLAG_T_FFH; 223 224 break; 225 226 case CPUVENDOR_INTEL: 227 228 /* 229 * Bus master control and arbitration should be 230 * available on all supported Intel CPUs (to be 231 * sure, this is double-checked later from the 232 * firmware data). These flags imply that it is 233 * not necessary to flush caches before C3 state. 234 */ 235 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 236 237 /* 238 * Check if we can use "native", MSR-based, 239 * access. If not, we have to resort to I/O. 240 */ 241 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 242 val |= ACPICPU_FLAG_P_FFH; 243 244 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 245 val |= ACPICPU_FLAG_T_FFH; 246 247 /* 248 * Check whether MSR_APERF, MSR_MPERF, and Turbo 249 * Boost are available. Also see if we might have 250 * an invariant local APIC timer ("ARAT"). 251 */ 252 if (cpuid_level >= 0x06) { 253 254 x86_cpuid(0x00000006, regs); 255 256 if ((regs[2] & CPUID_DSPM_HWF) != 0) 257 val |= ACPICPU_FLAG_P_HWF; 258 259 if ((regs[0] & CPUID_DSPM_IDA) != 0) 260 val |= ACPICPU_FLAG_P_TURBO; 261 262 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 263 val &= ~ACPICPU_FLAG_C_APIC; 264 } 265 266 /* 267 * Detect whether TSC is invariant. If it is not, 268 * we keep the flag to note that TSC will not run 269 * at constant rate. Depending on the CPU, this may 270 * affect P- and T-state changes, but especially 271 * relevant are C-states; with variant TSC, states 272 * larger than C1 may completely stop the counter. 273 */ 274 x86_cpuid(0x80000000, regs); 275 276 if (regs[0] >= 0x80000007) { 277 278 x86_cpuid(0x80000007, regs); 279 280 if ((regs[3] & __BIT(8)) != 0) 281 val &= ~ACPICPU_FLAG_C_TSC; 282 } 283 284 break; 285 286 case CPUVENDOR_AMD: 287 288 x86_cpuid(0x80000000, regs); 289 290 if (regs[0] < 0x80000007) 291 break; 292 293 x86_cpuid(0x80000007, regs); 294 295 family = CPUID2FAMILY(ci->ci_signature); 296 297 if (family == 0xf) 298 family += CPUID2EXTFAMILY(ci->ci_signature); 299 300 switch (family) { 301 302 case 0x0f: 303 304 /* 305 * Evaluate support for the "FID/VID 306 * algorithm" also used by powernow(4). 307 */ 308 if ((regs[3] & CPUID_APM_FID) == 0) 309 break; 310 311 if ((regs[3] & CPUID_APM_VID) == 0) 312 break; 313 314 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 315 break; 316 317 case 0x10: 318 case 0x11: 319 val |= ACPICPU_FLAG_C_C1E; 320 /* FALLTHROUGH */ 321 322 case 0x14: /* AMD Fusion */ 323 324 /* 325 * Like with Intel, detect invariant TSC, 326 * MSR-based P-states, and AMD's "turbo" 327 * (Core Performance Boost), respectively. 328 */ 329 if ((regs[3] & CPUID_APM_TSC) != 0) 330 val &= ~ACPICPU_FLAG_C_TSC; 331 332 if ((regs[3] & CPUID_APM_HWP) != 0) 333 val |= ACPICPU_FLAG_P_FFH; 334 335 if ((regs[3] & CPUID_APM_CPB) != 0) 336 val |= ACPICPU_FLAG_P_TURBO; 337 338 /* 339 * Also check for APERF and MPERF, 340 * first available in the family 10h. 341 */ 342 if (cpuid_level >= 0x06) { 343 344 x86_cpuid(0x00000006, regs); 345 346 if ((regs[2] & CPUID_DSPM_HWF) != 0) 347 val |= ACPICPU_FLAG_P_HWF; 348 } 349 350 break; 351 } 352 353 break; 354 } 355 356 /* 357 * There are several erratums for PIIX4. 358 */ 359 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 360 val |= ACPICPU_FLAG_PIIX4; 361 362 return val; 363 } 364 365 static int 366 acpicpu_md_quirk_piix4(const struct pci_attach_args *pa) 367 { 368 369 /* 370 * XXX: The pci_find_device(9) function only 371 * deals with attached devices. Change this 372 * to use something like pci_device_foreach(). 373 */ 374 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 375 return 0; 376 377 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 378 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 379 return 1; 380 381 return 0; 382 } 383 384 void 385 acpicpu_md_quirk_c1e(void) 386 { 387 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 388 uint64_t val; 389 390 val = rdmsr(MSR_CMPHALT); 391 392 if ((val & c1e) != 0) 393 wrmsr(MSR_CMPHALT, val & ~c1e); 394 } 395 396 int 397 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 398 { 399 const size_t size = sizeof(native_idle_text); 400 struct acpicpu_cstate *cs; 401 bool ipi = false; 402 int i; 403 404 /* 405 * Save the cpu_idle(9) loop used by default. 406 */ 407 x86_cpu_idle_get(&native_idle, native_idle_text, size); 408 409 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 410 411 cs = &sc->sc_cstate[i]; 412 413 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 414 ipi = true; 415 break; 416 } 417 } 418 419 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 420 421 return 0; 422 } 423 424 int 425 acpicpu_md_cstate_stop(void) 426 { 427 uint64_t xc; 428 bool ipi; 429 430 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 431 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 432 433 /* 434 * Run a cross-call to ensure that all CPUs are 435 * out from the ACPI idle-loop before detachment. 436 */ 437 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 438 xc_wait(xc); 439 440 return 0; 441 } 442 443 /* 444 * Called with interrupts disabled. 445 * Caller should enable interrupts after return. 446 */ 447 void 448 acpicpu_md_cstate_enter(int method, int state) 449 { 450 struct cpu_info *ci = curcpu(); 451 452 switch (method) { 453 454 case ACPICPU_C_STATE_FFH: 455 456 x86_enable_intr(); 457 x86_monitor(&ci->ci_want_resched, 0, 0); 458 459 if (__predict_false(ci->ci_want_resched != 0)) 460 return; 461 462 x86_mwait((state - 1) << 4, 0); 463 break; 464 465 case ACPICPU_C_STATE_HALT: 466 467 if (__predict_false(ci->ci_want_resched != 0)) 468 return; 469 470 x86_stihlt(); 471 break; 472 } 473 } 474 475 int 476 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 477 { 478 uint64_t xc; 479 480 /* 481 * Reset the APERF and MPERF counters. 482 */ 483 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 484 xc = xc_broadcast(0, acpicpu_md_pstate_hwf_reset, NULL, NULL); 485 xc_wait(xc); 486 } 487 488 return acpicpu_md_pstate_sysctl_init(); 489 } 490 491 int 492 acpicpu_md_pstate_stop(void) 493 { 494 if (acpicpu_log != NULL) 495 sysctl_teardown(&acpicpu_log); 496 497 return 0; 498 } 499 500 int 501 acpicpu_md_pstate_init(struct acpicpu_softc *sc) 502 { 503 struct cpu_info *ci = sc->sc_ci; 504 struct acpicpu_pstate *ps, msr; 505 uint32_t family, i = 0; 506 uint64_t val; 507 508 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 509 510 switch (cpu_vendor) { 511 512 case CPUVENDOR_IDT: 513 case CPUVENDOR_INTEL: 514 515 /* 516 * Make sure EST is enabled. 517 */ 518 if ((sc->sc_flags & ACPICPU_FLAG_P_FFH) != 0) { 519 520 val = rdmsr(MSR_MISC_ENABLE); 521 522 if ((val & MSR_MISC_ENABLE_EST) == 0) { 523 524 val |= MSR_MISC_ENABLE_EST; 525 wrmsr(MSR_MISC_ENABLE, val); 526 val = rdmsr(MSR_MISC_ENABLE); 527 528 if ((val & MSR_MISC_ENABLE_EST) == 0) 529 return ENOTTY; 530 } 531 } 532 533 /* 534 * If the so-called Turbo Boost is present, 535 * the P0-state is always the "turbo state". 536 * It is shown as the P1 frequency + 1 MHz. 537 * 538 * For discussion, see: 539 * 540 * Intel Corporation: Intel Turbo Boost Technology 541 * in Intel Core(tm) Microarchitectures (Nehalem) 542 * Based Processors. White Paper, November 2008. 543 */ 544 if (sc->sc_pstate_count >= 2 && 545 (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 546 547 ps = &sc->sc_pstate[0]; 548 549 if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 550 ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 551 } 552 553 msr.ps_control_addr = MSR_PERF_CTL; 554 msr.ps_control_mask = __BITS(0, 15); 555 556 msr.ps_status_addr = MSR_PERF_STATUS; 557 msr.ps_status_mask = __BITS(0, 15); 558 break; 559 560 case CPUVENDOR_AMD: 561 562 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 563 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 564 565 family = CPUID2FAMILY(ci->ci_signature); 566 567 if (family == 0xf) 568 family += CPUID2EXTFAMILY(ci->ci_signature); 569 570 switch (family) { 571 572 case 0x0f: 573 msr.ps_control_addr = MSR_0FH_CONTROL; 574 msr.ps_status_addr = MSR_0FH_STATUS; 575 break; 576 577 case 0x10: 578 case 0x11: 579 case 0x14: /* AMD Fusion */ 580 msr.ps_control_addr = MSR_10H_CONTROL; 581 msr.ps_control_mask = __BITS(0, 2); 582 583 msr.ps_status_addr = MSR_10H_STATUS; 584 msr.ps_status_mask = __BITS(0, 2); 585 break; 586 587 default: 588 /* 589 * If we have an unknown AMD CPU, rely on XPSS. 590 */ 591 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 592 return EOPNOTSUPP; 593 } 594 595 break; 596 597 default: 598 return ENODEV; 599 } 600 601 /* 602 * Fill the P-state structures with MSR addresses that are 603 * known to be correct. If we do not know the addresses, 604 * leave the values intact. If a vendor uses XPSS, we do 605 * not necessarily need to do anything to support new CPUs. 606 */ 607 while (i < sc->sc_pstate_count) { 608 609 ps = &sc->sc_pstate[i]; 610 611 if (msr.ps_flags != 0) 612 ps->ps_flags |= msr.ps_flags; 613 614 if (msr.ps_status_addr != 0) 615 ps->ps_status_addr = msr.ps_status_addr; 616 617 if (msr.ps_status_mask != 0) 618 ps->ps_status_mask = msr.ps_status_mask; 619 620 if (msr.ps_control_addr != 0) 621 ps->ps_control_addr = msr.ps_control_addr; 622 623 if (msr.ps_control_mask != 0) 624 ps->ps_control_mask = msr.ps_control_mask; 625 626 i++; 627 } 628 629 return 0; 630 } 631 632 /* 633 * Read the IA32_APERF and IA32_MPERF counters. The first 634 * increments at the rate of the fixed maximum frequency 635 * configured during the boot, whereas APERF counts at the 636 * rate of the actual frequency. Note that the MSRs must be 637 * read without delay, and that only the ratio between 638 * IA32_APERF and IA32_MPERF is architecturally defined. 639 * 640 * The function thus returns the percentage of the actual 641 * frequency in terms of the maximum frequency of the calling 642 * CPU since the last call. A value zero implies an error. 643 * 644 * For further details, refer to: 645 * 646 * Intel Corporation: Intel 64 and IA-32 Architectures 647 * Software Developer's Manual. Section 13.2, Volume 3A: 648 * System Programming Guide, Part 1. July, 2008. 649 * 650 * Advanced Micro Devices: BIOS and Kernel Developer's 651 * Guide (BKDG) for AMD Family 10h Processors. Section 652 * 2.4.5, Revision 3.48, April 2010. 653 */ 654 uint8_t 655 acpicpu_md_pstate_hwf(struct cpu_info *ci) 656 { 657 struct acpicpu_softc *sc; 658 uint64_t aperf, mperf; 659 uint8_t rv = 0; 660 661 sc = acpicpu_sc[ci->ci_acpiid]; 662 663 if (__predict_false(sc == NULL)) 664 return 0; 665 666 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 667 return 0; 668 669 aperf = sc->sc_pstate_aperf; 670 mperf = sc->sc_pstate_mperf; 671 672 x86_disable_intr(); 673 674 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 675 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 676 677 x86_enable_intr(); 678 679 aperf = sc->sc_pstate_aperf - aperf; 680 mperf = sc->sc_pstate_mperf - mperf; 681 682 if (__predict_true(mperf != 0)) 683 rv = (aperf * 100) / mperf; 684 685 return rv; 686 } 687 688 static void 689 acpicpu_md_pstate_hwf_reset(void *arg1, void *arg2) 690 { 691 struct cpu_info *ci = curcpu(); 692 struct acpicpu_softc *sc; 693 694 sc = acpicpu_sc[ci->ci_acpiid]; 695 696 if (__predict_false(sc == NULL)) 697 return; 698 699 x86_disable_intr(); 700 701 wrmsr(MSR_APERF, 0); 702 wrmsr(MSR_MPERF, 0); 703 704 x86_enable_intr(); 705 706 sc->sc_pstate_aperf = 0; 707 sc->sc_pstate_mperf = 0; 708 } 709 710 int 711 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 712 { 713 struct acpicpu_pstate *ps = NULL; 714 uint64_t val; 715 uint32_t i; 716 717 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 718 return acpicpu_md_pstate_fidvid_get(sc, freq); 719 720 /* 721 * Pick any P-state for the status address. 722 */ 723 for (i = 0; i < sc->sc_pstate_count; i++) { 724 725 ps = &sc->sc_pstate[i]; 726 727 if (__predict_true(ps->ps_freq != 0)) 728 break; 729 } 730 731 if (__predict_false(ps == NULL)) 732 return ENODEV; 733 734 if (__predict_false(ps->ps_status_addr == 0)) 735 return EINVAL; 736 737 val = rdmsr(ps->ps_status_addr); 738 739 if (__predict_true(ps->ps_status_mask != 0)) 740 val = val & ps->ps_status_mask; 741 742 /* 743 * Search for the value from known P-states. 744 */ 745 for (i = 0; i < sc->sc_pstate_count; i++) { 746 747 ps = &sc->sc_pstate[i]; 748 749 if (__predict_false(ps->ps_freq == 0)) 750 continue; 751 752 if (val == ps->ps_status) { 753 *freq = ps->ps_freq; 754 return 0; 755 } 756 } 757 758 return EIO; 759 } 760 761 int 762 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 763 { 764 uint64_t val = 0; 765 766 if (__predict_false(ps->ps_control_addr == 0)) 767 return EINVAL; 768 769 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 770 return acpicpu_md_pstate_fidvid_set(ps); 771 772 /* 773 * If the mask is set, do a read-modify-write. 774 */ 775 if (__predict_true(ps->ps_control_mask != 0)) { 776 val = rdmsr(ps->ps_control_addr); 777 val &= ~ps->ps_control_mask; 778 } 779 780 val |= ps->ps_control; 781 782 wrmsr(ps->ps_control_addr, val); 783 DELAY(ps->ps_latency); 784 785 return 0; 786 } 787 788 static int 789 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 790 { 791 struct acpicpu_pstate *ps; 792 uint32_t fid, i, vid; 793 uint32_t cfid, cvid; 794 int rv; 795 796 /* 797 * AMD family 0Fh needs special treatment. 798 * While it wants to use ACPI, it does not 799 * comply with the ACPI specifications. 800 */ 801 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 802 803 if (rv != 0) 804 return rv; 805 806 for (i = 0; i < sc->sc_pstate_count; i++) { 807 808 ps = &sc->sc_pstate[i]; 809 810 if (__predict_false(ps->ps_freq == 0)) 811 continue; 812 813 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 814 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 815 816 if (cfid == fid && cvid == vid) { 817 *freq = ps->ps_freq; 818 return 0; 819 } 820 } 821 822 return EIO; 823 } 824 825 static int 826 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 827 { 828 const uint64_t ctrl = ps->ps_control; 829 uint32_t cfid, cvid, fid, i, irt; 830 uint32_t pll, vco_cfid, vco_fid; 831 uint32_t val, vid, vst; 832 int rv; 833 834 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 835 836 if (rv != 0) 837 return rv; 838 839 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 840 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 841 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 842 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 843 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 844 845 vst = vst * 20; 846 pll = pll * 1000 / 5; 847 irt = 10 * __BIT(irt); 848 849 /* 850 * Phase 1. 851 */ 852 while (cvid > vid) { 853 854 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 855 val = (val > cvid) ? 0 : cvid - val; 856 857 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 858 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 859 860 if (rv != 0) 861 return rv; 862 } 863 864 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 865 866 for (; i > 0 && cvid > 0; --i) { 867 868 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 869 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 870 871 if (rv != 0) 872 return rv; 873 } 874 875 /* 876 * Phase 2. 877 */ 878 if (cfid != fid) { 879 880 vco_fid = FID_TO_VCO_FID(fid); 881 vco_cfid = FID_TO_VCO_FID(cfid); 882 883 while (abs(vco_fid - vco_cfid) > 2) { 884 885 if (fid <= cfid) 886 val = cfid - 2; 887 else { 888 val = (cfid > 6) ? cfid + 2 : 889 FID_TO_VCO_FID(cfid) + 2; 890 } 891 892 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 893 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 894 895 if (rv != 0) 896 return rv; 897 898 vco_cfid = FID_TO_VCO_FID(cfid); 899 } 900 901 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 902 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 903 904 if (rv != 0) 905 return rv; 906 } 907 908 /* 909 * Phase 3. 910 */ 911 if (cvid != vid) { 912 913 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 914 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 915 916 if (rv != 0) 917 return rv; 918 } 919 920 if (cfid != fid || cvid != vid) 921 return EIO; 922 923 return 0; 924 } 925 926 static int 927 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 928 { 929 int i = ACPICPU_P_STATE_RETRY * 100; 930 uint64_t val; 931 932 do { 933 val = rdmsr(MSR_0FH_STATUS); 934 935 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 936 937 if (i == 0) 938 return EAGAIN; 939 940 if (cfid != NULL) 941 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 942 943 if (cvid != NULL) 944 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 945 946 return 0; 947 } 948 949 static void 950 acpicpu_md_pstate_fidvid_write(uint32_t fid, 951 uint32_t vid, uint32_t cnt, uint32_t tmo) 952 { 953 uint64_t val = 0; 954 955 val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 956 val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 957 val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 958 val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 959 960 wrmsr(MSR_0FH_CONTROL, val); 961 DELAY(tmo); 962 } 963 964 int 965 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 966 { 967 struct acpicpu_tstate *ts; 968 uint64_t val; 969 uint32_t i; 970 971 val = rdmsr(MSR_THERM_CONTROL); 972 973 for (i = 0; i < sc->sc_tstate_count; i++) { 974 975 ts = &sc->sc_tstate[i]; 976 977 if (ts->ts_percent == 0) 978 continue; 979 980 if (val == ts->ts_status) { 981 *percent = ts->ts_percent; 982 return 0; 983 } 984 } 985 986 return EIO; 987 } 988 989 int 990 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 991 { 992 uint64_t val; 993 uint8_t i; 994 995 val = ts->ts_control; 996 val = val & __BITS(1, 4); 997 998 wrmsr(MSR_THERM_CONTROL, val); 999 1000 if (ts->ts_status == 0) { 1001 DELAY(ts->ts_latency); 1002 return 0; 1003 } 1004 1005 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 1006 1007 val = rdmsr(MSR_THERM_CONTROL); 1008 1009 if (val == ts->ts_status) 1010 return 0; 1011 1012 DELAY(ts->ts_latency); 1013 } 1014 1015 return EAGAIN; 1016 } 1017 1018 /* 1019 * A kludge for backwards compatibility. 1020 */ 1021 static int 1022 acpicpu_md_pstate_sysctl_init(void) 1023 { 1024 const struct sysctlnode *fnode, *mnode, *rnode; 1025 const char *str; 1026 int rv; 1027 1028 switch (cpu_vendor) { 1029 1030 case CPUVENDOR_IDT: 1031 case CPUVENDOR_INTEL: 1032 str = "est"; 1033 break; 1034 1035 case CPUVENDOR_AMD: 1036 str = "powernow"; 1037 break; 1038 1039 default: 1040 return ENODEV; 1041 } 1042 1043 1044 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1045 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1046 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1047 1048 if (rv != 0) 1049 goto fail; 1050 1051 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1052 0, CTLTYPE_NODE, str, NULL, 1053 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1054 1055 if (rv != 0) 1056 goto fail; 1057 1058 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1059 0, CTLTYPE_NODE, "frequency", NULL, 1060 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1061 1062 if (rv != 0) 1063 goto fail; 1064 1065 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1066 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1067 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1068 1069 if (rv != 0) 1070 goto fail; 1071 1072 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1073 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1074 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1075 1076 if (rv != 0) 1077 goto fail; 1078 1079 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1080 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1081 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1082 1083 if (rv != 0) 1084 goto fail; 1085 1086 return 0; 1087 1088 fail: 1089 if (acpicpu_log != NULL) { 1090 sysctl_teardown(&acpicpu_log); 1091 acpicpu_log = NULL; 1092 } 1093 1094 return rv; 1095 } 1096 1097 static int 1098 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1099 { 1100 struct cpu_info *ci = curcpu(); 1101 struct sysctlnode node; 1102 uint32_t freq; 1103 int err; 1104 1105 err = acpicpu_pstate_get(ci, &freq); 1106 1107 if (err != 0) 1108 return err; 1109 1110 node = *rnode; 1111 node.sysctl_data = &freq; 1112 1113 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1114 1115 if (err != 0 || newp == NULL) 1116 return err; 1117 1118 return 0; 1119 } 1120 1121 static int 1122 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1123 { 1124 struct cpu_info *ci = curcpu(); 1125 struct sysctlnode node; 1126 uint32_t freq; 1127 int err; 1128 1129 err = acpicpu_pstate_get(ci, &freq); 1130 1131 if (err != 0) 1132 return err; 1133 1134 node = *rnode; 1135 node.sysctl_data = &freq; 1136 1137 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1138 1139 if (err != 0 || newp == NULL) 1140 return err; 1141 1142 acpicpu_pstate_set(ci, freq); 1143 1144 return 0; 1145 } 1146 1147 static int 1148 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1149 { 1150 struct cpu_info *ci = curcpu(); 1151 struct acpicpu_softc *sc; 1152 struct sysctlnode node; 1153 char buf[1024]; 1154 size_t len; 1155 uint32_t i; 1156 int err; 1157 1158 sc = acpicpu_sc[ci->ci_acpiid]; 1159 1160 if (sc == NULL) 1161 return ENXIO; 1162 1163 (void)memset(&buf, 0, sizeof(buf)); 1164 1165 mutex_enter(&sc->sc_mtx); 1166 1167 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1168 1169 if (sc->sc_pstate[i].ps_freq == 0) 1170 continue; 1171 1172 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1173 sc->sc_pstate[i].ps_freq, 1174 i < (sc->sc_pstate_count - 1) ? " " : ""); 1175 } 1176 1177 mutex_exit(&sc->sc_mtx); 1178 1179 node = *rnode; 1180 node.sysctl_data = buf; 1181 1182 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1183 1184 if (err != 0 || newp == NULL) 1185 return err; 1186 1187 return 0; 1188 } 1189 1190