1 /* $NetBSD: acpi_cpu_md.c,v 1.63 2011/06/23 08:10:35 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.63 2011/06/23 08:10:35 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/kcore.h> 36 #include <sys/sysctl.h> 37 #include <sys/xcall.h> 38 39 #include <x86/cpu.h> 40 #include <x86/cpufunc.h> 41 #include <x86/cputypes.h> 42 #include <x86/cpuvar.h> 43 #include <x86/cpu_msr.h> 44 #include <x86/machdep.h> 45 46 #include <dev/acpi/acpica.h> 47 #include <dev/acpi/acpi_cpu.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <machine/acpi_machdep.h> 53 54 /* 55 * Intel IA32_MISC_ENABLE. 56 */ 57 #define MSR_MISC_ENABLE_EST __BIT(16) 58 #define MSR_MISC_ENABLE_TURBO __BIT(38) 59 60 /* 61 * AMD C1E. 62 */ 63 #define MSR_CMPHALT 0xc0010055 64 65 #define MSR_CMPHALT_SMI __BIT(27) 66 #define MSR_CMPHALT_C1E __BIT(28) 67 #define MSR_CMPHALT_BMSTS __BIT(29) 68 69 /* 70 * AMD families 10h, 11h, and 14h 71 */ 72 #define MSR_10H_LIMIT 0xc0010061 73 #define MSR_10H_CONTROL 0xc0010062 74 #define MSR_10H_STATUS 0xc0010063 75 #define MSR_10H_CONFIG 0xc0010064 76 77 /* 78 * AMD family 0Fh. 79 */ 80 #define MSR_0FH_CONTROL 0xc0010041 81 #define MSR_0FH_STATUS 0xc0010042 82 83 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 84 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 85 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 86 87 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 88 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 89 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 90 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 91 92 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 93 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 94 95 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 96 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 97 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 98 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 99 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 100 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 101 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 102 103 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 104 105 static char native_idle_text[16]; 106 void (*native_idle)(void) = NULL; 107 108 static int acpicpu_md_quirk_piix4(const struct pci_attach_args *); 109 static void acpicpu_md_pstate_hwf_reset(void *, void *); 110 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 111 uint32_t *); 112 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 113 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 114 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 115 uint32_t, uint32_t); 116 static int acpicpu_md_pstate_sysctl_init(void); 117 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 118 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 119 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 120 121 extern struct acpicpu_softc **acpicpu_sc; 122 static struct sysctllog *acpicpu_log = NULL; 123 124 struct cpu_info * 125 acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct cpufeature_attach_args *cfaa = aux; 128 129 if (strcmp(cfaa->name, "frequency") != 0) 130 return NULL; 131 132 return cfaa->ci; 133 } 134 135 struct cpu_info * 136 acpicpu_md_attach(device_t parent, device_t self, void *aux) 137 { 138 struct cpufeature_attach_args *cfaa = aux; 139 140 return cfaa->ci; 141 } 142 143 uint32_t 144 acpicpu_md_flags(void) 145 { 146 struct cpu_info *ci = curcpu(); 147 struct pci_attach_args pa; 148 uint32_t family, val = 0; 149 uint32_t regs[4]; 150 151 if (acpi_md_ncpus() == 1) 152 val |= ACPICPU_FLAG_C_BM; 153 154 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 155 val |= ACPICPU_FLAG_C_FFH; 156 157 /* 158 * By default, assume that the local APIC timer 159 * as well as TSC are stalled during C3 sleep. 160 */ 161 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 162 163 switch (cpu_vendor) { 164 165 case CPUVENDOR_IDT: 166 167 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 168 val |= ACPICPU_FLAG_P_FFH; 169 170 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 171 val |= ACPICPU_FLAG_T_FFH; 172 173 break; 174 175 case CPUVENDOR_INTEL: 176 177 /* 178 * Bus master control and arbitration should be 179 * available on all supported Intel CPUs (to be 180 * sure, this is double-checked later from the 181 * firmware data). These flags imply that it is 182 * not necessary to flush caches before C3 state. 183 */ 184 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 185 186 /* 187 * Check if we can use "native", MSR-based, 188 * access. If not, we have to resort to I/O. 189 */ 190 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 191 val |= ACPICPU_FLAG_P_FFH; 192 193 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 194 val |= ACPICPU_FLAG_T_FFH; 195 196 /* 197 * Check whether MSR_APERF, MSR_MPERF, and Turbo 198 * Boost are available. Also see if we might have 199 * an invariant local APIC timer ("ARAT"). 200 */ 201 if (cpuid_level >= 0x06) { 202 203 x86_cpuid(0x00000006, regs); 204 205 if ((regs[2] & CPUID_DSPM_HWF) != 0) 206 val |= ACPICPU_FLAG_P_HWF; 207 208 if ((regs[0] & CPUID_DSPM_IDA) != 0) 209 val |= ACPICPU_FLAG_P_TURBO; 210 211 if ((regs[0] & CPUID_DSPM_ARAT) != 0) 212 val &= ~ACPICPU_FLAG_C_APIC; 213 } 214 215 /* 216 * Detect whether TSC is invariant. If it is not, 217 * we keep the flag to note that TSC will not run 218 * at constant rate. Depending on the CPU, this may 219 * affect P- and T-state changes, but especially 220 * relevant are C-states; with variant TSC, states 221 * larger than C1 may completely stop the counter. 222 */ 223 x86_cpuid(0x80000000, regs); 224 225 if (regs[0] >= 0x80000007) { 226 227 x86_cpuid(0x80000007, regs); 228 229 if ((regs[3] & __BIT(8)) != 0) 230 val &= ~ACPICPU_FLAG_C_TSC; 231 } 232 233 break; 234 235 case CPUVENDOR_AMD: 236 237 x86_cpuid(0x80000000, regs); 238 239 if (regs[0] < 0x80000007) 240 break; 241 242 x86_cpuid(0x80000007, regs); 243 244 family = CPUID2FAMILY(ci->ci_signature); 245 246 if (family == 0xf) 247 family += CPUID2EXTFAMILY(ci->ci_signature); 248 249 switch (family) { 250 251 case 0x0f: 252 253 /* 254 * Evaluate support for the "FID/VID 255 * algorithm" also used by powernow(4). 256 */ 257 if ((regs[3] & CPUID_APM_FID) == 0) 258 break; 259 260 if ((regs[3] & CPUID_APM_VID) == 0) 261 break; 262 263 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 264 break; 265 266 case 0x10: 267 case 0x11: 268 val |= ACPICPU_FLAG_C_C1E; 269 /* FALLTHROUGH */ 270 271 case 0x14: /* AMD Fusion */ 272 273 /* 274 * Like with Intel, detect invariant TSC, 275 * MSR-based P-states, and AMD's "turbo" 276 * (Core Performance Boost), respectively. 277 */ 278 if ((regs[3] & CPUID_APM_TSC) != 0) 279 val &= ~ACPICPU_FLAG_C_TSC; 280 281 if ((regs[3] & CPUID_APM_HWP) != 0) 282 val |= ACPICPU_FLAG_P_FFH; 283 284 if ((regs[3] & CPUID_APM_CPB) != 0) 285 val |= ACPICPU_FLAG_P_TURBO; 286 287 /* 288 * Also check for APERF and MPERF, 289 * first available in the family 10h. 290 */ 291 if (cpuid_level >= 0x06) { 292 293 x86_cpuid(0x00000006, regs); 294 295 if ((regs[2] & CPUID_DSPM_HWF) != 0) 296 val |= ACPICPU_FLAG_P_HWF; 297 } 298 299 break; 300 } 301 302 break; 303 } 304 305 /* 306 * There are several erratums for PIIX4. 307 */ 308 if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 309 val |= ACPICPU_FLAG_PIIX4; 310 311 return val; 312 } 313 314 static int 315 acpicpu_md_quirk_piix4(const struct pci_attach_args *pa) 316 { 317 318 /* 319 * XXX: The pci_find_device(9) function only 320 * deals with attached devices. Change this 321 * to use something like pci_device_foreach(). 322 */ 323 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 324 return 0; 325 326 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 327 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 328 return 1; 329 330 return 0; 331 } 332 333 void 334 acpicpu_md_quirk_c1e(void) 335 { 336 const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 337 uint64_t val; 338 339 val = rdmsr(MSR_CMPHALT); 340 341 if ((val & c1e) != 0) 342 wrmsr(MSR_CMPHALT, val & ~c1e); 343 } 344 345 int 346 acpicpu_md_cstate_start(struct acpicpu_softc *sc) 347 { 348 const size_t size = sizeof(native_idle_text); 349 struct acpicpu_cstate *cs; 350 bool ipi = false; 351 int i; 352 353 /* 354 * Save the cpu_idle(9) loop used by default. 355 */ 356 x86_cpu_idle_get(&native_idle, native_idle_text, size); 357 358 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 359 360 cs = &sc->sc_cstate[i]; 361 362 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 363 ipi = true; 364 break; 365 } 366 } 367 368 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 369 370 return 0; 371 } 372 373 int 374 acpicpu_md_cstate_stop(void) 375 { 376 static char text[16]; 377 void (*func)(void); 378 uint64_t xc; 379 bool ipi; 380 381 x86_cpu_idle_get(&func, text, sizeof(text)); 382 383 if (func == native_idle) 384 return EALREADY; 385 386 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 387 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 388 389 /* 390 * Run a cross-call to ensure that all CPUs are 391 * out from the ACPI idle-loop before detachment. 392 */ 393 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 394 xc_wait(xc); 395 396 return 0; 397 } 398 399 /* 400 * Called with interrupts disabled. 401 * Caller should enable interrupts after return. 402 */ 403 void 404 acpicpu_md_cstate_enter(int method, int state) 405 { 406 struct cpu_info *ci = curcpu(); 407 408 switch (method) { 409 410 case ACPICPU_C_STATE_FFH: 411 412 x86_enable_intr(); 413 x86_monitor(&ci->ci_want_resched, 0, 0); 414 415 if (__predict_false(ci->ci_want_resched != 0)) 416 return; 417 418 x86_mwait((state - 1) << 4, 0); 419 break; 420 421 case ACPICPU_C_STATE_HALT: 422 423 if (__predict_false(ci->ci_want_resched != 0)) 424 return; 425 426 x86_stihlt(); 427 break; 428 } 429 } 430 431 int 432 acpicpu_md_pstate_start(struct acpicpu_softc *sc) 433 { 434 uint64_t xc, val; 435 436 switch (cpu_vendor) { 437 438 case CPUVENDOR_IDT: 439 case CPUVENDOR_INTEL: 440 441 /* 442 * Make sure EST is enabled. 443 */ 444 if ((sc->sc_flags & ACPICPU_FLAG_P_FFH) != 0) { 445 446 val = rdmsr(MSR_MISC_ENABLE); 447 448 if ((val & MSR_MISC_ENABLE_EST) == 0) { 449 450 val |= MSR_MISC_ENABLE_EST; 451 wrmsr(MSR_MISC_ENABLE, val); 452 val = rdmsr(MSR_MISC_ENABLE); 453 454 if ((val & MSR_MISC_ENABLE_EST) == 0) 455 return ENOTTY; 456 } 457 } 458 } 459 460 /* 461 * Reset the APERF and MPERF counters. 462 */ 463 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 464 xc = xc_broadcast(0, acpicpu_md_pstate_hwf_reset, NULL, NULL); 465 xc_wait(xc); 466 } 467 468 return acpicpu_md_pstate_sysctl_init(); 469 } 470 471 int 472 acpicpu_md_pstate_stop(void) 473 { 474 475 if (acpicpu_log == NULL) 476 return EALREADY; 477 478 sysctl_teardown(&acpicpu_log); 479 acpicpu_log = NULL; 480 481 return 0; 482 } 483 484 int 485 acpicpu_md_pstate_init(struct acpicpu_softc *sc) 486 { 487 struct cpu_info *ci = sc->sc_ci; 488 struct acpicpu_pstate *ps, msr; 489 uint32_t family, i = 0; 490 491 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 492 493 switch (cpu_vendor) { 494 495 case CPUVENDOR_IDT: 496 case CPUVENDOR_INTEL: 497 498 /* 499 * If the so-called Turbo Boost is present, 500 * the P0-state is always the "turbo state". 501 * It is shown as the P1 frequency + 1 MHz. 502 * 503 * For discussion, see: 504 * 505 * Intel Corporation: Intel Turbo Boost Technology 506 * in Intel Core(tm) Microarchitectures (Nehalem) 507 * Based Processors. White Paper, November 2008. 508 */ 509 if (sc->sc_pstate_count >= 2 && 510 (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 511 512 ps = &sc->sc_pstate[0]; 513 514 if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 515 ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 516 } 517 518 msr.ps_control_addr = MSR_PERF_CTL; 519 msr.ps_control_mask = __BITS(0, 15); 520 521 msr.ps_status_addr = MSR_PERF_STATUS; 522 msr.ps_status_mask = __BITS(0, 15); 523 break; 524 525 case CPUVENDOR_AMD: 526 527 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 528 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 529 530 family = CPUID2FAMILY(ci->ci_signature); 531 532 if (family == 0xf) 533 family += CPUID2EXTFAMILY(ci->ci_signature); 534 535 switch (family) { 536 537 case 0x0f: 538 msr.ps_control_addr = MSR_0FH_CONTROL; 539 msr.ps_status_addr = MSR_0FH_STATUS; 540 break; 541 542 case 0x10: 543 case 0x11: 544 case 0x14: /* AMD Fusion */ 545 msr.ps_control_addr = MSR_10H_CONTROL; 546 msr.ps_control_mask = __BITS(0, 2); 547 548 msr.ps_status_addr = MSR_10H_STATUS; 549 msr.ps_status_mask = __BITS(0, 2); 550 break; 551 552 default: 553 /* 554 * If we have an unknown AMD CPU, rely on XPSS. 555 */ 556 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 557 return EOPNOTSUPP; 558 } 559 560 break; 561 562 default: 563 return ENODEV; 564 } 565 566 /* 567 * Fill the P-state structures with MSR addresses that are 568 * known to be correct. If we do not know the addresses, 569 * leave the values intact. If a vendor uses XPSS, we do 570 * not necessarily need to do anything to support new CPUs. 571 */ 572 while (i < sc->sc_pstate_count) { 573 574 ps = &sc->sc_pstate[i]; 575 576 if (msr.ps_flags != 0) 577 ps->ps_flags |= msr.ps_flags; 578 579 if (msr.ps_status_addr != 0) 580 ps->ps_status_addr = msr.ps_status_addr; 581 582 if (msr.ps_status_mask != 0) 583 ps->ps_status_mask = msr.ps_status_mask; 584 585 if (msr.ps_control_addr != 0) 586 ps->ps_control_addr = msr.ps_control_addr; 587 588 if (msr.ps_control_mask != 0) 589 ps->ps_control_mask = msr.ps_control_mask; 590 591 i++; 592 } 593 594 return 0; 595 } 596 597 /* 598 * Read the IA32_APERF and IA32_MPERF counters. The first 599 * increments at the rate of the fixed maximum frequency 600 * configured during the boot, whereas APERF counts at the 601 * rate of the actual frequency. Note that the MSRs must be 602 * read without delay, and that only the ratio between 603 * IA32_APERF and IA32_MPERF is architecturally defined. 604 * 605 * The function thus returns the percentage of the actual 606 * frequency in terms of the maximum frequency of the calling 607 * CPU since the last call. A value zero implies an error. 608 * 609 * For further details, refer to: 610 * 611 * Intel Corporation: Intel 64 and IA-32 Architectures 612 * Software Developer's Manual. Section 13.2, Volume 3A: 613 * System Programming Guide, Part 1. July, 2008. 614 * 615 * Advanced Micro Devices: BIOS and Kernel Developer's 616 * Guide (BKDG) for AMD Family 10h Processors. Section 617 * 2.4.5, Revision 3.48, April 2010. 618 */ 619 uint8_t 620 acpicpu_md_pstate_hwf(struct cpu_info *ci) 621 { 622 struct acpicpu_softc *sc; 623 uint64_t aperf, mperf; 624 uint8_t rv = 0; 625 626 sc = acpicpu_sc[ci->ci_acpiid]; 627 628 if (__predict_false(sc == NULL)) 629 return 0; 630 631 if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 632 return 0; 633 634 aperf = sc->sc_pstate_aperf; 635 mperf = sc->sc_pstate_mperf; 636 637 x86_disable_intr(); 638 639 sc->sc_pstate_aperf = rdmsr(MSR_APERF); 640 sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 641 642 x86_enable_intr(); 643 644 aperf = sc->sc_pstate_aperf - aperf; 645 mperf = sc->sc_pstate_mperf - mperf; 646 647 if (__predict_true(mperf != 0)) 648 rv = (aperf * 100) / mperf; 649 650 return rv; 651 } 652 653 static void 654 acpicpu_md_pstate_hwf_reset(void *arg1, void *arg2) 655 { 656 struct cpu_info *ci = curcpu(); 657 struct acpicpu_softc *sc; 658 659 sc = acpicpu_sc[ci->ci_acpiid]; 660 661 if (__predict_false(sc == NULL)) 662 return; 663 664 x86_disable_intr(); 665 666 wrmsr(MSR_APERF, 0); 667 wrmsr(MSR_MPERF, 0); 668 669 x86_enable_intr(); 670 671 sc->sc_pstate_aperf = 0; 672 sc->sc_pstate_mperf = 0; 673 } 674 675 int 676 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 677 { 678 struct acpicpu_pstate *ps = NULL; 679 uint64_t val; 680 uint32_t i; 681 682 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 683 return acpicpu_md_pstate_fidvid_get(sc, freq); 684 685 /* 686 * Pick any P-state for the status address. 687 */ 688 for (i = 0; i < sc->sc_pstate_count; i++) { 689 690 ps = &sc->sc_pstate[i]; 691 692 if (__predict_true(ps->ps_freq != 0)) 693 break; 694 } 695 696 if (__predict_false(ps == NULL)) 697 return ENODEV; 698 699 if (__predict_false(ps->ps_status_addr == 0)) 700 return EINVAL; 701 702 val = rdmsr(ps->ps_status_addr); 703 704 if (__predict_true(ps->ps_status_mask != 0)) 705 val = val & ps->ps_status_mask; 706 707 /* 708 * Search for the value from known P-states. 709 */ 710 for (i = 0; i < sc->sc_pstate_count; i++) { 711 712 ps = &sc->sc_pstate[i]; 713 714 if (__predict_false(ps->ps_freq == 0)) 715 continue; 716 717 if (val == ps->ps_status) { 718 *freq = ps->ps_freq; 719 return 0; 720 } 721 } 722 723 /* 724 * If the value was not found, try APERF/MPERF. 725 * The state is P0 if the return value is 100 %. 726 */ 727 if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) { 728 729 if (acpicpu_md_pstate_hwf(sc->sc_ci) == 100) { 730 *freq = sc->sc_pstate[0].ps_freq; 731 return 0; 732 } 733 } 734 735 return EIO; 736 } 737 738 int 739 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 740 { 741 uint64_t val = 0; 742 743 if (__predict_false(ps->ps_control_addr == 0)) 744 return EINVAL; 745 746 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 747 return acpicpu_md_pstate_fidvid_set(ps); 748 749 /* 750 * If the mask is set, do a read-modify-write. 751 */ 752 if (__predict_true(ps->ps_control_mask != 0)) { 753 val = rdmsr(ps->ps_control_addr); 754 val &= ~ps->ps_control_mask; 755 } 756 757 val |= ps->ps_control; 758 759 wrmsr(ps->ps_control_addr, val); 760 DELAY(ps->ps_latency); 761 762 return 0; 763 } 764 765 static int 766 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 767 { 768 struct acpicpu_pstate *ps; 769 uint32_t fid, i, vid; 770 uint32_t cfid, cvid; 771 int rv; 772 773 /* 774 * AMD family 0Fh needs special treatment. 775 * While it wants to use ACPI, it does not 776 * comply with the ACPI specifications. 777 */ 778 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 779 780 if (rv != 0) 781 return rv; 782 783 for (i = 0; i < sc->sc_pstate_count; i++) { 784 785 ps = &sc->sc_pstate[i]; 786 787 if (__predict_false(ps->ps_freq == 0)) 788 continue; 789 790 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 791 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 792 793 if (cfid == fid && cvid == vid) { 794 *freq = ps->ps_freq; 795 return 0; 796 } 797 } 798 799 return EIO; 800 } 801 802 static int 803 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 804 { 805 const uint64_t ctrl = ps->ps_control; 806 uint32_t cfid, cvid, fid, i, irt; 807 uint32_t pll, vco_cfid, vco_fid; 808 uint32_t val, vid, vst; 809 int rv; 810 811 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 812 813 if (rv != 0) 814 return rv; 815 816 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 817 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 818 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 819 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 820 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 821 822 vst = vst * 20; 823 pll = pll * 1000 / 5; 824 irt = 10 * __BIT(irt); 825 826 /* 827 * Phase 1. 828 */ 829 while (cvid > vid) { 830 831 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 832 val = (val > cvid) ? 0 : cvid - val; 833 834 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 835 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 836 837 if (rv != 0) 838 return rv; 839 } 840 841 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 842 843 for (; i > 0 && cvid > 0; --i) { 844 845 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 846 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 847 848 if (rv != 0) 849 return rv; 850 } 851 852 /* 853 * Phase 2. 854 */ 855 if (cfid != fid) { 856 857 vco_fid = FID_TO_VCO_FID(fid); 858 vco_cfid = FID_TO_VCO_FID(cfid); 859 860 while (abs(vco_fid - vco_cfid) > 2) { 861 862 if (fid <= cfid) 863 val = cfid - 2; 864 else { 865 val = (cfid > 6) ? cfid + 2 : 866 FID_TO_VCO_FID(cfid) + 2; 867 } 868 869 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 870 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 871 872 if (rv != 0) 873 return rv; 874 875 vco_cfid = FID_TO_VCO_FID(cfid); 876 } 877 878 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 879 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 880 881 if (rv != 0) 882 return rv; 883 } 884 885 /* 886 * Phase 3. 887 */ 888 if (cvid != vid) { 889 890 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 891 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 892 893 if (rv != 0) 894 return rv; 895 } 896 897 return 0; 898 } 899 900 static int 901 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 902 { 903 int i = ACPICPU_P_STATE_RETRY * 100; 904 uint64_t val; 905 906 do { 907 val = rdmsr(MSR_0FH_STATUS); 908 909 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 910 911 if (i == 0) 912 return EAGAIN; 913 914 if (cfid != NULL) 915 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 916 917 if (cvid != NULL) 918 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 919 920 return 0; 921 } 922 923 static void 924 acpicpu_md_pstate_fidvid_write(uint32_t fid, 925 uint32_t vid, uint32_t cnt, uint32_t tmo) 926 { 927 uint64_t val = 0; 928 929 val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 930 val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 931 val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 932 val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 933 934 wrmsr(MSR_0FH_CONTROL, val); 935 DELAY(tmo); 936 } 937 938 int 939 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 940 { 941 struct acpicpu_tstate *ts; 942 uint64_t val; 943 uint32_t i; 944 945 val = rdmsr(MSR_THERM_CONTROL); 946 947 for (i = 0; i < sc->sc_tstate_count; i++) { 948 949 ts = &sc->sc_tstate[i]; 950 951 if (ts->ts_percent == 0) 952 continue; 953 954 if (val == ts->ts_status) { 955 *percent = ts->ts_percent; 956 return 0; 957 } 958 } 959 960 return EIO; 961 } 962 963 int 964 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 965 { 966 uint64_t val; 967 uint8_t i; 968 969 val = ts->ts_control; 970 val = val & __BITS(1, 4); 971 972 wrmsr(MSR_THERM_CONTROL, val); 973 974 if (ts->ts_status == 0) { 975 DELAY(ts->ts_latency); 976 return 0; 977 } 978 979 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 980 981 val = rdmsr(MSR_THERM_CONTROL); 982 983 if (val == ts->ts_status) 984 return 0; 985 986 DELAY(ts->ts_latency); 987 } 988 989 return EAGAIN; 990 } 991 992 /* 993 * A kludge for backwards compatibility. 994 */ 995 static int 996 acpicpu_md_pstate_sysctl_init(void) 997 { 998 const struct sysctlnode *fnode, *mnode, *rnode; 999 const char *str; 1000 int rv; 1001 1002 switch (cpu_vendor) { 1003 1004 case CPUVENDOR_IDT: 1005 case CPUVENDOR_INTEL: 1006 str = "est"; 1007 break; 1008 1009 case CPUVENDOR_AMD: 1010 str = "powernow"; 1011 break; 1012 1013 default: 1014 return ENODEV; 1015 } 1016 1017 1018 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1019 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1020 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1021 1022 if (rv != 0) 1023 goto fail; 1024 1025 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1026 0, CTLTYPE_NODE, str, NULL, 1027 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1028 1029 if (rv != 0) 1030 goto fail; 1031 1032 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1033 0, CTLTYPE_NODE, "frequency", NULL, 1034 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1035 1036 if (rv != 0) 1037 goto fail; 1038 1039 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1040 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1041 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1042 1043 if (rv != 0) 1044 goto fail; 1045 1046 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1047 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1048 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1049 1050 if (rv != 0) 1051 goto fail; 1052 1053 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1054 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1055 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1056 1057 if (rv != 0) 1058 goto fail; 1059 1060 return 0; 1061 1062 fail: 1063 if (acpicpu_log != NULL) { 1064 sysctl_teardown(&acpicpu_log); 1065 acpicpu_log = NULL; 1066 } 1067 1068 return rv; 1069 } 1070 1071 static int 1072 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1073 { 1074 struct cpu_info *ci = curcpu(); 1075 struct sysctlnode node; 1076 uint32_t freq; 1077 int err; 1078 1079 err = acpicpu_pstate_get(ci, &freq); 1080 1081 if (err != 0) 1082 return err; 1083 1084 node = *rnode; 1085 node.sysctl_data = &freq; 1086 1087 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1088 1089 if (err != 0 || newp == NULL) 1090 return err; 1091 1092 return 0; 1093 } 1094 1095 static int 1096 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1097 { 1098 struct cpu_info *ci = curcpu(); 1099 struct sysctlnode node; 1100 uint32_t freq; 1101 int err; 1102 1103 err = acpicpu_pstate_get(ci, &freq); 1104 1105 if (err != 0) 1106 return err; 1107 1108 node = *rnode; 1109 node.sysctl_data = &freq; 1110 1111 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1112 1113 if (err != 0 || newp == NULL) 1114 return err; 1115 1116 acpicpu_pstate_set(ci, freq); 1117 1118 return 0; 1119 } 1120 1121 static int 1122 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1123 { 1124 struct cpu_info *ci = curcpu(); 1125 struct acpicpu_softc *sc; 1126 struct sysctlnode node; 1127 char buf[1024]; 1128 size_t len; 1129 uint32_t i; 1130 int err; 1131 1132 sc = acpicpu_sc[ci->ci_acpiid]; 1133 1134 if (sc == NULL) 1135 return ENXIO; 1136 1137 (void)memset(&buf, 0, sizeof(buf)); 1138 1139 mutex_enter(&sc->sc_mtx); 1140 1141 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1142 1143 if (sc->sc_pstate[i].ps_freq == 0) 1144 continue; 1145 1146 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1147 sc->sc_pstate[i].ps_freq, 1148 i < (sc->sc_pstate_count - 1) ? " " : ""); 1149 } 1150 1151 mutex_exit(&sc->sc_mtx); 1152 1153 node = *rnode; 1154 node.sysctl_data = buf; 1155 1156 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1157 1158 if (err != 0 || newp == NULL) 1159 return err; 1160 1161 return 0; 1162 } 1163 1164