xref: /netbsd-src/sys/arch/x68k/dev/zs.c (revision d909946ca08dceb44d7d0f22ec9488679695d976) 
1 /*	$NetBSD: zs.c,v 1.44 2016/08/05 05:32:02 isaki Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998 Minoura Makoto
5  * Copyright (c) 1996 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Gordon W. Ross.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Zilog Z8530 Dual UART driver (machine-dependent part)
35  *
36  * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
37  * while channel B is dedicated to the mouse.
38  * Extra Z8530's can be installed for serial ports.  This driver
39  * supports up to 5 chips including the built-in one.
40  */
41 
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.44 2016/08/05 05:32:02 isaki Exp $");
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/bus.h>
58 #include <sys/intr.h>
59 
60 #include <arch/x68k/dev/intiovar.h>
61 #include <machine/z8530var.h>
62 
63 #include <dev/ic/z8530reg.h>
64 
65 #include "ioconf.h"
66 #include "zsc.h"	/* NZSC */
67 #include "opt_zsc.h"
68 #ifndef ZSCN_SPEED
69 #define ZSCN_SPEED 9600
70 #endif
71 #include "zstty.h"
72 
73 
74 extern void Debugger(void);
75 
76 /*
77  * Some warts needed by z8530tty.c -
78  * The default parity REALLY needs to be the same as the PROM uses,
79  * or you can not see messages done with printf during boot-up...
80  */
81 int zs_def_cflag = (CREAD | CS8 | HUPCL);
82 int zscn_def_cflag = (CREAD | CS8 | HUPCL);
83 
84 /*
85  * X68k provides a 5.0 MHz clock to the ZS chips.
86  */
87 #define PCLK	(5 * 1000 * 1000)	/* PCLK pin input clock rate */
88 
89 
90 /* Default physical addresses. */
91 #define ZS_MAXDEV 5
92 static bus_addr_t zs_physaddr[ZS_MAXDEV] = {
93 	0x00e98000,
94 	0x00eafc00,
95 	0x00eafc10,
96 	0x00eafc20,
97 	0x00eafc30
98 };
99 
100 static uint8_t zs_init_reg[16] = {
101 	0,	/* 0: CMD (reset, etc.) */
102 	0,	/* 1: No interrupts yet. */
103 	0x70,	/* 2: XXX: IVECT */
104 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
105 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
106 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
107 	0,	/* 6: TXSYNC/SYNCLO */
108 	0,	/* 7: RXSYNC/SYNCHI */
109 	0,	/* 8: alias for data port */
110 	ZSWR9_MASTER_IE,
111 	ZSWR10_NRZ,	/*10: Misc. TX/RX control bits */
112 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
113 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
114 	0,			/*13: BAUDHI (default=9600) */
115 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
116 	ZSWR15_BREAK_IE,
117 };
118 
119 static volatile struct zschan *conschan = 0;
120 
121 
122 /****************************************************************
123  * Autoconfig
124  ****************************************************************/
125 
126 /* Definition of the driver for autoconfig. */
127 static int	zs_match(device_t, cfdata_t, void *);
128 static void	zs_attach(device_t, device_t, void *);
129 static int	zs_print(void *, const char *name);
130 
131 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
132     zs_match, zs_attach, NULL, NULL);
133 
134 static int zshard(void *);
135 static int zs_get_speed(struct zs_chanstate *);
136 
137 
138 /*
139  * Is the zs chip present?
140  */
141 static int
142 zs_match(device_t parent, cfdata_t cf, void *aux)
143 {
144 	struct intio_attach_args *ia = aux;
145 	struct zsdevice *zsaddr = (void *)ia->ia_addr;
146 	int i;
147 
148 	if (strcmp(ia->ia_name, "zsc") != 0)
149 		return 0;
150 
151 	for (i = 0; i < ZS_MAXDEV; i++)
152 		if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
153 			break;
154 	if (i == ZS_MAXDEV) {
155 		/* not a recognized address */
156 		return 0;
157 	}
158 
159 	ia->ia_size = 8;
160 	if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
161 		return 0;
162 
163 	if (badaddr((void *)IIOV(zsaddr)))
164 		return 0;
165 
166 	return (1);
167 }
168 
169 /*
170  * Attach a found zs.
171  */
172 static void
173 zs_attach(device_t parent, device_t self, void *aux)
174 {
175 	struct zsc_softc *zsc = device_private(self);
176 	struct intio_attach_args *ia = aux;
177 	struct zsc_attach_args zsc_args;
178 	volatile struct zschan *zc;
179 	struct zs_chanstate *cs;
180 	int r __diagused;
181 	int s, channel;
182 
183 	zsc->zsc_dev = self;
184 	aprint_normal("\n");
185 
186 	zsc->zsc_addr = (void *)ia->ia_addr;
187 
188 	ia->ia_size = 8;
189 	r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
190 #ifdef DIAGNOSTIC
191 	if (r)
192 		panic("zs: intio IO map corruption");
193 #endif
194 
195 	/*
196 	 * Initialize software state for each channel.
197 	 */
198 	for (channel = 0; channel < 2; channel++) {
199 		device_t child;
200 
201 		zsc_args.channel = channel;
202 		zsc_args.hwflags = 0;
203 		cs = &zsc->zsc_cs_store[channel];
204 		zsc->zsc_cs[channel] = cs;
205 
206 		zs_lock_init(cs);
207 		cs->cs_channel = channel;
208 		cs->cs_private = NULL;
209 		cs->cs_ops = &zsops_null;
210 		cs->cs_brg_clk = PCLK / 16;
211 
212 		if (channel == 0)
213 			zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_a);
214 		else
215 			zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_b);
216 		cs->cs_reg_csr  = &zc->zc_csr;
217 		cs->cs_reg_data = &zc->zc_data;
218 
219 		zs_init_reg[2] = ia->ia_intr;
220 		memcpy(cs->cs_creg, zs_init_reg, 16);
221 		memcpy(cs->cs_preg, zs_init_reg, 16);
222 
223 		if (zc == conschan) {
224 			zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
225 			cs->cs_defspeed = zs_get_speed(cs);
226 			cs->cs_defcflag = zscn_def_cflag;
227 		} else {
228 			cs->cs_defspeed = 9600;
229 			cs->cs_defcflag = zs_def_cflag;
230 		}
231 
232 		/* Make these correspond to cs_defcflag (-crtscts) */
233 		cs->cs_rr0_dcd = ZSRR0_DCD;
234 		cs->cs_rr0_cts = 0;
235 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
236 		cs->cs_wr5_rts = 0;
237 
238 		/*
239 		 * Clear the master interrupt enable.
240 		 * The INTENA is common to both channels,
241 		 * so just do it on the A channel.
242 		 */
243 		if (channel == 0) {
244 			s = splzs();
245 			zs_write_reg(cs, 9, 0);
246 			splx(s);
247 		}
248 
249 		/*
250 		 * Look for a child driver for this channel.
251 		 * The child attach will setup the hardware.
252 		 */
253 		child = config_found(self, (void *)&zsc_args, zs_print);
254 #if ZSTTY > 0
255 		if (zc == conschan &&
256 		    ((child && strcmp(device_xname(child), "zstty0")) ||
257 		     child == NULL)) /* XXX */
258 			panic("%s: console device mismatch", __func__);
259 #endif
260 		if (child == NULL) {
261 			/* No sub-driver.  Just reset it. */
262 			uint8_t reset = (channel == 0) ?
263 				ZSWR9_A_RESET : ZSWR9_B_RESET;
264 			s = splzs();
265 			zs_write_reg(cs,  9, reset);
266 			splx(s);
267 		}
268 	}
269 
270 	/*
271 	 * Now safe to install interrupt handlers.
272 	 */
273 	if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
274 		panic("%s: interrupt vector busy", __func__);
275 	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
276 	    (void (*)(void *))zsc_intr_soft, zsc);
277 	/* XXX; evcnt_attach() ? */
278 
279 	/*
280 	 * Set the master interrupt enable and interrupt vector.
281 	 * (common to both channels, do it on A)
282 	 */
283 	cs = zsc->zsc_cs[0];
284 	s = splzs();
285 	/* interrupt vector */
286 	zs_write_reg(cs, 2, ia->ia_intr);
287 	/* master interrupt control (enable) */
288 	zs_write_reg(cs, 9, zs_init_reg[9]);
289 	splx(s);
290 }
291 
292 static int
293 zs_print(void *aux, const char *name)
294 {
295 	struct zsc_attach_args *args = aux;
296 
297 	if (name != NULL)
298 		aprint_normal("%s: ", name);
299 
300 	if (args->channel != -1)
301 		aprint_normal(" channel %d", args->channel);
302 
303 	return UNCONF;
304 }
305 
306 
307 /*
308  * For x68k-port, we don't use autovectored interrupt.
309  * We do not need to look at all of the zs chips.
310  */
311 static int
312 zshard(void *arg)
313 {
314 	struct zsc_softc *zsc = arg;
315 	int rval;
316 	int s;
317 
318 	/*
319 	 * Actually, zs hardware ipl is 5.
320 	 * Here we disable all interrupts to shorten the zshard
321 	 * handling time.  Otherwise, too many characters are
322 	 * dropped.
323 	 */
324 	s = splhigh();
325 	rval = zsc_intr_hard(zsc);
326 
327 	/* We are at splzs here, so no need to lock. */
328 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
329 		softint_schedule(zsc->zsc_softintr_cookie);
330 	splx(s);
331 
332 	return (rval);
333 }
334 
335 /*
336  * Compute the current baud rate given a ZS channel.
337  */
338 static int
339 zs_get_speed(struct zs_chanstate *cs)
340 {
341 	int tconst;
342 
343 	tconst = zs_read_reg(cs, 12);
344 	tconst |= zs_read_reg(cs, 13) << 8;
345 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
346 }
347 
348 /*
349  * MD functions for setting the baud rate and control modes.
350  */
351 int
352 zs_set_speed(struct zs_chanstate *cs, int bps	/* bits per second */)
353 {
354 	int tconst, real_bps;
355 
356 	if (bps == 0)
357 		return (0);
358 
359 #ifdef	DIAGNOSTIC
360 	if (cs->cs_brg_clk == 0)
361 		panic("zs_set_speed");
362 #endif
363 
364 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
365 	if (tconst < 0)
366 		return (EINVAL);
367 
368 	/* Convert back to make sure we can do it. */
369 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
370 
371 #if 0				/* XXX */
372 	/* XXX - Allow some tolerance here? */
373 	if (real_bps != bps)
374 		return (EINVAL);
375 #else
376 	/*
377 	 * Since our PCLK has somewhat strange value,
378 	 * we have to allow tolerance here.
379 	 */
380 	if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
381 		return (EINVAL);
382 #endif
383 
384 	cs->cs_preg[12] = tconst;
385 	cs->cs_preg[13] = tconst >> 8;
386 
387 	/* Caller will stuff the pending registers. */
388 	return (0);
389 }
390 
391 int
392 zs_set_modes(struct zs_chanstate *cs, int cflag	/* bits per second */)
393 {
394 	int s;
395 
396 	/*
397 	 * Output hardware flow control on the chip is horrendous:
398 	 * if carrier detect drops, the receiver is disabled, and if
399 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
400 	 * Therefore, NEVER set the HFC bit, and instead use the
401 	 * status interrupt to detect CTS changes.
402 	 */
403 	s = splzs();
404 	cs->cs_rr0_pps = 0;
405 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
406 		cs->cs_rr0_dcd = 0;
407 		if ((cflag & MDMBUF) == 0)
408 			cs->cs_rr0_pps = ZSRR0_DCD;
409 	} else
410 		cs->cs_rr0_dcd = ZSRR0_DCD;
411 	if ((cflag & CRTSCTS) != 0) {
412 		cs->cs_wr5_dtr = ZSWR5_DTR;
413 		cs->cs_wr5_rts = ZSWR5_RTS;
414 		cs->cs_rr0_cts = ZSRR0_CTS;
415 	} else if ((cflag & MDMBUF) != 0) {
416 		cs->cs_wr5_dtr = 0;
417 		cs->cs_wr5_rts = ZSWR5_DTR;
418 		cs->cs_rr0_cts = ZSRR0_DCD;
419 	} else {
420 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
421 		cs->cs_wr5_rts = 0;
422 		cs->cs_rr0_cts = 0;
423 	}
424 	splx(s);
425 
426 	/* Caller will stuff the pending registers. */
427 	return (0);
428 }
429 
430 
431 /*
432  * Read or write the chip with suitable delays.
433  */
434 
435 uint8_t
436 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
437 {
438 	uint8_t val;
439 
440 	*cs->cs_reg_csr = reg;
441 	ZS_DELAY();
442 	val = *cs->cs_reg_csr;
443 	ZS_DELAY();
444 	return val;
445 }
446 
447 void
448 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
449 {
450 	*cs->cs_reg_csr = reg;
451 	ZS_DELAY();
452 	*cs->cs_reg_csr = val;
453 	ZS_DELAY();
454 }
455 
456 uint8_t
457 zs_read_csr(struct zs_chanstate *cs)
458 {
459 	uint8_t val;
460 
461 	val = *cs->cs_reg_csr;
462 	ZS_DELAY();
463 	return val;
464 }
465 
466 void
467 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
468 {
469 	*cs->cs_reg_csr = val;
470 	ZS_DELAY();
471 }
472 
473 uint8_t
474 zs_read_data(struct zs_chanstate *cs)
475 {
476 	uint8_t val;
477 
478 	val = *cs->cs_reg_data;
479 	ZS_DELAY();
480 	return val;
481 }
482 
483 void
484 zs_write_data(struct zs_chanstate *cs, uint8_t val)
485 {
486 	*cs->cs_reg_data = val;
487 	ZS_DELAY();
488 }
489 
490 
491 /****************************************************************
492  * Console support functions (x68k specific!)
493  * Note: this code is allowed to know about the layout of
494  * the chip registers, and uses that to keep things simple.
495  * XXX - I think I like the mvme167 code better. -gwr
496  ****************************************************************/
497 
498 /*
499  * Handle user request to enter kernel debugger.
500  */
501 void
502 zs_abort(struct zs_chanstate *cs)
503 {
504 	int rr0;
505 
506 	/* Wait for end of break to avoid PROM abort. */
507 	/* XXX - Limit the wait? */
508 	do {
509 		rr0 = *cs->cs_reg_csr;
510 		ZS_DELAY();
511 	} while (rr0 & ZSRR0_BREAK);
512 
513 #ifdef DDB
514 	Debugger();
515 #else
516 	printf("BREAK!!\n");
517 #endif
518 }
519 
520 
521 #if NZSTTY > 0
522 
523 #include <dev/cons.h>
524 cons_decl(zs);
525 
526 static int zs_getc(void);
527 static void zs_putc(int);
528 
529 static struct zs_chanstate zscn_cs;
530 
531 /*
532  * Polled input char.
533  */
534 static int
535 zs_getc(void)
536 {
537 	int s, c, rr0;
538 
539 	s = splzs();
540 	/* Wait for a character to arrive. */
541 	do {
542 		rr0 = zs_read_csr(&zscn_cs);
543 	} while ((rr0 & ZSRR0_RX_READY) == 0);
544 
545 	c = zs_read_data(&zscn_cs);
546 	splx(s);
547 
548 	/*
549 	 * This is used by the kd driver to read scan codes,
550 	 * so don't translate '\r' ==> '\n' here...
551 	 */
552 	return (c);
553 }
554 
555 /*
556  * Polled output char.
557  */
558 static void
559 zs_putc(int c)
560 {
561 	int s, rr0;
562 
563 	s = splzs();
564 	/* Wait for transmitter to become ready. */
565 	do {
566 		rr0 = zs_read_csr(&zscn_cs);
567 	} while ((rr0 & ZSRR0_TX_READY) == 0);
568 
569 	zs_write_data(&zscn_cs, c);
570 	splx(s);
571 }
572 
573 void
574 zscninit(struct consdev *cn)
575 {
576 	volatile struct zschan *cnchan = (volatile void *)IIOV(ZSCN_PHYSADDR);
577 	int s;
578 
579 	memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
580 	zscn_cs.cs_reg_csr = &cnchan->zc_csr;
581 	zscn_cs.cs_reg_data = &cnchan->zc_data;
582 	zscn_cs.cs_channel = 0;
583 	zscn_cs.cs_brg_clk = PCLK / 16;
584 	memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
585 	zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
586 	zscn_cs.cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
587 	zs_set_speed(&zscn_cs, ZSCN_SPEED);
588 	s = splzs();
589 	zs_write_reg(&zscn_cs, 9, 0);
590 	zs_write_reg(&zscn_cs, 9, ZSWR9_HARD_RESET);
591 	zs_loadchannelregs(&zscn_cs);
592 	splx(s);
593 	conschan = cnchan;
594 }
595 
596 /*
597  * Polled console input putchar.
598  */
599 int
600 zscngetc(dev_t dev)
601 {
602 	return (zs_getc());
603 }
604 
605 /*
606  * Polled console output putchar.
607  */
608 void
609 zscnputc(dev_t dev, int c)
610 {
611 	zs_putc(c);
612 }
613 
614 void
615 zscnprobe(struct consdev *cd)
616 {
617 	int maj;
618 	extern const struct cdevsw zstty_cdevsw;
619 
620 	/* locate the major number */
621 	maj = cdevsw_lookup_major(&zstty_cdevsw);
622 	/* XXX: minor number is 0 */
623 
624 	if (maj == -1)
625 		cd->cn_pri = CN_DEAD;
626 	else {
627 #ifdef ZSCONSOLE
628 		cd->cn_pri = CN_REMOTE;	/* higher than ITE (CN_INTERNAL) */
629 #else
630 		cd->cn_pri = CN_NORMAL;
631 #endif
632 		cd->cn_dev = makedev(maj, 0);
633 	}
634 }
635 
636 void
637 zscnpollc(dev_t dev, int on)
638 {
639 }
640 
641 #endif
642