xref: /netbsd-src/sys/arch/x68k/dev/zs.c (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55) 
1 /*	$NetBSD: zs.c,v 1.42 2014/03/26 08:17:32 christos Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998 Minoura Makoto
5  * Copyright (c) 1996 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Gordon W. Ross.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Zilog Z8530 Dual UART driver (machine-dependent part)
35  *
36  * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
37  * while channel B is dedicated to the mouse.
38  * Extra Z8530's can be installed for serial ports.  This driver
39  * supports up to 5 chips including the built-in one.
40  */
41 
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.42 2014/03/26 08:17:32 christos Exp $");
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/bus.h>
58 #include <sys/intr.h>
59 
60 #include <arch/x68k/dev/intiovar.h>
61 #include <machine/z8530var.h>
62 
63 #include <dev/ic/z8530reg.h>
64 
65 #include "ioconf.h"
66 #include "zsc.h"	/* NZSC */
67 #include "opt_zsc.h"
68 #ifndef ZSCN_SPEED
69 #define ZSCN_SPEED 9600
70 #endif
71 #include "zstty.h"
72 
73 
74 extern void Debugger(void);
75 
76 /*
77  * Some warts needed by z8530tty.c -
78  * The default parity REALLY needs to be the same as the PROM uses,
79  * or you can not see messages done with printf during boot-up...
80  */
81 int zs_def_cflag = (CREAD | CS8 | HUPCL);
82 int zscn_def_cflag = (CREAD | CS8 | HUPCL);
83 
84 /*
85  * X68k provides a 5.0 MHz clock to the ZS chips.
86  */
87 #define PCLK	(5 * 1000 * 1000)	/* PCLK pin input clock rate */
88 
89 
90 /* Default physical addresses. */
91 #define ZS_MAXDEV 5
92 static bus_addr_t zs_physaddr[ZS_MAXDEV] = {
93 	0x00e98000,
94 	0x00eafc00,
95 	0x00eafc10,
96 	0x00eafc20,
97 	0x00eafc30
98 };
99 
100 static uint8_t zs_init_reg[16] = {
101 	0,	/* 0: CMD (reset, etc.) */
102 	0,	/* 1: No interrupts yet. */
103 	0x70,	/* 2: XXX: IVECT */
104 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
105 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
106 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
107 	0,	/* 6: TXSYNC/SYNCLO */
108 	0,	/* 7: RXSYNC/SYNCHI */
109 	0,	/* 8: alias for data port */
110 	ZSWR9_MASTER_IE,
111 	ZSWR10_NRZ,	/*10: Misc. TX/RX control bits */
112 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
113 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
114 	0,			/*13: BAUDHI (default=9600) */
115 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
116 	ZSWR15_BREAK_IE,
117 };
118 
119 static volatile struct zschan *conschan = 0;
120 
121 
122 /****************************************************************
123  * Autoconfig
124  ****************************************************************/
125 
126 /* Definition of the driver for autoconfig. */
127 static int	zs_match(device_t, cfdata_t, void *);
128 static void	zs_attach(device_t, device_t, void *);
129 static int	zs_print(void *, const char *name);
130 
131 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
132     zs_match, zs_attach, NULL, NULL);
133 
134 static int zshard(void *);
135 static int zs_get_speed(struct zs_chanstate *);
136 
137 
138 /*
139  * Is the zs chip present?
140  */
141 static int
142 zs_match(device_t parent, cfdata_t cf, void *aux)
143 {
144 	struct intio_attach_args *ia = aux;
145 	struct zsdevice *zsaddr = (void *)ia->ia_addr;
146 	int i;
147 
148 	if (strcmp(ia->ia_name, "zsc") != 0)
149 		return 0;
150 
151 	for (i = 0; i < ZS_MAXDEV; i++)
152 		if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
153 			break;
154 
155 	ia->ia_size = 8;
156 	if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
157 		return 0;
158 
159 	if (zsaddr != (void *)zs_physaddr[i])
160 		return 0;
161 	if (badaddr((void *)IIOV(zsaddr)))
162 		return 0;
163 
164 	return (1);
165 }
166 
167 /*
168  * Attach a found zs.
169  */
170 static void
171 zs_attach(device_t parent, device_t self, void *aux)
172 {
173 	struct zsc_softc *zsc = device_private(self);
174 	struct intio_attach_args *ia = aux;
175 	struct zsc_attach_args zsc_args;
176 	volatile struct zschan *zc;
177 	struct zs_chanstate *cs;
178 	int r __diagused;
179 	int s, channel;
180 
181 	zsc->zsc_dev = self;
182 	aprint_normal("\n");
183 
184 	zsc->zsc_addr = (void *)ia->ia_addr;
185 
186 	ia->ia_size = 8;
187 	r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
188 #ifdef DIAGNOSTIC
189 	if (r)
190 		panic("zs: intio IO map corruption");
191 #endif
192 
193 	/*
194 	 * Initialize software state for each channel.
195 	 */
196 	for (channel = 0; channel < 2; channel++) {
197 		device_t child;
198 
199 		zsc_args.channel = channel;
200 		zsc_args.hwflags = 0;
201 		cs = &zsc->zsc_cs_store[channel];
202 		zsc->zsc_cs[channel] = cs;
203 
204 		zs_lock_init(cs);
205 		cs->cs_channel = channel;
206 		cs->cs_private = NULL;
207 		cs->cs_ops = &zsops_null;
208 		cs->cs_brg_clk = PCLK / 16;
209 
210 		if (channel == 0)
211 			zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_a);
212 		else
213 			zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_b);
214 		cs->cs_reg_csr  = &zc->zc_csr;
215 		cs->cs_reg_data = &zc->zc_data;
216 
217 		zs_init_reg[2] = ia->ia_intr;
218 		memcpy(cs->cs_creg, zs_init_reg, 16);
219 		memcpy(cs->cs_preg, zs_init_reg, 16);
220 
221 		if (zc == conschan) {
222 			zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
223 			cs->cs_defspeed = zs_get_speed(cs);
224 			cs->cs_defcflag = zscn_def_cflag;
225 		} else {
226 			cs->cs_defspeed = 9600;
227 			cs->cs_defcflag = zs_def_cflag;
228 		}
229 
230 		/* Make these correspond to cs_defcflag (-crtscts) */
231 		cs->cs_rr0_dcd = ZSRR0_DCD;
232 		cs->cs_rr0_cts = 0;
233 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
234 		cs->cs_wr5_rts = 0;
235 
236 		/*
237 		 * Clear the master interrupt enable.
238 		 * The INTENA is common to both channels,
239 		 * so just do it on the A channel.
240 		 */
241 		if (channel == 0) {
242 			s = splzs();
243 			zs_write_reg(cs, 9, 0);
244 			splx(s);
245 		}
246 
247 		/*
248 		 * Look for a child driver for this channel.
249 		 * The child attach will setup the hardware.
250 		 */
251 		child = config_found(self, (void *)&zsc_args, zs_print);
252 #if ZSTTY > 0
253 		if (zc == conschan &&
254 		    ((child && strcmp(device_xname(child), "zstty0")) ||
255 		     child == NULL)) /* XXX */
256 			panic("%s: console device mismatch", __func__);
257 #endif
258 		if (child == NULL) {
259 			/* No sub-driver.  Just reset it. */
260 			uint8_t reset = (channel == 0) ?
261 				ZSWR9_A_RESET : ZSWR9_B_RESET;
262 			s = splzs();
263 			zs_write_reg(cs,  9, reset);
264 			splx(s);
265 		}
266 	}
267 
268 	/*
269 	 * Now safe to install interrupt handlers.
270 	 */
271 	if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
272 		panic("%s: interrupt vector busy", __func__);
273 	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
274 	    (void (*)(void *))zsc_intr_soft, zsc);
275 	/* XXX; evcnt_attach() ? */
276 
277 	/*
278 	 * Set the master interrupt enable and interrupt vector.
279 	 * (common to both channels, do it on A)
280 	 */
281 	cs = zsc->zsc_cs[0];
282 	s = splzs();
283 	/* interrupt vector */
284 	zs_write_reg(cs, 2, ia->ia_intr);
285 	/* master interrupt control (enable) */
286 	zs_write_reg(cs, 9, zs_init_reg[9]);
287 	splx(s);
288 }
289 
290 static int
291 zs_print(void *aux, const char *name)
292 {
293 	struct zsc_attach_args *args = aux;
294 
295 	if (name != NULL)
296 		aprint_normal("%s: ", name);
297 
298 	if (args->channel != -1)
299 		aprint_normal(" channel %d", args->channel);
300 
301 	return UNCONF;
302 }
303 
304 
305 /*
306  * For x68k-port, we don't use autovectored interrupt.
307  * We do not need to look at all of the zs chips.
308  */
309 static int
310 zshard(void *arg)
311 {
312 	struct zsc_softc *zsc = arg;
313 	int rval;
314 	int s;
315 
316 	/*
317 	 * Actually, zs hardware ipl is 5.
318 	 * Here we disable all interrupts to shorten the zshard
319 	 * handling time.  Otherwise, too many characters are
320 	 * dropped.
321 	 */
322 	s = splhigh();
323 	rval = zsc_intr_hard(zsc);
324 
325 	/* We are at splzs here, so no need to lock. */
326 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
327 		softint_schedule(zsc->zsc_softintr_cookie);
328 	splx(s);
329 
330 	return (rval);
331 }
332 
333 /*
334  * Compute the current baud rate given a ZS channel.
335  */
336 static int
337 zs_get_speed(struct zs_chanstate *cs)
338 {
339 	int tconst;
340 
341 	tconst = zs_read_reg(cs, 12);
342 	tconst |= zs_read_reg(cs, 13) << 8;
343 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
344 }
345 
346 /*
347  * MD functions for setting the baud rate and control modes.
348  */
349 int
350 zs_set_speed(struct zs_chanstate *cs, int bps	/* bits per second */)
351 {
352 	int tconst, real_bps;
353 
354 	if (bps == 0)
355 		return (0);
356 
357 #ifdef	DIAGNOSTIC
358 	if (cs->cs_brg_clk == 0)
359 		panic("zs_set_speed");
360 #endif
361 
362 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
363 	if (tconst < 0)
364 		return (EINVAL);
365 
366 	/* Convert back to make sure we can do it. */
367 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
368 
369 #if 0				/* XXX */
370 	/* XXX - Allow some tolerance here? */
371 	if (real_bps != bps)
372 		return (EINVAL);
373 #else
374 	/*
375 	 * Since our PCLK has somewhat strange value,
376 	 * we have to allow tolerance here.
377 	 */
378 	if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
379 		return (EINVAL);
380 #endif
381 
382 	cs->cs_preg[12] = tconst;
383 	cs->cs_preg[13] = tconst >> 8;
384 
385 	/* Caller will stuff the pending registers. */
386 	return (0);
387 }
388 
389 int
390 zs_set_modes(struct zs_chanstate *cs, int cflag	/* bits per second */)
391 {
392 	int s;
393 
394 	/*
395 	 * Output hardware flow control on the chip is horrendous:
396 	 * if carrier detect drops, the receiver is disabled, and if
397 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
398 	 * Therefore, NEVER set the HFC bit, and instead use the
399 	 * status interrupt to detect CTS changes.
400 	 */
401 	s = splzs();
402 	cs->cs_rr0_pps = 0;
403 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
404 		cs->cs_rr0_dcd = 0;
405 		if ((cflag & MDMBUF) == 0)
406 			cs->cs_rr0_pps = ZSRR0_DCD;
407 	} else
408 		cs->cs_rr0_dcd = ZSRR0_DCD;
409 	if ((cflag & CRTSCTS) != 0) {
410 		cs->cs_wr5_dtr = ZSWR5_DTR;
411 		cs->cs_wr5_rts = ZSWR5_RTS;
412 		cs->cs_rr0_cts = ZSRR0_CTS;
413 	} else if ((cflag & MDMBUF) != 0) {
414 		cs->cs_wr5_dtr = 0;
415 		cs->cs_wr5_rts = ZSWR5_DTR;
416 		cs->cs_rr0_cts = ZSRR0_DCD;
417 	} else {
418 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
419 		cs->cs_wr5_rts = 0;
420 		cs->cs_rr0_cts = 0;
421 	}
422 	splx(s);
423 
424 	/* Caller will stuff the pending registers. */
425 	return (0);
426 }
427 
428 
429 /*
430  * Read or write the chip with suitable delays.
431  */
432 
433 uint8_t
434 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
435 {
436 	uint8_t val;
437 
438 	*cs->cs_reg_csr = reg;
439 	ZS_DELAY();
440 	val = *cs->cs_reg_csr;
441 	ZS_DELAY();
442 	return val;
443 }
444 
445 void
446 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
447 {
448 	*cs->cs_reg_csr = reg;
449 	ZS_DELAY();
450 	*cs->cs_reg_csr = val;
451 	ZS_DELAY();
452 }
453 
454 uint8_t
455 zs_read_csr(struct zs_chanstate *cs)
456 {
457 	uint8_t val;
458 
459 	val = *cs->cs_reg_csr;
460 	ZS_DELAY();
461 	return val;
462 }
463 
464 void
465 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
466 {
467 	*cs->cs_reg_csr = val;
468 	ZS_DELAY();
469 }
470 
471 uint8_t
472 zs_read_data(struct zs_chanstate *cs)
473 {
474 	uint8_t val;
475 
476 	val = *cs->cs_reg_data;
477 	ZS_DELAY();
478 	return val;
479 }
480 
481 void
482 zs_write_data(struct zs_chanstate *cs, uint8_t val)
483 {
484 	*cs->cs_reg_data = val;
485 	ZS_DELAY();
486 }
487 
488 
489 /****************************************************************
490  * Console support functions (x68k specific!)
491  * Note: this code is allowed to know about the layout of
492  * the chip registers, and uses that to keep things simple.
493  * XXX - I think I like the mvme167 code better. -gwr
494  ****************************************************************/
495 
496 /*
497  * Handle user request to enter kernel debugger.
498  */
499 void
500 zs_abort(struct zs_chanstate *cs)
501 {
502 	int rr0;
503 
504 	/* Wait for end of break to avoid PROM abort. */
505 	/* XXX - Limit the wait? */
506 	do {
507 		rr0 = *cs->cs_reg_csr;
508 		ZS_DELAY();
509 	} while (rr0 & ZSRR0_BREAK);
510 
511 #ifdef DDB
512 	Debugger();
513 #else
514 	printf("BREAK!!\n");
515 #endif
516 }
517 
518 
519 #if NZSTTY > 0
520 
521 #include <dev/cons.h>
522 cons_decl(zs);
523 
524 static int zs_getc(void);
525 static void zs_putc(int);
526 
527 static struct zs_chanstate zscn_cs;
528 
529 /*
530  * Polled input char.
531  */
532 static int
533 zs_getc(void)
534 {
535 	int s, c, rr0;
536 
537 	s = splzs();
538 	/* Wait for a character to arrive. */
539 	do {
540 		rr0 = zs_read_csr(&zscn_cs);
541 	} while ((rr0 & ZSRR0_RX_READY) == 0);
542 
543 	c = zs_read_data(&zscn_cs);
544 	splx(s);
545 
546 	/*
547 	 * This is used by the kd driver to read scan codes,
548 	 * so don't translate '\r' ==> '\n' here...
549 	 */
550 	return (c);
551 }
552 
553 /*
554  * Polled output char.
555  */
556 static void
557 zs_putc(int c)
558 {
559 	int s, rr0;
560 
561 	s = splzs();
562 	/* Wait for transmitter to become ready. */
563 	do {
564 		rr0 = zs_read_csr(&zscn_cs);
565 	} while ((rr0 & ZSRR0_TX_READY) == 0);
566 
567 	zs_write_data(&zscn_cs, c);
568 	splx(s);
569 }
570 
571 void
572 zscninit(struct consdev *cn)
573 {
574 	volatile struct zschan *cnchan = (volatile void *)IIOV(ZSCN_PHYSADDR);
575 	int s;
576 
577 	memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
578 	zscn_cs.cs_reg_csr = &cnchan->zc_csr;
579 	zscn_cs.cs_reg_data = &cnchan->zc_data;
580 	zscn_cs.cs_channel = 0;
581 	zscn_cs.cs_brg_clk = PCLK / 16;
582 	memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
583 	zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
584 	zscn_cs.cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
585 	zs_set_speed(&zscn_cs, ZSCN_SPEED);
586 	s = splzs();
587 	zs_write_reg(&zscn_cs, 9, 0);
588 	zs_write_reg(&zscn_cs, 9, ZSWR9_HARD_RESET);
589 	zs_loadchannelregs(&zscn_cs);
590 	splx(s);
591 	conschan = cnchan;
592 }
593 
594 /*
595  * Polled console input putchar.
596  */
597 int
598 zscngetc(dev_t dev)
599 {
600 	return (zs_getc());
601 }
602 
603 /*
604  * Polled console output putchar.
605  */
606 void
607 zscnputc(dev_t dev, int c)
608 {
609 	zs_putc(c);
610 }
611 
612 void
613 zscnprobe(struct consdev *cd)
614 {
615 	int maj;
616 	extern const struct cdevsw zstty_cdevsw;
617 
618 	/* locate the major number */
619 	maj = cdevsw_lookup_major(&zstty_cdevsw);
620 	/* XXX: minor number is 0 */
621 
622 	if (maj == -1)
623 		cd->cn_pri = CN_DEAD;
624 	else {
625 #ifdef ZSCONSOLE
626 		cd->cn_pri = CN_REMOTE;	/* higher than ITE (CN_INTERNAL) */
627 #else
628 		cd->cn_pri = CN_NORMAL;
629 #endif
630 		cd->cn_dev = makedev(maj, 0);
631 	}
632 }
633 
634 void
635 zscnpollc(dev_t dev, int on)
636 {
637 }
638 
639 #endif
640