xref: /netbsd-src/sys/arch/x68k/dev/zs.c (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa) 
1 /*	$NetBSD: zs.c,v 1.35 2007/12/03 15:34:25 ad Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998 Minoura Makoto
5  * Copyright (c) 1996 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Gordon W. Ross.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *        This product includes software developed by the NetBSD
22  *        Foundation, Inc. and its contributors.
23  * 4. Neither the name of The NetBSD Foundation nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*
41  * Zilog Z8530 Dual UART driver (machine-dependent part)
42  *
43  * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
44  * while channel B is dedicated to the mouse.
45  * Extra Z8530's can be installed for serial ports.  This driver
46  * supports up to 5 chips including the built-in one.
47  */
48 
49 #include <sys/cdefs.h>
50 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.35 2007/12/03 15:34:25 ad Exp $");
51 
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/conf.h>
55 #include <sys/device.h>
56 #include <sys/file.h>
57 #include <sys/ioctl.h>
58 #include <sys/kernel.h>
59 #include <sys/proc.h>
60 #include <sys/tty.h>
61 #include <sys/time.h>
62 #include <sys/syslog.h>
63 #include <sys/cpu.h>
64 #include <sys/bus.h>
65 #include <sys/intr.h>
66 
67 #include <arch/x68k/dev/intiovar.h>
68 #include <machine/z8530var.h>
69 
70 #include <dev/ic/z8530reg.h>
71 
72 #include "zsc.h"	/* NZSC */
73 #include "opt_zsc.h"
74 #ifndef ZSCN_SPEED
75 #define ZSCN_SPEED 9600
76 #endif
77 #include "zstty.h"
78 
79 
80 extern void Debugger(void);
81 
82 /*
83  * Some warts needed by z8530tty.c -
84  * The default parity REALLY needs to be the same as the PROM uses,
85  * or you can not see messages done with printf during boot-up...
86  */
87 int zs_def_cflag = (CREAD | CS8 | HUPCL);
88 int zscn_def_cflag = (CREAD | CS8 | HUPCL);
89 
90 /*
91  * X68k provides a 5.0 MHz clock to the ZS chips.
92  */
93 #define PCLK	(5 * 1000 * 1000)	/* PCLK pin input clock rate */
94 
95 
96 /* Default physical addresses. */
97 #define ZS_MAXDEV 5
98 static bus_addr_t zs_physaddr[ZS_MAXDEV] = {
99 	0x00e98000,
100 	0x00eafc00,
101 	0x00eafc10,
102 	0x00eafc20,
103 	0x00eafc30
104 };
105 
106 static u_char zs_init_reg[16] = {
107 	0,	/* 0: CMD (reset, etc.) */
108 	0,	/* 1: No interrupts yet. */
109 	0x70,	/* 2: XXX: IVECT */
110 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
111 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
112 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
113 	0,	/* 6: TXSYNC/SYNCLO */
114 	0,	/* 7: RXSYNC/SYNCHI */
115 	0,	/* 8: alias for data port */
116 	ZSWR9_MASTER_IE,
117 	ZSWR10_NRZ,	/*10: Misc. TX/RX control bits */
118 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
119 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
120 	0,			/*13: BAUDHI (default=9600) */
121 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
122 	ZSWR15_BREAK_IE,
123 };
124 
125 static volatile struct zschan *conschan = 0;
126 
127 
128 /****************************************************************
129  * Autoconfig
130  ****************************************************************/
131 
132 /* Definition of the driver for autoconfig. */
133 static int	zs_match(struct device *, struct cfdata *, void *);
134 static void	zs_attach(struct device *, struct device *, void *);
135 static int	zs_print(void *, const char *name);
136 
137 CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
138     zs_match, zs_attach, NULL, NULL);
139 
140 extern struct cfdriver zsc_cd;
141 
142 static int zshard(void *);
143 static int zs_get_speed(struct zs_chanstate *);
144 
145 
146 /*
147  * Is the zs chip present?
148  */
149 static int
150 zs_match(struct device *parent, struct cfdata *cf, void *aux)
151 {
152 	struct intio_attach_args *ia = aux;
153 	struct zsdevice *zsaddr = (void *)ia->ia_addr;
154 	int i;
155 
156 	if (strcmp(ia->ia_name, "zsc") != 0)
157 		return 0;
158 
159 	for (i = 0; i < ZS_MAXDEV; i++)
160 		if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
161 			break;
162 
163 	ia->ia_size = 8;
164 	if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
165 		return 0;
166 
167 	if (zsaddr != (void *)zs_physaddr[i])
168 		return 0;
169 	if (badaddr(INTIO_ADDR(zsaddr)))
170 		return 0;
171 
172 	return (1);
173 }
174 
175 /*
176  * Attach a found zs.
177  */
178 static void
179 zs_attach(struct device *parent, struct device *self, void *aux)
180 {
181 	struct zsc_softc *zsc = (void *)self;
182 	struct intio_attach_args *ia = aux;
183 	struct zsc_attach_args zsc_args;
184 	volatile struct zschan *zc;
185 	struct zs_chanstate *cs;
186 	int r, s, zs_unit, channel;
187 
188 	zs_unit = device_unit(&zsc->zsc_dev);
189 	zsc->zsc_addr = (void *)ia->ia_addr;
190 
191 	ia->ia_size = 8;
192 	r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
193 #ifdef DIAGNOSTIC
194 	if (r)
195 		panic("zs: intio IO map corruption");
196 #endif
197 
198 	printf("\n");
199 
200 	/*
201 	 * Initialize software state for each channel.
202 	 */
203 	for (channel = 0; channel < 2; channel++) {
204 		struct device *child;
205 
206 		zsc_args.channel = channel;
207 		zsc_args.hwflags = 0;
208 		cs = &zsc->zsc_cs_store[channel];
209 		zsc->zsc_cs[channel] = cs;
210 
211 		zs_lock_init(cs);
212 		cs->cs_channel = channel;
213 		cs->cs_private = NULL;
214 		cs->cs_ops = &zsops_null;
215 		cs->cs_brg_clk = PCLK / 16;
216 
217 		if (channel == 0)
218 			zc = (volatile void *)INTIO_ADDR(&zsc->zsc_addr->zs_chan_a);
219 		else
220 			zc = (volatile void *)INTIO_ADDR(&zsc->zsc_addr->zs_chan_b);
221 		cs->cs_reg_csr  = &zc->zc_csr;
222 		cs->cs_reg_data = &zc->zc_data;
223 
224 		zs_init_reg[2] = ia->ia_intr;
225 		memcpy(cs->cs_creg, zs_init_reg, 16);
226 		memcpy(cs->cs_preg, zs_init_reg, 16);
227 
228 		if (zc == conschan) {
229 			zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
230 			cs->cs_defspeed = zs_get_speed(cs);
231 			cs->cs_defcflag = zscn_def_cflag;
232 		} else {
233 			cs->cs_defspeed = 9600;
234 			cs->cs_defcflag = zs_def_cflag;
235 		}
236 
237 		/* Make these correspond to cs_defcflag (-crtscts) */
238 		cs->cs_rr0_dcd = ZSRR0_DCD;
239 		cs->cs_rr0_cts = 0;
240 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
241 		cs->cs_wr5_rts = 0;
242 
243 		/*
244 		 * Clear the master interrupt enable.
245 		 * The INTENA is common to both channels,
246 		 * so just do it on the A channel.
247 		 */
248 		if (channel == 0) {
249 			s = splzs();
250 			zs_write_reg(cs, 9, 0);
251 			splx(s);
252 		}
253 
254 		/*
255 		 * Look for a child driver for this channel.
256 		 * The child attach will setup the hardware.
257 		 */
258 		child = config_found(self, (void *)&zsc_args, zs_print);
259 #if ZSTTY > 0
260 		if (zc == conschan &&
261 		    ((child && strcmp(child->dv_xname, "zstty0")) ||
262 		     child == NULL)) /* XXX */
263 			panic("zs_attach: console device mismatch");
264 #endif
265 		if (child == NULL) {
266 			/* No sub-driver.  Just reset it. */
267 			u_char reset = (channel == 0) ?
268 				ZSWR9_A_RESET : ZSWR9_B_RESET;
269 			s = splzs();
270 			zs_write_reg(cs,  9, reset);
271 			splx(s);
272 		}
273 	}
274 
275 	/*
276 	 * Now safe to install interrupt handlers.
277 	 */
278 	if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
279 		panic("zs_attach: interrupt vector busy");
280 	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
281 	    (void (*)(void *))zsc_intr_soft, zsc);
282 	/* XXX; evcnt_attach() ? */
283 
284 	/*
285 	 * Set the master interrupt enable and interrupt vector.
286 	 * (common to both channels, do it on A)
287 	 */
288 	cs = zsc->zsc_cs[0];
289 	s = splzs();
290 	/* interrupt vector */
291 	zs_write_reg(cs, 2, ia->ia_intr);
292 	/* master interrupt control (enable) */
293 	zs_write_reg(cs, 9, zs_init_reg[9]);
294 	splx(s);
295 }
296 
297 static int
298 zs_print(void *aux, const char *name)
299 {
300 	struct zsc_attach_args *args = aux;
301 
302 	if (name != NULL)
303 		aprint_normal("%s: ", name);
304 
305 	if (args->channel != -1)
306 		aprint_normal(" channel %d", args->channel);
307 
308 	return UNCONF;
309 }
310 
311 
312 /*
313  * For x68k-port, we don't use autovectored interrupt.
314  * We do not need to look at all of the zs chips.
315  */
316 static int
317 zshard(void *arg)
318 {
319 	struct zsc_softc *zsc = arg;
320 	int rval;
321 	int s;
322 
323 	/*
324 	 * Actually, zs hardware ipl is 5.
325 	 * Here we disable all interrupts to shorten the zshard
326 	 * handling time.  Otherwise, too many characters are
327 	 * dropped.
328 	 */
329 	s = splhigh();
330 	rval = zsc_intr_hard(zsc);
331 
332 	/* We are at splzs here, so no need to lock. */
333 	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
334 		softint_schedule(zsc->zsc_softintr_cookie);
335 
336 	return (rval);
337 }
338 
339 /*
340  * Compute the current baud rate given a ZS channel.
341  */
342 static int
343 zs_get_speed(struct zs_chanstate *cs)
344 {
345 	int tconst;
346 
347 	tconst = zs_read_reg(cs, 12);
348 	tconst |= zs_read_reg(cs, 13) << 8;
349 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
350 }
351 
352 /*
353  * MD functions for setting the baud rate and control modes.
354  */
355 int
356 zs_set_speed(struct zs_chanstate *cs, int bps	/* bits per second */)
357 {
358 	int tconst, real_bps;
359 
360 	if (bps == 0)
361 		return (0);
362 
363 #ifdef	DIAGNOSTIC
364 	if (cs->cs_brg_clk == 0)
365 		panic("zs_set_speed");
366 #endif
367 
368 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
369 	if (tconst < 0)
370 		return (EINVAL);
371 
372 	/* Convert back to make sure we can do it. */
373 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
374 
375 #if 0				/* XXX */
376 	/* XXX - Allow some tolerance here? */
377 	if (real_bps != bps)
378 		return (EINVAL);
379 #else
380 	/*
381 	 * Since our PCLK has somewhat strange value,
382 	 * we have to allow tolerance here.
383 	 */
384 	if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
385 		return (EINVAL);
386 #endif
387 
388 	cs->cs_preg[12] = tconst;
389 	cs->cs_preg[13] = tconst >> 8;
390 
391 	/* Caller will stuff the pending registers. */
392 	return (0);
393 }
394 
395 int
396 zs_set_modes(struct zs_chanstate *cs, int cflag	/* bits per second */)
397 {
398 	int s;
399 
400 	/*
401 	 * Output hardware flow control on the chip is horrendous:
402 	 * if carrier detect drops, the receiver is disabled, and if
403 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
404 	 * Therefore, NEVER set the HFC bit, and instead use the
405 	 * status interrupt to detect CTS changes.
406 	 */
407 	s = splzs();
408 	cs->cs_rr0_pps = 0;
409 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
410 		cs->cs_rr0_dcd = 0;
411 		if ((cflag & MDMBUF) == 0)
412 			cs->cs_rr0_pps = ZSRR0_DCD;
413 	} else
414 		cs->cs_rr0_dcd = ZSRR0_DCD;
415 	if ((cflag & CRTSCTS) != 0) {
416 		cs->cs_wr5_dtr = ZSWR5_DTR;
417 		cs->cs_wr5_rts = ZSWR5_RTS;
418 		cs->cs_rr0_cts = ZSRR0_CTS;
419 	} else if ((cflag & MDMBUF) != 0) {
420 		cs->cs_wr5_dtr = 0;
421 		cs->cs_wr5_rts = ZSWR5_DTR;
422 		cs->cs_rr0_cts = ZSRR0_DCD;
423 	} else {
424 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
425 		cs->cs_wr5_rts = 0;
426 		cs->cs_rr0_cts = 0;
427 	}
428 	splx(s);
429 
430 	/* Caller will stuff the pending registers. */
431 	return (0);
432 }
433 
434 
435 /*
436  * Read or write the chip with suitable delays.
437  */
438 
439 u_char
440 zs_read_reg(struct zs_chanstate *cs, u_char reg)
441 {
442 	u_char val;
443 
444 	*cs->cs_reg_csr = reg;
445 	ZS_DELAY();
446 	val = *cs->cs_reg_csr;
447 	ZS_DELAY();
448 	return val;
449 }
450 
451 void
452 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
453 {
454 	*cs->cs_reg_csr = reg;
455 	ZS_DELAY();
456 	*cs->cs_reg_csr = val;
457 	ZS_DELAY();
458 }
459 
460 u_char
461 zs_read_csr(struct zs_chanstate *cs)
462 {
463 	u_char val;
464 
465 	val = *cs->cs_reg_csr;
466 	ZS_DELAY();
467 	return val;
468 }
469 
470 void
471 zs_write_csr(struct zs_chanstate *cs, u_char val)
472 {
473 	*cs->cs_reg_csr = val;
474 	ZS_DELAY();
475 }
476 
477 u_char
478 zs_read_data(struct zs_chanstate *cs)
479 {
480 	u_char val;
481 
482 	val = *cs->cs_reg_data;
483 	ZS_DELAY();
484 	return val;
485 }
486 
487 void
488 zs_write_data(struct zs_chanstate *cs, u_char val)
489 {
490 	*cs->cs_reg_data = val;
491 	ZS_DELAY();
492 }
493 
494 
495 static struct zs_chanstate zscn_cs;
496 
497 /****************************************************************
498  * Console support functions (x68k specific!)
499  * Note: this code is allowed to know about the layout of
500  * the chip registers, and uses that to keep things simple.
501  * XXX - I think I like the mvme167 code better. -gwr
502  ****************************************************************/
503 
504 /*
505  * Handle user request to enter kernel debugger.
506  */
507 void
508 zs_abort(struct zs_chanstate *cs)
509 {
510 	int rr0;
511 
512 	/* Wait for end of break to avoid PROM abort. */
513 	/* XXX - Limit the wait? */
514 	do {
515 		rr0 = *cs->cs_reg_csr;
516 		ZS_DELAY();
517 	} while (rr0 & ZSRR0_BREAK);
518 
519 #ifdef DDB
520 	Debugger();
521 #else
522 	printf("BREAK!!\n");
523 #endif
524 }
525 
526 
527 #if NZSTTY > 0
528 
529 #include <dev/cons.h>
530 cons_decl(zs);
531 
532 static int zs_getc(void);
533 static void zs_putc(int);
534 
535 /*
536  * Polled input char.
537  */
538 static int
539 zs_getc(void)
540 {
541 	int s, c, rr0;
542 
543 	s = splzs();
544 	/* Wait for a character to arrive. */
545 	do {
546 		rr0 = zs_read_csr(&zscn_cs);
547 	} while ((rr0 & ZSRR0_RX_READY) == 0);
548 
549 	c = zs_read_data(&zscn_cs);
550 	splx(s);
551 
552 	/*
553 	 * This is used by the kd driver to read scan codes,
554 	 * so don't translate '\r' ==> '\n' here...
555 	 */
556 	return (c);
557 }
558 
559 /*
560  * Polled output char.
561  */
562 static void
563 zs_putc(int c)
564 {
565 	int s, rr0;
566 
567 	s = splzs();
568 	/* Wait for transmitter to become ready. */
569 	do {
570 		rr0 = zs_read_csr(&zscn_cs);
571 	} while ((rr0 & ZSRR0_TX_READY) == 0);
572 
573 	zs_write_data(&zscn_cs, c);
574 	splx(s);
575 }
576 
577 void
578 zscninit(struct consdev *cn)
579 {
580 	volatile struct zschan *cnchan = (volatile void *)INTIO_ADDR(ZSCN_PHYSADDR);
581 	int s;
582 
583 	memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
584 	zscn_cs.cs_reg_csr = &cnchan->zc_csr;
585 	zscn_cs.cs_reg_data = &cnchan->zc_data;
586 	zscn_cs.cs_channel = 0;
587 	zscn_cs.cs_brg_clk = PCLK / 16;
588 	memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
589 	zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
590 	zscn_cs.cs_preg[9] = 0;
591 	zs_set_speed(&zscn_cs, ZSCN_SPEED);
592 	s = splzs();
593 	zs_loadchannelregs(&zscn_cs);
594 	splx(s);
595 	conschan = cnchan;
596 }
597 
598 /*
599  * Polled console input putchar.
600  */
601 int
602 zscngetc(dev_t dev)
603 {
604 	return (zs_getc());
605 }
606 
607 /*
608  * Polled console output putchar.
609  */
610 void
611 zscnputc(dev_t dev, int c)
612 {
613 	zs_putc(c);
614 }
615 
616 void
617 zscnprobe(struct consdev *cd)
618 {
619 	int maj;
620 	extern const struct cdevsw zstty_cdevsw;
621 
622 	/* locate the major number */
623 	maj = cdevsw_lookup_major(&zstty_cdevsw);
624 	/* XXX: minor number is 0 */
625 
626 	if (maj == -1)
627 		cd->cn_pri = CN_DEAD;
628 	else {
629 #ifdef ZSCONSOLE
630 		cd->cn_pri = CN_REMOTE;	/* higher than ITE (CN_INTERNAL) */
631 #else
632 		cd->cn_pri = CN_NORMAL;
633 #endif
634 		cd->cn_dev = makedev(maj, 0);
635 	}
636 }
637 
638 void
639 zscnpollc(dev_t dev, int on)
640 {
641 }
642 
643 #endif
644