1 /* $NetBSD: mha.c,v 1.29 2002/05/30 22:21:51 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 189 #define Debugger() panic("should call debugger here (mha.c)") 190 #endif /* ! DDB */ 191 192 193 #if SPC_DEBUG 194 #define SPC_SHOWACBS 0x01 195 #define SPC_SHOWINTS 0x02 196 #define SPC_SHOWCMDS 0x04 197 #define SPC_SHOWMISC 0x08 198 #define SPC_SHOWTRAC 0x10 199 #define SPC_SHOWSTART 0x20 200 #define SPC_SHOWPHASE 0x40 201 #define SPC_SHOWDMA 0x80 202 #define SPC_SHOWCCMDS 0x100 203 #define SPC_SHOWMSGS 0x200 204 #define SPC_DOBREAK 0x400 205 206 int mha_debug = 207 #if 0 208 0x7FF; 209 #else 210 SPC_SHOWSTART|SPC_SHOWTRAC; 211 #endif 212 213 214 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 215 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 216 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 217 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 218 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 219 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 220 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 221 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 222 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 223 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 224 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 225 #else 226 #define SPC_ACBS(str) 227 #define SPC_MISC(str) 228 #define SPC_INTS(str) 229 #define SPC_TRACE(str) 230 #define SPC_CMDS(str) 231 #define SPC_START(str) 232 #define SPC_PHASE(str) 233 #define SPC_DMA(str) 234 #define SPC_MSGS(str) 235 #define SPC_BREAK() 236 #define SPC_ASSERT(x) 237 #endif 238 239 int mhamatch __P((struct device *, struct cfdata *, void *)); 240 void mhaattach __P((struct device *, struct device *, void *)); 241 void mhaselect __P((struct mha_softc *, 242 u_char, u_char, u_char *, u_char)); 243 void mha_scsi_reset __P((struct mha_softc *)); 244 void mha_reset __P((struct mha_softc *)); 245 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 246 void mha_sense __P((struct mha_softc *, struct acb *)); 247 void mha_msgin __P((struct mha_softc *)); 248 void mha_msgout __P((struct mha_softc *)); 249 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 250 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_dataout __P((struct mha_softc *, u_char *, int)); 252 int mha_datain __P((struct mha_softc *, u_char *, int)); 253 void mha_abort __P((struct mha_softc *, struct acb *)); 254 void mha_init __P((struct mha_softc *)); 255 void mha_scsi_request __P((struct scsipi_channel *, 256 scsipi_adapter_req_t, void *)); 257 void mha_poll __P((struct mha_softc *, struct acb *)); 258 void mha_sched __P((struct mha_softc *)); 259 void mha_done __P((struct mha_softc *, struct acb *)); 260 int mhaintr __P((void*)); 261 void mha_timeout __P((void *)); 262 void mha_minphys __P((struct buf *)); 263 void mha_dequeue __P((struct mha_softc *, struct acb *)); 264 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 265 #if SPC_DEBUG 266 void mha_print_acb __P((struct acb *)); 267 void mha_show_scsi_cmd __P((struct acb *)); 268 void mha_print_active_acb __P((void)); 269 void mha_dump_driver __P((struct mha_softc *)); 270 #endif 271 272 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 273 274 struct cfattach mha_ca = { 275 sizeof(struct mha_softc), mhamatch, mhaattach 276 }; 277 278 extern struct cfdriver mha_cd; 279 280 281 /* 282 * returns non-zero value if a controller is found. 283 */ 284 int 285 mhamatch(parent, cf, aux) 286 struct device *parent; 287 struct cfdata *cf; 288 void *aux; 289 { 290 struct intio_attach_args *ia = aux; 291 bus_space_tag_t iot = ia->ia_bst; 292 bus_space_handle_t ioh; 293 294 ia->ia_size=0x20; 295 if (ia->ia_addr != 0xea0000) 296 return 0; 297 298 if (intio_map_allocate_region(parent->dv_parent, ia, 299 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 300 return 0; 301 302 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 303 &ioh) < 0) 304 return 0; 305 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 306 return 0; 307 bus_space_unmap(iot, ioh, 0x20); 308 309 return 1; 310 } 311 312 /* 313 */ 314 315 struct mha_softc *tmpsc; 316 317 void 318 mhaattach(parent, self, aux) 319 struct device *parent, *self; 320 void *aux; 321 { 322 struct mha_softc *sc = (void *)self; 323 struct intio_attach_args *ia = aux; 324 325 tmpsc = sc; /* XXX */ 326 327 printf (": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 328 329 SPC_TRACE(("mhaattach ")); 330 sc->sc_state = SPC_INIT; 331 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 332 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 333 /* XXX: FAKE */ 334 sc->sc_dmat = ia->ia_dmat; 335 336 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 337 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 338 sc->sc_pcx = &sc->sc_pc[0x10]; 339 340 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 341 342 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 343 344 mha_init(sc); /* Init chip and driver */ 345 346 mha_scsi_reset(sc); /* XXX: some devices need this. */ 347 348 sc->sc_phase = BUSFREE_PHASE; 349 350 /* 351 * Fill in the adapter. 352 */ 353 sc->sc_adapter.adapt_dev = &sc->sc_dev; 354 sc->sc_adapter.adapt_nchannels = 1; 355 sc->sc_adapter.adapt_openings = 7; 356 sc->sc_adapter.adapt_max_periph = 1; 357 sc->sc_adapter.adapt_ioctl = NULL; 358 sc->sc_adapter.adapt_minphys = mha_minphys; 359 sc->sc_adapter.adapt_request = mha_scsi_request; 360 361 sc->sc_channel.chan_adapter = &sc->sc_adapter; 362 sc->sc_channel.chan_bustype = &scsi_bustype; 363 sc->sc_channel.chan_channel = 0; 364 sc->sc_channel.chan_ntargets = 8; 365 sc->sc_channel.chan_nluns = 8; 366 sc->sc_channel.chan_id = sc->sc_id; 367 368 sc->sc_spcinitialized = 0; 369 WAR = WA_INITWIN; 370 #if 1 371 CCR = 0x14; 372 OIR = sc->sc_id; 373 AMR = 0x00; 374 SMR = 0x00; 375 SRR = 0x00; 376 STR = 0x20; 377 RTR = 0x40; 378 ATR = 0x01; 379 PER = 0xc9; 380 #endif 381 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 382 #if 1 383 GLR = 0x00; 384 DMR = 0x30; 385 IMR = 0x00; 386 #endif 387 WAR = WA_MCSBUFWIN; 388 389 /* drop off */ 390 while (SSR & SS_IREQUEST) 391 { 392 (void) ISCSR; 393 } 394 395 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 396 397 SPC_TRACE(("waiting for intr...")); 398 while (!(SSR & SS_IREQUEST)) 399 delay(10); 400 mhaintr (sc); 401 402 tmpsc = NULL; 403 404 config_found(self, &sc->sc_channel, scsiprint); 405 } 406 407 #if 0 408 void 409 mha_reset(sc) 410 struct mha_softc *sc; 411 { 412 u_short dummy; 413 printf("reset..."); 414 CMR = CMD_SOFT_RESET; 415 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 416 dummy = sc->sc_ps[-1]; 417 dummy = sc->sc_ps[-1]; 418 dummy = sc->sc_ps[-1]; 419 dummy = sc->sc_ps[-1]; 420 asm volatile ("nop"); 421 CMR = CMD_SOFT_RESET; 422 sc->sc_spcinitialized = 0; 423 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 424 while(!sc->sc_spcinitialized); 425 426 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 427 printf("done.\n"); 428 } 429 #endif 430 431 /* 432 * Pull the SCSI RST line for 500us. 433 */ 434 void 435 mha_scsi_reset(sc) /* FINISH? */ 436 struct mha_softc *sc; 437 { 438 439 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 440 while (!(SSR&SS_IREQUEST)) 441 delay(10); 442 } 443 444 /* 445 * Initialize mha SCSI driver. 446 */ 447 void 448 mha_init(sc) 449 struct mha_softc *sc; 450 { 451 struct acb *acb; 452 int r; 453 454 if (sc->sc_state == SPC_INIT) { 455 /* First time through; initialize. */ 456 TAILQ_INIT(&sc->ready_list); 457 TAILQ_INIT(&sc->nexus_list); 458 TAILQ_INIT(&sc->free_list); 459 sc->sc_nexus = NULL; 460 acb = sc->sc_acb; 461 memset(acb, 0, sizeof(sc->sc_acb)); 462 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 463 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 464 acb++; 465 } 466 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 467 468 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 469 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 470 BUS_DMA_NOWAIT); 471 if (r) 472 panic("mha_init: cannot allocate dma memory"); 473 if (sc->sc_ndmasegs != 1) 474 panic("mha_init: number of segment > 1??"); 475 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 476 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 477 if (r) 478 panic("mha_init: cannot map dma memory"); 479 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 480 MAXBSIZE, 0, BUS_DMA_NOWAIT, 481 &sc->sc_dmamap); 482 if (r) 483 panic("mha_init: cannot create dmamap structure"); 484 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 485 sc->sc_dmabuf, MAXBSIZE, NULL, 486 BUS_DMA_NOWAIT); 487 if (r) 488 panic("mha_init: cannot load dma buffer into dmamap"); 489 sc->sc_p = 0; 490 } else { 491 /* Cancel any active commands. */ 492 sc->sc_flags |= SPC_ABORTING; 493 sc->sc_state = SPC_IDLE; 494 if ((acb = sc->sc_nexus) != NULL) { 495 acb->xs->error = XS_DRIVER_STUFFUP; 496 mha_done(sc, acb); 497 } 498 while ((acb = sc->nexus_list.tqh_first) != NULL) { 499 acb->xs->error = XS_DRIVER_STUFFUP; 500 mha_done(sc, acb); 501 } 502 } 503 504 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 505 for (r = 0; r < 8; r++) { 506 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 507 508 ti->flags = 0; 509 #if SPC_USE_SYNCHRONOUS 510 ti->flags |= T_SYNCMODE; 511 ti->period = sc->sc_minsync; 512 ti->offset = SPC_SYNC_REQ_ACK_OFS; 513 #else 514 ti->period = ti->offset = 0; 515 #endif 516 ti->width = 0; 517 } 518 519 sc->sc_state = SPC_IDLE; 520 } 521 522 void 523 mha_free_acb(sc, acb, flags) 524 struct mha_softc *sc; 525 struct acb *acb; 526 int flags; 527 { 528 int s; 529 530 s = splbio(); 531 532 acb->flags = 0; 533 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 534 535 /* 536 * If there were none, wake anybody waiting for one to come free, 537 * starting with queued entries. 538 */ 539 if (acb->chain.tqe_next == 0) 540 wakeup(&sc->free_list); 541 542 splx(s); 543 } 544 545 546 /* 547 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 548 */ 549 550 /* 551 * Expected sequence: 552 * 1) Command inserted into ready list 553 * 2) Command selected for execution 554 * 3) Command won arbitration and has selected target device 555 * 4) Send message out (identify message, eventually also sync.negotiations) 556 * 5) Send command 557 * 5a) Receive disconnect message, disconnect. 558 * 5b) Reselected by target 559 * 5c) Receive identify message from target. 560 * 6) Send or receive data 561 * 7) Receive status 562 * 8) Receive message (command complete etc.) 563 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 564 * Repeat 2-8 (no disconnects please...) 565 */ 566 567 /* 568 * Start a selection. This is used by mha_sched() to select an idle target, 569 * and by mha_done() to immediately reselect a target to get sense information. 570 */ 571 void 572 mhaselect(sc, target, lun, cmd, clen) 573 struct mha_softc *sc; 574 u_char target, lun; 575 u_char *cmd; 576 u_char clen; 577 { 578 int i; 579 int s; 580 581 s = splbio(); /* XXX */ 582 583 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 584 585 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 586 /* Now the command into the FIFO */ 587 WAIT; 588 #if 1 589 SPC_MISC(("[cmd:")); 590 for (i = 0; i < clen; i++) 591 { 592 unsigned c = cmd[i]; 593 if (i == 1) 594 c |= lun << 5; 595 SPC_MISC((" %02x", c)); 596 sc->sc_pcx[i] = c; 597 } 598 SPC_MISC(("], target=%d\n", target)); 599 #else 600 memcpy(sc->sc_pcx, cmd, clen); 601 #endif 602 if (NSR & 0x80) 603 panic("scsistart: already selected..."); 604 sc->sc_phase = COMMAND_PHASE; 605 606 /* new state ASP_SELECTING */ 607 sc->sc_state = SPC_SELECTING; 608 609 SIR = target; 610 #if 0 611 CMR = CMD_SELECT; 612 #else 613 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 614 #endif 615 splx(s); 616 } 617 618 #if 0 619 int 620 mha_reselect(sc, message) 621 struct mha_softc *sc; 622 u_char message; 623 { 624 u_char selid, target, lun; 625 struct acb *acb; 626 struct scsipi_periph *periph; 627 struct spc_tinfo *ti; 628 629 /* 630 * The SCSI chip made a snapshot of the data bus while the reselection 631 * was being negotiated. This enables us to determine which target did 632 * the reselect. 633 */ 634 selid = sc->sc_selid & ~(1 << sc->sc_id); 635 if (selid & (selid - 1)) { 636 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 637 sc->sc_dev.dv_xname, selid); 638 SPC_BREAK(); 639 goto reset; 640 } 641 642 /* 643 * Search wait queue for disconnected cmd 644 * The list should be short, so I haven't bothered with 645 * any more sophisticated structures than a simple 646 * singly linked list. 647 */ 648 target = ffs(selid) - 1; 649 lun = message & 0x07; 650 for (acb = sc->nexus_list.tqh_first; acb != NULL; 651 acb = acb->chain.tqe_next) { 652 periph = acb->xs->xs_periph; 653 if (periph->periph_target == target && 654 periph->periph_lun == lun) 655 break; 656 } 657 if (acb == NULL) { 658 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 659 sc->sc_dev.dv_xname, target, lun); 660 SPC_BREAK(); 661 goto abort; 662 } 663 664 /* Make this nexus active again. */ 665 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 666 sc->sc_state = SPC_HASNEXUS; 667 sc->sc_nexus = acb; 668 ti = &sc->sc_tinfo[target]; 669 ti->lubusy |= (1 << lun); 670 mha_setsync(sc, ti); 671 672 if (acb->flags & ACB_RESET) 673 mha_sched_msgout(sc, SEND_DEV_RESET); 674 else if (acb->flags & ACB_ABORTED) 675 mha_sched_msgout(sc, SEND_ABORT); 676 677 /* Do an implicit RESTORE POINTERS. */ 678 sc->sc_dp = acb->daddr; 679 sc->sc_dleft = acb->dleft; 680 sc->sc_cp = (u_char *)&acb->cmd; 681 sc->sc_cleft = acb->clen; 682 683 return (0); 684 685 reset: 686 mha_sched_msgout(sc, SEND_DEV_RESET); 687 return (1); 688 689 abort: 690 mha_sched_msgout(sc, SEND_ABORT); 691 return (1); 692 } 693 #endif 694 /* 695 * Start a SCSI-command 696 * This function is called by the higher level SCSI-driver to queue/run 697 * SCSI-commands. 698 */ 699 void 700 mha_scsi_request(chan, req, arg) 701 struct scsipi_channel *chan; 702 scsipi_adapter_req_t req; 703 void *arg; 704 { 705 struct scsipi_xfer *xs; 706 struct scsipi_periph *periph; 707 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 708 struct acb *acb; 709 int s, flags; 710 711 switch (req) { 712 case ADAPTER_REQ_RUN_XFER: 713 xs = arg; 714 periph = xs->xs_periph; 715 716 SPC_TRACE(("[mha_scsi_cmd] ")); 717 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 718 periph->periph_target)); 719 720 flags = xs->xs_control; 721 722 /* Get a mha command block */ 723 s = splbio(); 724 acb = sc->free_list.tqh_first; 725 if (acb) { 726 TAILQ_REMOVE(&sc->free_list, acb, chain); 727 ACB_SETQ(acb, ACB_QNONE); 728 } 729 730 if (acb == NULL) { 731 xs->error = XS_RESOURCE_SHORTAGE; 732 scsipi_done(xs); 733 splx(s); 734 return; 735 } 736 splx(s); 737 738 /* Initialize acb */ 739 acb->xs = xs; 740 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 741 acb->clen = xs->cmdlen; 742 acb->daddr = xs->data; 743 acb->dleft = xs->datalen; 744 acb->stat = 0; 745 746 s = splbio(); 747 ACB_SETQ(acb, ACB_QREADY); 748 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 749 #if 1 750 callout_reset(&acb->xs->xs_callout, 751 mstohz(xs->timeout), mha_timeout, acb); 752 #endif 753 754 /* 755 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 756 */ 757 if (sc->sc_state == SPC_IDLE) 758 mha_sched(sc); 759 760 splx(s); 761 762 if (flags & XS_CTL_POLL) { 763 /* Not allowed to use interrupts, use polling instead */ 764 mha_poll(sc, acb); 765 } 766 767 SPC_MISC(("SUCCESSFULLY_QUEUED")); 768 return; 769 770 case ADAPTER_REQ_GROW_RESOURCES: 771 /* XXX Not supported. */ 772 return; 773 774 case ADAPTER_REQ_SET_XFER_MODE: 775 /* XXX Not supported. */ 776 return; 777 } 778 } 779 780 /* 781 * Adjust transfer size in buffer structure 782 */ 783 void 784 mha_minphys(bp) 785 struct buf *bp; 786 { 787 788 SPC_TRACE(("mha_minphys ")); 789 minphys(bp); 790 } 791 792 /* 793 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 794 */ 795 void 796 mha_poll(sc, acb) 797 struct mha_softc *sc; 798 struct acb *acb; 799 { 800 struct scsipi_xfer *xs = acb->xs; 801 int count = xs->timeout * 100; 802 int s = splbio(); 803 804 SPC_TRACE(("[mha_poll] ")); 805 806 while (count) { 807 /* 808 * If we had interrupts enabled, would we 809 * have got an interrupt? 810 */ 811 if (SSR & SS_IREQUEST) 812 mhaintr(sc); 813 if ((xs->xs_status & XS_STS_DONE) != 0) 814 break; 815 DELAY(10); 816 #if 1 817 if (sc->sc_state == SPC_IDLE) { 818 SPC_TRACE(("[mha_poll: rescheduling] ")); 819 mha_sched(sc); 820 } 821 #endif 822 count--; 823 } 824 825 if (count == 0) { 826 SPC_MISC(("mha_poll: timeout")); 827 mha_timeout((caddr_t)acb); 828 } 829 splx(s); 830 scsipi_done(xs); 831 } 832 833 /* 834 * LOW LEVEL SCSI UTILITIES 835 */ 836 837 /* 838 * Set synchronous transfer offset and period. 839 */ 840 inline void 841 mha_setsync(sc, ti) 842 struct mha_softc *sc; 843 struct spc_tinfo *ti; 844 { 845 } 846 847 848 /* 849 * Schedule a SCSI operation. This has now been pulled out of the interrupt 850 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 851 * save us an unecessary interrupt just to get things going. Should only be 852 * called when state == SPC_IDLE and at bio pl. 853 */ 854 void 855 mha_sched(sc) 856 register struct mha_softc *sc; 857 { 858 struct scsipi_periph *periph; 859 struct acb *acb; 860 int t; 861 862 SPC_TRACE(("[mha_sched] ")); 863 if (sc->sc_state != SPC_IDLE) 864 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 865 866 if (sc->sc_flags & SPC_ABORTING) 867 return; 868 869 /* 870 * Find first acb in ready queue that is for a target/lunit 871 * combinations that is not busy. 872 */ 873 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 874 struct spc_tinfo *ti; 875 periph = acb->xs->xs_periph; 876 t = periph->periph_target; 877 ti = &sc->sc_tinfo[t]; 878 if (!(ti->lubusy & (1 << periph->periph_lun))) { 879 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 880 panic("mha: busy entry on ready list"); 881 TAILQ_REMOVE(&sc->ready_list, acb, chain); 882 ACB_SETQ(acb, ACB_QNONE); 883 sc->sc_nexus = acb; 884 sc->sc_flags = 0; 885 sc->sc_prevphase = INVALID_PHASE; 886 sc->sc_dp = acb->daddr; 887 sc->sc_dleft = acb->dleft; 888 ti->lubusy |= (1<<periph->periph_lun); 889 mhaselect(sc, t, periph->periph_lun, 890 (u_char *)&acb->cmd, acb->clen); 891 break; 892 } else { 893 SPC_MISC(("%d:%d busy\n", 894 periph->periph_target, 895 periph->periph_lun)); 896 } 897 } 898 } 899 900 /* 901 * POST PROCESSING OF SCSI_CMD (usually current) 902 */ 903 void 904 mha_done(sc, acb) 905 struct mha_softc *sc; 906 struct acb *acb; 907 { 908 struct scsipi_xfer *xs = acb->xs; 909 struct scsipi_periph *periph = xs->xs_periph; 910 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 911 912 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 913 914 #if 1 915 callout_stop(&acb->xs->xs_callout); 916 #endif 917 918 /* 919 * Now, if we've come here with no error code, i.e. we've kept the 920 * initial XS_NOERROR, and the status code signals that we should 921 * check sense, we'll need to set up a request sense cmd block and 922 * push the command back into the ready queue *before* any other 923 * commands for this target/lunit, else we lose the sense info. 924 * We don't support chk sense conditions for the request sense cmd. 925 */ 926 if (xs->error == XS_NOERROR) { 927 if ((acb->flags & ACB_ABORTED) != 0) { 928 xs->error = XS_TIMEOUT; 929 } else if (acb->flags & ACB_CHKSENSE) { 930 xs->error = XS_SENSE; 931 } else { 932 xs->status = acb->stat & ST_MASK; 933 switch (xs->status) { 934 case SCSI_CHECK: 935 xs->resid = acb->dleft; 936 /* FALLTHOUGH */ 937 case SCSI_BUSY: 938 xs->error = XS_BUSY; 939 break; 940 case SCSI_OK: 941 xs->resid = acb->dleft; 942 break; 943 default: 944 xs->error = XS_DRIVER_STUFFUP; 945 #if SPC_DEBUG 946 printf("%s: mha_done: bad stat 0x%x\n", 947 sc->sc_dev.dv_xname, acb->stat); 948 #endif 949 break; 950 } 951 } 952 } 953 954 #if SPC_DEBUG 955 if ((mha_debug & SPC_SHOWMISC) != 0) { 956 if (xs->resid != 0) 957 printf("resid=%d ", xs->resid); 958 if (xs->error == XS_SENSE) 959 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 960 else 961 printf("error=%d\n", xs->error); 962 } 963 #endif 964 965 /* 966 * Remove the ACB from whatever queue it's on. 967 */ 968 switch (acb->flags & ACB_QBITS) { 969 case ACB_QNONE: 970 if (acb != sc->sc_nexus) { 971 panic("%s: floating acb", sc->sc_dev.dv_xname); 972 } 973 sc->sc_nexus = NULL; 974 sc->sc_state = SPC_IDLE; 975 ti->lubusy &= ~(1<<periph->periph_lun); 976 mha_sched(sc); 977 break; 978 case ACB_QREADY: 979 TAILQ_REMOVE(&sc->ready_list, acb, chain); 980 break; 981 case ACB_QNEXUS: 982 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 983 ti->lubusy &= ~(1<<periph->periph_lun); 984 break; 985 case ACB_QFREE: 986 panic("%s: dequeue: busy acb on free list", 987 sc->sc_dev.dv_xname); 988 break; 989 default: 990 panic("%s: dequeue: unknown queue %d", 991 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 992 } 993 994 /* Put it on the free list, and clear flags. */ 995 #if 0 996 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 997 acb->flags = ACB_QFREE; 998 #else 999 mha_free_acb(sc, acb, xs->xs_control); 1000 #endif 1001 1002 ti->cmds++; 1003 scsipi_done(xs); 1004 } 1005 1006 void 1007 mha_dequeue(sc, acb) 1008 struct mha_softc *sc; 1009 struct acb *acb; 1010 { 1011 1012 if (acb->flags & ACB_QNEXUS) { 1013 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1014 } else { 1015 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1016 } 1017 } 1018 1019 /* 1020 * INTERRUPT/PROTOCOL ENGINE 1021 */ 1022 1023 /* 1024 * Schedule an outgoing message by prioritizing it, and asserting 1025 * attention on the bus. We can only do this when we are the initiator 1026 * else there will be an illegal command interrupt. 1027 */ 1028 #define mha_sched_msgout(m) \ 1029 do { \ 1030 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1031 CMR = CMD_SET_ATN; \ 1032 sc->sc_msgpriq |= (m); \ 1033 } while (0) 1034 1035 /* 1036 * Precondition: 1037 * The SCSI bus is already in the MSGI phase and there is a message byte 1038 * on the bus, along with an asserted REQ signal. 1039 */ 1040 void 1041 mha_msgin(sc) 1042 register struct mha_softc *sc; 1043 { 1044 register int v; 1045 1046 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1047 1048 /* 1049 * Prepare for a new message. A message should (according 1050 * to the SCSI standard) be transmitted in one single 1051 * MESSAGE_IN_PHASE. If we have been in some other phase, 1052 * then this is a new message. 1053 */ 1054 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1055 sc->sc_flags &= ~SPC_DROP_MSGI; 1056 sc->sc_imlen = 0; 1057 } 1058 1059 WAIT; 1060 1061 v = MBR; /* modified byte */ 1062 v = sc->sc_pcx[0]; 1063 1064 sc->sc_imess[sc->sc_imlen] = v; 1065 1066 /* 1067 * If we're going to reject the message, don't bother storing 1068 * the incoming bytes. But still, we need to ACK them. 1069 */ 1070 1071 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1072 CMR = CMD_SET_ATN; 1073 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1074 printf("<dropping msg byte %x>", 1075 sc->sc_imess[sc->sc_imlen]); 1076 return; 1077 } 1078 1079 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1080 mha_sched_msgout(SEND_REJECT); 1081 sc->sc_flags |= SPC_DROP_MSGI; 1082 } else { 1083 sc->sc_imlen++; 1084 /* 1085 * This testing is suboptimal, but most 1086 * messages will be of the one byte variety, so 1087 * it should not effect performance 1088 * significantly. 1089 */ 1090 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1091 goto gotit; 1092 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1093 goto gotit; 1094 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1095 sc->sc_imlen == sc->sc_imess[1] + 2) 1096 goto gotit; 1097 } 1098 #if 0 1099 /* Ack what we have so far */ 1100 ESPCMD(sc, ESPCMD_MSGOK); 1101 #endif 1102 return; 1103 1104 gotit: 1105 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1106 /* 1107 * Now we should have a complete message (1 byte, 2 byte 1108 * and moderately long extended messages). We only handle 1109 * extended messages which total length is shorter than 1110 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1111 */ 1112 if (sc->sc_state == SPC_HASNEXUS) { 1113 struct acb *acb = sc->sc_nexus; 1114 struct spc_tinfo *ti = 1115 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1116 1117 switch (sc->sc_imess[0]) { 1118 case MSG_CMDCOMPLETE: 1119 SPC_MSGS(("cmdcomplete ")); 1120 if (sc->sc_dleft < 0) { 1121 struct scsipi_periph *periph = acb->xs->xs_periph; 1122 printf("mha: %d extra bytes from %d:%d\n", 1123 -sc->sc_dleft, 1124 periph->periph_target, 1125 periph->periph_lun); 1126 sc->sc_dleft = 0; 1127 } 1128 acb->xs->resid = acb->dleft = sc->sc_dleft; 1129 sc->sc_flags |= SPC_BUSFREE_OK; 1130 break; 1131 1132 case MSG_MESSAGE_REJECT: 1133 #if SPC_DEBUG 1134 if (mha_debug & SPC_SHOWMSGS) 1135 printf("%s: our msg rejected by target\n", 1136 sc->sc_dev.dv_xname); 1137 #endif 1138 #if 1 /* XXX - must remember last message */ 1139 scsipi_printaddr(acb->xs->xs_periph); 1140 printf("MSG_MESSAGE_REJECT>>"); 1141 #endif 1142 if (sc->sc_flags & SPC_SYNCHNEGO) { 1143 ti->period = ti->offset = 0; 1144 sc->sc_flags &= ~SPC_SYNCHNEGO; 1145 ti->flags &= ~T_NEGOTIATE; 1146 } 1147 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1148 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1149 mha_sched_msgout(SEND_ABORT); 1150 break; 1151 case MSG_NOOP: 1152 SPC_MSGS(("noop ")); 1153 break; 1154 case MSG_DISCONNECT: 1155 SPC_MSGS(("disconnect ")); 1156 ti->dconns++; 1157 sc->sc_flags |= SPC_DISCON; 1158 sc->sc_flags |= SPC_BUSFREE_OK; 1159 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1160 break; 1161 /*FALLTHROUGH*/ 1162 case MSG_SAVEDATAPOINTER: 1163 SPC_MSGS(("save datapointer ")); 1164 acb->dleft = sc->sc_dleft; 1165 acb->daddr = sc->sc_dp; 1166 break; 1167 case MSG_RESTOREPOINTERS: 1168 SPC_MSGS(("restore datapointer ")); 1169 if (!acb) { 1170 mha_sched_msgout(SEND_ABORT); 1171 printf("%s: no DATAPOINTERs to restore\n", 1172 sc->sc_dev.dv_xname); 1173 break; 1174 } 1175 sc->sc_dp = acb->daddr; 1176 sc->sc_dleft = acb->dleft; 1177 break; 1178 case MSG_PARITY_ERROR: 1179 printf("%s:target%d: MSG_PARITY_ERROR\n", 1180 sc->sc_dev.dv_xname, 1181 acb->xs->xs_periph->periph_target); 1182 break; 1183 case MSG_EXTENDED: 1184 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1185 switch (sc->sc_imess[2]) { 1186 case MSG_EXT_SDTR: 1187 SPC_MSGS(("SDTR period %d, offset %d ", 1188 sc->sc_imess[3], sc->sc_imess[4])); 1189 ti->period = sc->sc_imess[3]; 1190 ti->offset = sc->sc_imess[4]; 1191 if (sc->sc_minsync == 0) { 1192 /* We won't do synch */ 1193 ti->offset = 0; 1194 mha_sched_msgout(SEND_SDTR); 1195 } else if (ti->offset == 0) { 1196 printf("%s:%d: async\n", "mha", 1197 acb->xs->xs_periph->periph_target); 1198 ti->offset = 0; 1199 sc->sc_flags &= ~SPC_SYNCHNEGO; 1200 } else if (ti->period > 124) { 1201 printf("%s:%d: async\n", "mha", 1202 acb->xs->xs_periph->periph_target); 1203 ti->offset = 0; 1204 mha_sched_msgout(SEND_SDTR); 1205 } else { 1206 #if 0 1207 int p; 1208 p = mha_stp2cpb(sc, ti->period); 1209 ti->period = mha_cpb2stp(sc, p); 1210 #endif 1211 1212 #if SPC_DEBUG 1213 scsipi_printaddr(acb->xs->xs_periph); 1214 #endif 1215 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1216 /* Target initiated negotiation */ 1217 if (ti->flags & T_SYNCMODE) { 1218 ti->flags &= ~T_SYNCMODE; 1219 #if SPC_DEBUG 1220 printf("renegotiated "); 1221 #endif 1222 } 1223 TMR=TM_ASYNC; 1224 /* Clamp to our maxima */ 1225 if (ti->period < sc->sc_minsync) 1226 ti->period = sc->sc_minsync; 1227 if (ti->offset > 15) 1228 ti->offset = 15; 1229 mha_sched_msgout(SEND_SDTR); 1230 } else { 1231 /* we are sync */ 1232 sc->sc_flags &= ~SPC_SYNCHNEGO; 1233 TMR = TM_SYNC; 1234 ti->flags |= T_SYNCMODE; 1235 } 1236 } 1237 ti->flags &= ~T_NEGOTIATE; 1238 break; 1239 default: /* Extended messages we don't handle */ 1240 CMR = CMD_SET_ATN; /* XXX? */ 1241 break; 1242 } 1243 break; 1244 default: 1245 SPC_MSGS(("ident ")); 1246 /* thanks for that ident... */ 1247 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1248 SPC_MISC(("unknown ")); 1249 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1250 CMR = CMD_SET_ATN; /* XXX? */ 1251 } 1252 break; 1253 } 1254 } else if (sc->sc_state == SPC_RESELECTED) { 1255 struct scsipi_periph *periph = NULL; 1256 struct acb *acb; 1257 struct spc_tinfo *ti; 1258 u_char lunit; 1259 1260 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1261 SPC_MISC(("searching ")); 1262 /* 1263 * Search wait queue for disconnected cmd 1264 * The list should be short, so I haven't bothered with 1265 * any more sophisticated structures than a simple 1266 * singly linked list. 1267 */ 1268 lunit = sc->sc_imess[0] & 0x07; 1269 for (acb = sc->nexus_list.tqh_first; acb; 1270 acb = acb->chain.tqe_next) { 1271 periph = acb->xs->xs_periph; 1272 if (periph->periph_lun == lunit && 1273 sc->sc_selid == (1<<periph->periph_target)) { 1274 TAILQ_REMOVE(&sc->nexus_list, acb, 1275 chain); 1276 ACB_SETQ(acb, ACB_QNONE); 1277 break; 1278 } 1279 } 1280 1281 if (!acb) { /* Invalid reselection! */ 1282 mha_sched_msgout(SEND_ABORT); 1283 printf("mha: invalid reselect (idbit=0x%2x)\n", 1284 sc->sc_selid); 1285 } else { /* Reestablish nexus */ 1286 /* 1287 * Setup driver data structures and 1288 * do an implicit RESTORE POINTERS 1289 */ 1290 ti = &sc->sc_tinfo[periph->periph_target]; 1291 sc->sc_nexus = acb; 1292 sc->sc_dp = acb->daddr; 1293 sc->sc_dleft = acb->dleft; 1294 sc->sc_tinfo[periph->periph_target].lubusy 1295 |= (1<<periph->periph_lun); 1296 if (ti->flags & T_SYNCMODE) { 1297 TMR = TM_SYNC; /* XXX */ 1298 } else { 1299 TMR = TM_ASYNC; 1300 } 1301 SPC_MISC(("... found acb")); 1302 sc->sc_state = SPC_HASNEXUS; 1303 } 1304 } else { 1305 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1306 sc->sc_dev.dv_xname, sc->sc_selid); 1307 mha_sched_msgout(SEND_DEV_RESET); 1308 } 1309 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1310 printf("%s: unexpected message in; will send DEV_RESET\n", 1311 sc->sc_dev.dv_xname); 1312 mha_sched_msgout(SEND_DEV_RESET); 1313 } 1314 1315 /* Ack last message byte */ 1316 #if 0 1317 ESPCMD(sc, ESPCMD_MSGOK); 1318 #endif 1319 1320 /* Done, reset message pointer. */ 1321 sc->sc_flags &= ~SPC_DROP_MSGI; 1322 sc->sc_imlen = 0; 1323 } 1324 1325 /* 1326 * Send the highest priority, scheduled message. 1327 */ 1328 void 1329 mha_msgout(sc) 1330 register struct mha_softc *sc; 1331 { 1332 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE) 1333 struct spc_tinfo *ti; 1334 #endif 1335 int n; 1336 1337 SPC_TRACE(("mha_msgout ")); 1338 1339 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1340 if (sc->sc_omp == sc->sc_omess) { 1341 /* 1342 * This is a retransmission. 1343 * 1344 * We get here if the target stayed in MESSAGE OUT 1345 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1346 * that all of the previously transmitted messages must 1347 * be sent again, in the same order. Therefore, we 1348 * requeue all the previously transmitted messages, and 1349 * start again from the top. Our simple priority 1350 * scheme keeps the messages in the right order. 1351 */ 1352 SPC_MISC(("retransmitting ")); 1353 sc->sc_msgpriq |= sc->sc_msgoutq; 1354 /* 1355 * Set ATN. If we're just sending a trivial 1-byte 1356 * message, we'll clear ATN later on anyway. 1357 */ 1358 CMR = CMD_SET_ATN; /* XXX? */ 1359 } else { 1360 /* This is a continuation of the previous message. */ 1361 n = sc->sc_omp - sc->sc_omess; 1362 goto nextbyte; 1363 } 1364 } 1365 1366 /* No messages transmitted so far. */ 1367 sc->sc_msgoutq = 0; 1368 sc->sc_lastmsg = 0; 1369 1370 nextmsg: 1371 /* Pick up highest priority message. */ 1372 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1373 sc->sc_msgpriq &= ~sc->sc_currmsg; 1374 sc->sc_msgoutq |= sc->sc_currmsg; 1375 1376 /* Build the outgoing message data. */ 1377 switch (sc->sc_currmsg) { 1378 case SEND_IDENTIFY: 1379 SPC_ASSERT(sc->sc_nexus != NULL); 1380 sc->sc_omess[0] = 1381 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1382 n = 1; 1383 break; 1384 1385 #if SPC_USE_SYNCHRONOUS 1386 case SEND_SDTR: 1387 SPC_ASSERT(sc->sc_nexus != NULL); 1388 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1389 sc->sc_omess[4] = MSG_EXTENDED; 1390 sc->sc_omess[3] = 3; 1391 sc->sc_omess[2] = MSG_EXT_SDTR; 1392 sc->sc_omess[1] = ti->period >> 2; 1393 sc->sc_omess[0] = ti->offset; 1394 n = 5; 1395 break; 1396 #endif 1397 1398 #if SPC_USE_WIDE 1399 case SEND_WDTR: 1400 SPC_ASSERT(sc->sc_nexus != NULL); 1401 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1402 sc->sc_omess[3] = MSG_EXTENDED; 1403 sc->sc_omess[2] = 2; 1404 sc->sc_omess[1] = MSG_EXT_WDTR; 1405 sc->sc_omess[0] = ti->width; 1406 n = 4; 1407 break; 1408 #endif 1409 1410 case SEND_DEV_RESET: 1411 sc->sc_flags |= SPC_ABORTING; 1412 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1413 n = 1; 1414 break; 1415 1416 case SEND_REJECT: 1417 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1418 n = 1; 1419 break; 1420 1421 case SEND_PARITY_ERROR: 1422 sc->sc_omess[0] = MSG_PARITY_ERROR; 1423 n = 1; 1424 break; 1425 1426 case SEND_INIT_DET_ERR: 1427 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1428 n = 1; 1429 break; 1430 1431 case SEND_ABORT: 1432 sc->sc_flags |= SPC_ABORTING; 1433 sc->sc_omess[0] = MSG_ABORT; 1434 n = 1; 1435 break; 1436 1437 default: 1438 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1439 sc->sc_dev.dv_xname); 1440 SPC_BREAK(); 1441 sc->sc_omess[0] = MSG_NOOP; 1442 n = 1; 1443 break; 1444 } 1445 sc->sc_omp = &sc->sc_omess[n]; 1446 1447 nextbyte: 1448 /* Send message bytes. */ 1449 /* send TRANSFER command. */ 1450 sc->sc_ps[3] = 1; 1451 sc->sc_ps[4] = n >> 8; 1452 sc->sc_pc[10] = n; 1453 sc->sc_ps[-1] = 0x000F; /* burst */ 1454 asm volatile ("nop"); 1455 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1456 for (;;) { 1457 if ((SSR & SS_BUSY) != 0) 1458 break; 1459 if (SSR & SS_IREQUEST) 1460 goto out; 1461 } 1462 for (;;) { 1463 #if 0 1464 for (;;) { 1465 if ((PSNS & PSNS_REQ) != 0) 1466 break; 1467 /* Wait for REQINIT. XXX Need timeout. */ 1468 } 1469 #endif 1470 if (SSR & SS_IREQUEST) { 1471 /* 1472 * Target left MESSAGE OUT, possibly to reject 1473 * our message. 1474 * 1475 * If this is the last message being sent, then we 1476 * deassert ATN, since either the target is going to 1477 * ignore this message, or it's going to ask for a 1478 * retransmission via MESSAGE PARITY ERROR (in which 1479 * case we reassert ATN anyway). 1480 */ 1481 #if 0 1482 if (sc->sc_msgpriq == 0) 1483 CMR = CMD_RESET_ATN; 1484 #endif 1485 goto out; 1486 } 1487 1488 #if 0 1489 /* Clear ATN before last byte if this is the last message. */ 1490 if (n == 1 && sc->sc_msgpriq == 0) 1491 CMR = CMD_RESET_ATN; 1492 #endif 1493 1494 while ((SSR & SS_DREG_FULL) != 0) 1495 ; 1496 /* Send message byte. */ 1497 sc->sc_pc[0] = *--sc->sc_omp; 1498 --n; 1499 /* Keep track of the last message we've sent any bytes of. */ 1500 sc->sc_lastmsg = sc->sc_currmsg; 1501 1502 if (n == 0) 1503 break; 1504 } 1505 1506 /* We get here only if the entire message has been transmitted. */ 1507 if (sc->sc_msgpriq != 0) { 1508 /* There are more outgoing messages. */ 1509 goto nextmsg; 1510 } 1511 1512 /* 1513 * The last message has been transmitted. We need to remember the last 1514 * message transmitted (in case the target switches to MESSAGE IN phase 1515 * and sends a MESSAGE REJECT), and the list of messages transmitted 1516 * this time around (in case the target stays in MESSAGE OUT phase to 1517 * request a retransmit). 1518 */ 1519 1520 out: 1521 /* Disable REQ/ACK protocol. */ 1522 return; 1523 } 1524 1525 1526 /*************************************************************** 1527 * 1528 * datain/dataout 1529 * 1530 */ 1531 1532 int 1533 mha_datain_pio(sc, p, n) 1534 register struct mha_softc *sc; 1535 u_char *p; 1536 int n; 1537 { 1538 u_short d; 1539 int a; 1540 int total_n = n; 1541 1542 SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n)); 1543 1544 WAIT; 1545 sc->sc_ps[3] = 1; 1546 sc->sc_ps[4] = n >> 8; 1547 sc->sc_pc[10] = n; 1548 /* $BHa$7$-%=%U%HE>Aw(B */ 1549 CMR = CMD_RECEIVE_TO_MPU; 1550 for (;;) { 1551 a = SSR; 1552 if (a & 0x04) { 1553 d = sc->sc_ps[0]; 1554 *p++ = d >> 8; 1555 if (--n > 0) { 1556 *p++ = d; 1557 --n; 1558 } 1559 a = SSR; 1560 } 1561 if (a & 0x40) 1562 continue; 1563 if (a & 0x80) 1564 break; 1565 } 1566 SPC_TRACE(("...%d resd]", n)); 1567 return total_n - n; 1568 } 1569 1570 int 1571 mha_dataout_pio(sc, p, n) 1572 register struct mha_softc *sc; 1573 u_char *p; 1574 int n; 1575 { 1576 u_short d; 1577 int a; 1578 int total_n = n; 1579 1580 SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n)); 1581 1582 WAIT; 1583 sc->sc_ps[3] = 1; 1584 sc->sc_ps[4] = n >> 8; 1585 sc->sc_pc[10] = n; 1586 /* $BHa$7$-%=%U%HE>Aw(B */ 1587 CMR = CMD_SEND_FROM_MPU; 1588 for (;;) { 1589 a = SSR; 1590 if (a & 0x04) { 1591 d = *p++ << 8; 1592 if (--n > 0) { 1593 d |= *p++; 1594 --n; 1595 } 1596 sc->sc_ps[0] = d; 1597 a = SSR; 1598 } 1599 if (a & 0x40) 1600 continue; 1601 if (a & 0x80) 1602 break; 1603 } 1604 SPC_TRACE(("...%d resd]", n)); 1605 return total_n - n; 1606 } 1607 1608 static int 1609 mha_dataio_dma(dw, cw, sc, p, n) 1610 int dw; /* DMA word */ 1611 int cw; /* CMR word */ 1612 register struct mha_softc *sc; 1613 u_char *p; 1614 int n; 1615 { 1616 char *paddr; 1617 1618 if (n > MAXBSIZE) 1619 panic("transfer size exceeds MAXBSIZE"); 1620 if (sc->sc_dmasize > 0) 1621 panic("DMA request while another DMA transfer is in pregress"); 1622 1623 if (cw == CMD_SEND_FROM_DMA) { 1624 memcpy(sc->sc_dmabuf, p, n); 1625 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1626 } else { 1627 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1628 } 1629 sc->sc_p = p; 1630 sc->sc_dmasize = n; 1631 1632 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1633 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1634 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1635 dw &= ~(1 << 3); 1636 #endif 1637 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1638 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1639 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1640 WAIT; 1641 sc->sc_ps[3] = 1; 1642 sc->sc_ps[4] = n >> 8; 1643 sc->sc_pc[10] = n; 1644 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1645 3 ... short bus cycle 1646 2 ... MAXIMUM XFER. 1647 1 ... BURST XFER. 1648 0 ... R/W */ 1649 sc->sc_ps[-1] = dw; /* burst */ 1650 asm volatile ("nop"); 1651 CMR = cw; /* receive to DMA */ 1652 return n; 1653 } 1654 int 1655 mha_dataout(sc, p, n) 1656 register struct mha_softc *sc; 1657 u_char *p; 1658 int n; 1659 { 1660 if (n == 0) 1661 return n; 1662 1663 if (n & 1) 1664 return mha_dataout_pio(sc, p, n); 1665 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1666 } 1667 1668 int 1669 mha_datain(sc, p, n) 1670 register struct mha_softc *sc; 1671 u_char *p; 1672 int n; 1673 { 1674 register struct acb *acb = sc->sc_nexus; 1675 1676 if (n == 0) 1677 return n; 1678 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1679 return mha_datain_pio(sc, p, n); 1680 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1681 } 1682 1683 1684 /* 1685 * Catch an interrupt from the adaptor 1686 */ 1687 /* 1688 * This is the workhorse routine of the driver. 1689 * Deficiencies (for now): 1690 * 1) always uses programmed I/O 1691 */ 1692 int 1693 mhaintr(arg) 1694 void *arg; 1695 { 1696 struct mha_softc *sc = arg; 1697 #if 0 1698 u_char ints; 1699 #endif 1700 struct acb *acb; 1701 u_char ph; 1702 u_short r; 1703 int n; 1704 1705 #if 1 /* XXX called during attach? */ 1706 if (tmpsc != NULL) { 1707 SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc)); 1708 sc = tmpsc; 1709 } else { 1710 #endif 1711 1712 #if 1 /* XXX */ 1713 } 1714 #endif 1715 1716 #if 0 1717 /* 1718 * $B3d$j9~$_6X;_$K$9$k(B 1719 */ 1720 SCTL &= ~SCTL_INTR_ENAB; 1721 #endif 1722 1723 SPC_TRACE(("[mhaintr]")); 1724 1725 /* 1726 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1727 */ 1728 /* 1729 * First check for abnormal conditions, such as reset. 1730 */ 1731 #if 0 1732 #if 1 /* XXX? */ 1733 while (((ints = SSR) & SS_IREQUEST) == 0) 1734 delay(1); 1735 SPC_MISC(("ints = 0x%x ", ints)); 1736 #else /* usually? */ 1737 ints = SSR; 1738 #endif 1739 #endif 1740 while (SSR & SS_IREQUEST) { 1741 acb = sc->sc_nexus; 1742 r = ISCSR; 1743 SPC_MISC(("[r=0x%x]", r)); 1744 switch (r >> 8) { 1745 default: 1746 printf("[addr=%p\n" 1747 "result=0x%x\n" 1748 "cmd=0x%x\n" 1749 "ph=0x%x(ought to be %d)]\n", 1750 &ISCSR, 1751 r, 1752 acb->xs->cmd->opcode, 1753 SCR, sc->sc_phase); 1754 panic("unexpected result."); 1755 case 0x82: /* selection timeout */ 1756 SPC_MISC(("selection timeout ")); 1757 sc->sc_phase = BUSFREE_PHASE; 1758 SPC_ASSERT(sc->sc_nexus != NULL); 1759 acb = sc->sc_nexus; 1760 delay(250); 1761 acb->xs->error = XS_SELTIMEOUT; 1762 mha_done(sc, acb); 1763 continue; /* XXX ??? msaitoh */ 1764 case 0x60: /* command completed */ 1765 sc->sc_spcinitialized++; 1766 if (sc->sc_phase == BUSFREE_PHASE) 1767 continue; 1768 ph = SCR; 1769 if (ph & PSNS_ACK) { 1770 int s; 1771 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1772 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1773 ph & PHASE_MASK, sc->sc_phase)); 1774 #if 0 1775 /* switch (sc->sc_phase) {*/ 1776 #else 1777 switch (ph & PHASE_MASK) { 1778 #endif 1779 case STATUS_PHASE: 1780 if (sc->sc_state != SPC_HASNEXUS) 1781 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1782 sc->sc_state); 1783 SPC_ASSERT(sc->sc_nexus != NULL); 1784 acb = sc->sc_nexus; 1785 WAIT; 1786 s = MBR; 1787 SPC_ASSERT(s == 1); 1788 acb->stat = sc->sc_pcx[0]; /* XXX */ 1789 SPC_MISC(("stat=0x%02x ", acb->stat)); 1790 sc->sc_prevphase = STATUS_PHASE; 1791 break; 1792 case MESSAGE_IN_PHASE: 1793 mha_msgin(sc); 1794 sc->sc_prevphase = MESSAGE_IN_PHASE; 1795 /* thru */ 1796 case DATA_IN_PHASE: 1797 if (sc->sc_dmasize == 0) 1798 break; 1799 bus_dmamap_sync(sc->sc_dmat, 1800 sc->sc_dmamap, 1801 0, sc->sc_dmasize, 1802 BUS_DMASYNC_POSTREAD); 1803 memcpy(sc->sc_p, sc->sc_dmabuf, 1804 sc->sc_dmasize); 1805 sc->sc_dmasize = 0; 1806 break; 1807 case DATA_OUT_PHASE: 1808 if (sc->sc_dmasize == 0) 1809 break; 1810 bus_dmamap_sync(sc->sc_dmat, 1811 sc->sc_dmamap, 1812 0, sc->sc_dmasize, 1813 BUS_DMASYNC_POSTWRITE); 1814 sc->sc_dmasize = 0; 1815 break; 1816 } 1817 WAIT; 1818 CMR = CMD_RESET_ACK; /* reset ack */ 1819 /*mha_done(sc, acb); XXX */ 1820 continue; 1821 } else if (NSR & 0x80) { /* nexus */ 1822 #if 1 1823 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1824 sc->sc_state = SPC_HASNEXUS; 1825 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1826 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1827 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1828 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1829 WAIT; 1830 if (SSR & SS_IREQUEST) 1831 continue; 1832 switch (sc->sc_phase) { 1833 default: 1834 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1835 case MESSAGE_IN_PHASE: 1836 /* $B2?$b$7$J$$(B */ 1837 continue; 1838 case STATUS_PHASE: 1839 sc->sc_phase = MESSAGE_IN_PHASE; 1840 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1841 continue; 1842 case DATA_IN_PHASE: 1843 sc->sc_prevphase = DATA_IN_PHASE; 1844 if (sc->sc_dleft == 0) { 1845 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1846 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1847 sc->sc_phase = STATUS_PHASE; 1848 CMR = CMD_RECEIVE_STS; /* receive sts */ 1849 continue; 1850 } 1851 n = mha_datain(sc, sc->sc_dp, 1852 sc->sc_dleft); 1853 sc->sc_dp += n; 1854 sc->sc_dleft -= n; 1855 continue; 1856 case DATA_OUT_PHASE: 1857 sc->sc_prevphase = DATA_OUT_PHASE; 1858 if (sc->sc_dleft == 0) { 1859 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1860 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1861 sc->sc_phase = STATUS_PHASE; 1862 CMR = CMD_RECEIVE_STS; /* receive sts */ 1863 continue; 1864 } 1865 /* data phase $B$NB3$-$r$d$m$&(B */ 1866 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1867 sc->sc_dp += n; 1868 sc->sc_dleft -= n; 1869 continue; 1870 case COMMAND_PHASE: 1871 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1872 if (acb->dleft) { 1873 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1874 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1875 sc->sc_phase = DATA_IN_PHASE; 1876 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1877 sc->sc_dp += n; 1878 sc->sc_dleft -= n; 1879 } 1880 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1881 sc->sc_phase = DATA_OUT_PHASE; 1882 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1883 sc->sc_dp += n; 1884 sc->sc_dleft -= n; 1885 } 1886 continue; 1887 } 1888 else { 1889 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1890 WAIT; 1891 sc->sc_phase = STATUS_PHASE; 1892 CMR = CMD_RECEIVE_STS; /* receive sts */ 1893 continue; 1894 } 1895 } 1896 #endif 1897 } 1898 continue; 1899 case 0x31: /* disconnected in xfer progress. */ 1900 SPC_MISC(("[0x31]")); 1901 case 0x70: /* disconnected. */ 1902 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1903 sc->sc_phase = BUSFREE_PHASE; 1904 sc->sc_state = SPC_IDLE; 1905 #if 1 1906 acb = sc->sc_nexus; 1907 SPC_ASSERT(sc->sc_nexus != NULL); 1908 acb->xs->error = XS_NOERROR; 1909 mha_done(sc, acb); 1910 #else 1911 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1912 mha_sched(sc); 1913 #endif 1914 continue; 1915 case 0x32: /* phase error in xfer progress. */ 1916 SPC_MISC(("[0x32]")); 1917 #if 0 1918 case 0x65: /* invalid command. 1919 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1920 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1921 #if 1 1922 SPC_MISC(("[0x%04x]", r)); 1923 #endif 1924 #endif 1925 case 0x54: /* initial-phase error. */ 1926 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1927 NSR, 1928 SCR, sc->sc_phase)); 1929 /* thru */ 1930 case 0x71: /* assert req */ 1931 WAIT; 1932 if (SSR & 0x40) { 1933 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1934 SSR, r, NSR, SCR); 1935 WAIT; 1936 } 1937 ph = SCR; 1938 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1939 sc->sc_state = SPC_HASNEXUS; 1940 } 1941 if (ph & 0x80) { 1942 switch (ph & PHASE_MASK) { 1943 default: 1944 printf("phase = %x\n", ph); 1945 panic("assert req: the phase I don't know!"); 1946 case DATA_IN_PHASE: 1947 sc->sc_prevphase = DATA_IN_PHASE; 1948 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1949 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1950 sc->sc_dp += n; 1951 sc->sc_dleft -= n; 1952 SPC_MISC(("done\n")); 1953 continue; 1954 case DATA_OUT_PHASE: 1955 sc->sc_prevphase = DATA_OUT_PHASE; 1956 SPC_MISC(("DATAOUT\n")); 1957 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1958 sc->sc_dp += n; 1959 sc->sc_dleft -= n; 1960 continue; 1961 case STATUS_PHASE: 1962 sc->sc_phase = STATUS_PHASE; 1963 SPC_MISC(("[RECV_STS]")); 1964 WAIT; 1965 CMR = CMD_RECEIVE_STS; /* receive sts */ 1966 continue; 1967 case MESSAGE_IN_PHASE: 1968 sc->sc_phase = MESSAGE_IN_PHASE; 1969 WAIT; 1970 CMR = CMD_RECEIVE_MSG; 1971 continue; 1972 } 1973 } 1974 continue; 1975 } 1976 } 1977 1978 return 1; 1979 } 1980 1981 void 1982 mha_abort(sc, acb) 1983 struct mha_softc *sc; 1984 struct acb *acb; 1985 { 1986 acb->flags |= ACB_ABORTED; 1987 1988 if (acb == sc->sc_nexus) { 1989 /* 1990 * If we're still selecting, the message will be scheduled 1991 * after selection is complete. 1992 */ 1993 if (sc->sc_state == SPC_HASNEXUS) { 1994 sc->sc_flags |= SPC_ABORTING; 1995 mha_sched_msgout(SEND_ABORT); 1996 } 1997 } else { 1998 if (sc->sc_state == SPC_IDLE) 1999 mha_sched(sc); 2000 } 2001 } 2002 2003 void 2004 mha_timeout(arg) 2005 void *arg; 2006 { 2007 int s = splbio(); 2008 struct acb *acb = (struct acb *)arg; 2009 struct scsipi_xfer *xs = acb->xs; 2010 struct scsipi_periph *periph = xs->xs_periph; 2011 struct mha_softc *sc = 2012 (void*)periph->periph_channel->chan_adapter->adapt_dev; 2013 2014 scsipi_printaddr(periph); 2015 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2016 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2017 sc->sc_dev.dv_xname, 2018 acb, acb->flags, acb->dleft, acb->stat, 2019 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2020 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2021 ); 2022 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2023 panic("timeout, ouch!"); 2024 2025 if (acb->flags & ACB_ABORTED) { 2026 /* abort timed out */ 2027 printf(" AGAIN\n"); 2028 #if 0 2029 mha_init(sc, 1); /* XXX 1?*/ 2030 #endif 2031 } else { 2032 /* abort the operation that has timed out */ 2033 printf("\n"); 2034 xs->error = XS_TIMEOUT; 2035 mha_abort(sc, acb); 2036 } 2037 2038 splx(s); 2039 } 2040 2041 #if SPC_DEBUG 2042 /* 2043 * The following functions are mostly used for debugging purposes, either 2044 * directly called from the driver or from the kernel debugger. 2045 */ 2046 2047 void 2048 mha_show_scsi_cmd(acb) 2049 struct acb *acb; 2050 { 2051 u_char *b = (u_char *)&acb->cmd; 2052 struct scsipi_periph *periph = acb->xs->xs_periph; 2053 int i; 2054 2055 scsipi_printaddr(periph); 2056 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2057 for (i = 0; i < acb->clen; i++) { 2058 if (i) 2059 printf(","); 2060 printf("%x", b[i]); 2061 } 2062 printf("\n"); 2063 } else 2064 printf("RESET\n"); 2065 } 2066 2067 void 2068 mha_print_acb(acb) 2069 struct acb *acb; 2070 { 2071 2072 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2073 printf(" dp=%p dleft=%d stat=%x\n", 2074 acb->daddr, acb->dleft, acb->stat); 2075 mha_show_scsi_cmd(acb); 2076 } 2077 2078 void 2079 mha_print_active_acb() 2080 { 2081 struct acb *acb; 2082 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2083 2084 printf("ready list:\n"); 2085 for (acb = sc->ready_list.tqh_first; acb != NULL; 2086 acb = acb->chain.tqe_next) 2087 mha_print_acb(acb); 2088 printf("nexus:\n"); 2089 if (sc->sc_nexus != NULL) 2090 mha_print_acb(sc->sc_nexus); 2091 printf("nexus list:\n"); 2092 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2093 acb = acb->chain.tqe_next) 2094 mha_print_acb(acb); 2095 } 2096 2097 void 2098 mha_dump_driver(sc) 2099 struct mha_softc *sc; 2100 { 2101 struct spc_tinfo *ti; 2102 int i; 2103 2104 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2105 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2106 sc->sc_state, sc->sc_imess[0], 2107 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2108 for (i = 0; i < 7; i++) { 2109 ti = &sc->sc_tinfo[i]; 2110 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2111 i, ti->cmds, ti->dconns, ti->touts); 2112 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2113 } 2114 } 2115 #endif 2116