1 /* $NetBSD: mha.c,v 1.48 2008/06/13 13:57:58 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1994 Jarle Greipsland 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 50 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 51 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 52 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 53 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 56 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 57 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: mha.c,v 1.48 2008/06/13 13:57:58 cegger Exp $"); 63 64 #include "opt_ddb.h" 65 66 /* Synchronous data transfers? */ 67 #define SPC_USE_SYNCHRONOUS 0 68 #define SPC_SYNC_REQ_ACK_OFS 8 69 70 /* Default DMA mode? */ 71 #define MHA_DMA_LIMIT_XFER 1 72 #define MHA_DMA_BURST_XFER 1 73 #define MHA_DMA_SHORT_BUS_CYCLE 1 74 75 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 76 | (MHA_DMA_BURST_XFER << 2) \ 77 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 78 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 79 | (MHA_DMA_BURST_XFER << 2) \ 80 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 81 82 /* Include debug functions? At the end of this file there are a bunch of 83 * functions that will print out various information regarding queued SCSI 84 * commands, driver state and chip contents. You can call them from the 85 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 86 * kernel uses less memory) but you lose the debugging facilities. 87 */ 88 #define SPC_DEBUG 0 89 90 /* End of customizable parameters */ 91 92 /* 93 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 94 */ 95 96 #include <sys/types.h> 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/kernel.h> 100 #include <sys/errno.h> 101 #include <sys/ioctl.h> 102 #include <sys/device.h> 103 #include <sys/buf.h> 104 #include <sys/proc.h> 105 #include <sys/user.h> 106 #include <sys/queue.h> 107 108 #include <machine/bus.h> 109 110 #include <dev/scsipi/scsi_spc.h> 111 #include <dev/scsipi/scsi_all.h> 112 #include <dev/scsipi/scsipi_all.h> 113 #include <dev/scsipi/scsi_message.h> 114 #include <dev/scsipi/scsiconf.h> 115 116 #include <x68k/x68k/iodevice.h> 117 #include <x68k/dev/mb86601reg.h> 118 #include <x68k/dev/mhavar.h> 119 #include <x68k/dev/intiovar.h> 120 #include <x68k/dev/scsiromvar.h> 121 122 #if 0 123 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 124 #else 125 #define WAIT {while (sc->sc_pc[2] & 0x40);} 126 #endif 127 128 #define SSR (sc->sc_pc[2]) 129 #define SS_IREQUEST 0x80 130 #define SS_BUSY 0x40 131 #define SS_DREG_FULL 0x02 132 133 #define NSR (sc->sc_pc[3]) 134 135 #define SIR (sc->sc_pc[4]) 136 137 #define CMR (sc->sc_pc[5]) 138 #define CMD_SEL_AND_CMD 0x00 139 #define CMD_SELECT 0x09 140 #define CMD_SET_ATN 0x0a 141 #define CMD_RESET_ATN 0x0b 142 #define CMD_RESET_ACK 0x0d 143 #define CMD_SEND_FROM_MPU 0x10 144 #define CMD_SEND_FROM_DMA 0x11 145 #define CMD_RECEIVE_TO_MPU 0x12 146 #define CMD_RECEIVE_TO_DMA 0x13 147 #define CMD_RECEIVE_MSG 0x1a 148 #define CMD_RECEIVE_STS 0x1c 149 #define CMD_SOFT_RESET 0x40 150 #define CMD_SCSI_RESET 0x42 151 #define CMD_SET_UP_REG 0x43 152 153 #define SCR (sc->sc_pc[11]) 154 155 #define TMR (sc->sc_pc[12]) 156 #define TM_SYNC 0x80 157 #define TM_ASYNC 0x00 158 159 #define WAR (sc->sc_pc[15]) 160 #define WA_MCSBUFWIN 0x00 161 #define WA_UPMWIN 0x80 162 #define WA_INITWIN 0xc0 163 164 #define MBR (sc->sc_pc[15]) 165 166 #define ISCSR (sc->sc_ps[2]) 167 168 #define CCR (sc->sc_pcx[0]) 169 #define OIR (sc->sc_pcx[1]) 170 #define AMR (sc->sc_pcx[2]) 171 #define SMR (sc->sc_pcx[3]) 172 #define SRR (sc->sc_pcx[4]) 173 #define STR (sc->sc_pcx[5]) 174 #define RTR (sc->sc_pcx[6]) 175 #define ATR (sc->sc_pcx[7]) 176 #define PER (sc->sc_pcx[8]) 177 #define IER (sc->sc_pcx[9]) 178 #define IE_ALL 0xBF 179 180 #define GLR (sc->sc_pcx[10]) 181 #define DMR (sc->sc_pcx[11]) 182 #define IMR (sc->sc_pcx[12]) 183 184 #ifndef DDB 185 #define Debugger() panic("should call debugger here (mha.c)") 186 #endif /* ! DDB */ 187 188 189 #if SPC_DEBUG 190 #define SPC_SHOWACBS 0x01 191 #define SPC_SHOWINTS 0x02 192 #define SPC_SHOWCMDS 0x04 193 #define SPC_SHOWMISC 0x08 194 #define SPC_SHOWTRAC 0x10 195 #define SPC_SHOWSTART 0x20 196 #define SPC_SHOWPHASE 0x40 197 #define SPC_SHOWDMA 0x80 198 #define SPC_SHOWCCMDS 0x100 199 #define SPC_SHOWMSGS 0x200 200 #define SPC_DOBREAK 0x400 201 202 int mha_debug = 203 #if 0 204 0x7FF; 205 #else 206 SPC_SHOWSTART|SPC_SHOWTRAC; 207 #endif 208 209 210 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 211 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 212 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 213 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 214 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 215 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 216 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 217 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 218 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 219 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 220 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 221 #else 222 #define SPC_ACBS(str) 223 #define SPC_MISC(str) 224 #define SPC_INTS(str) 225 #define SPC_TRACE(str) 226 #define SPC_CMDS(str) 227 #define SPC_START(str) 228 #define SPC_PHASE(str) 229 #define SPC_DMA(str) 230 #define SPC_MSGS(str) 231 #define SPC_BREAK() 232 #define SPC_ASSERT(x) 233 #endif 234 235 int mhamatch(struct device *, struct cfdata *, void *); 236 void mhaattach(struct device *, struct device *, void *); 237 void mhaselect(struct mha_softc *, u_char, u_char, u_char *, u_char); 238 void mha_scsi_reset(struct mha_softc *); 239 void mha_reset(struct mha_softc *); 240 void mha_free_acb(struct mha_softc *, struct acb *, int); 241 void mha_sense(struct mha_softc *, struct acb *); 242 void mha_msgin(struct mha_softc *); 243 void mha_msgout(struct mha_softc *); 244 int mha_dataout_pio(struct mha_softc *, u_char *, int); 245 int mha_datain_pio(struct mha_softc *, u_char *, int); 246 int mha_dataout(struct mha_softc *, u_char *, int); 247 int mha_datain(struct mha_softc *, u_char *, int); 248 void mha_abort(struct mha_softc *, struct acb *); 249 void mha_init(struct mha_softc *); 250 void mha_scsi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 251 void mha_poll(struct mha_softc *, struct acb *); 252 void mha_sched(struct mha_softc *); 253 void mha_done(struct mha_softc *, struct acb *); 254 int mhaintr(void *); 255 void mha_timeout(void *); 256 void mha_minphys(struct buf *); 257 void mha_dequeue(struct mha_softc *, struct acb *); 258 inline void mha_setsync(struct mha_softc *, struct spc_tinfo *); 259 #if SPC_DEBUG 260 void mha_print_acb(struct acb *); 261 void mha_show_scsi_cmd(struct acb *); 262 void mha_print_active_acb(void); 263 void mha_dump_driver(struct mha_softc *); 264 #endif 265 266 static int mha_dataio_dma(int, int, struct mha_softc *, u_char *, int); 267 268 CFATTACH_DECL(mha, sizeof(struct mha_softc), 269 mhamatch, mhaattach, NULL, NULL); 270 271 extern struct cfdriver mha_cd; 272 273 /* 274 * returns non-zero value if a controller is found. 275 */ 276 int 277 mhamatch(struct device *parent, struct cfdata *cf, void *aux) 278 { 279 struct intio_attach_args *ia = aux; 280 bus_space_tag_t iot = ia->ia_bst; 281 bus_space_handle_t ioh; 282 283 ia->ia_size=0x20; 284 if (ia->ia_addr != 0xea0000) 285 return 0; 286 287 if (intio_map_allocate_region(device_parent(parent), ia, 288 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 289 return 0; 290 291 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 292 &ioh) < 0) 293 return 0; 294 if (!badaddr(INTIO_ADDR(ia->ia_addr + 0))) 295 return 0; 296 bus_space_unmap(iot, ioh, 0x20); 297 298 return 1; 299 } 300 301 /* 302 */ 303 304 struct mha_softc *tmpsc; 305 306 void 307 mhaattach(struct device *parent, struct device *self, void *aux) 308 { 309 struct mha_softc *sc = (void *)self; 310 struct intio_attach_args *ia = aux; 311 312 tmpsc = sc; /* XXX */ 313 314 printf(": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 315 316 SPC_TRACE(("mhaattach ")); 317 sc->sc_state = SPC_INIT; 318 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 319 intio_map_allocate_region(device_parent(parent), ia, INTIO_MAP_ALLOCATE); 320 /* XXX: FAKE */ 321 sc->sc_dmat = ia->ia_dmat; 322 323 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 324 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 325 sc->sc_pcx = &sc->sc_pc[0x10]; 326 327 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 328 329 intio_intr_establish(ia->ia_intr, "mha", mhaintr, sc); 330 331 mha_init(sc); /* Init chip and driver */ 332 333 mha_scsi_reset(sc); /* XXX: some devices need this. */ 334 335 sc->sc_phase = BUSFREE_PHASE; 336 337 /* 338 * Fill in the adapter. 339 */ 340 sc->sc_adapter.adapt_dev = &sc->sc_dev; 341 sc->sc_adapter.adapt_nchannels = 1; 342 sc->sc_adapter.adapt_openings = 7; 343 sc->sc_adapter.adapt_max_periph = 1; 344 sc->sc_adapter.adapt_ioctl = NULL; 345 sc->sc_adapter.adapt_minphys = mha_minphys; 346 sc->sc_adapter.adapt_request = mha_scsi_request; 347 348 sc->sc_channel.chan_adapter = &sc->sc_adapter; 349 sc->sc_channel.chan_bustype = &scsi_bustype; 350 sc->sc_channel.chan_channel = 0; 351 sc->sc_channel.chan_ntargets = 8; 352 sc->sc_channel.chan_nluns = 8; 353 sc->sc_channel.chan_id = sc->sc_id; 354 355 sc->sc_spcinitialized = 0; 356 WAR = WA_INITWIN; 357 #if 1 358 CCR = 0x14; 359 OIR = sc->sc_id; 360 AMR = 0x00; 361 SMR = 0x00; 362 SRR = 0x00; 363 STR = 0x20; 364 RTR = 0x40; 365 ATR = 0x01; 366 PER = 0xc9; 367 #endif 368 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 369 #if 1 370 GLR = 0x00; 371 DMR = 0x30; 372 IMR = 0x00; 373 #endif 374 WAR = WA_MCSBUFWIN; 375 376 /* drop off */ 377 while (SSR & SS_IREQUEST) { 378 (void) ISCSR; 379 } 380 381 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 382 383 SPC_TRACE(("waiting for intr...")); 384 while (!(SSR & SS_IREQUEST)) 385 delay(10); 386 mhaintr(sc); 387 388 tmpsc = NULL; 389 390 config_found(self, &sc->sc_channel, scsiprint); 391 } 392 393 #if 0 394 void 395 mha_reset(struct mha_softc *sc) 396 { 397 u_short dummy; 398 printf("reset..."); 399 CMR = CMD_SOFT_RESET; 400 __asm volatile ("nop"); /* XXX wait (4clk in 20 MHz) ??? */ 401 dummy = sc->sc_ps[-1]; 402 dummy = sc->sc_ps[-1]; 403 dummy = sc->sc_ps[-1]; 404 dummy = sc->sc_ps[-1]; 405 __asm volatile ("nop"); 406 CMR = CMD_SOFT_RESET; 407 sc->sc_spcinitialized = 0; 408 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 409 while(!sc->sc_spcinitialized); 410 411 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 412 printf("done.\n"); 413 } 414 #endif 415 416 /* 417 * Pull the SCSI RST line for 500us. 418 */ 419 void 420 mha_scsi_reset(struct mha_softc *sc) 421 { 422 423 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 424 while (!(SSR&SS_IREQUEST)) 425 delay(10); 426 } 427 428 /* 429 * Initialize mha SCSI driver. 430 */ 431 void 432 mha_init(struct mha_softc *sc) 433 { 434 struct acb *acb; 435 int r; 436 437 if (sc->sc_state == SPC_INIT) { 438 /* First time through; initialize. */ 439 TAILQ_INIT(&sc->ready_list); 440 TAILQ_INIT(&sc->nexus_list); 441 TAILQ_INIT(&sc->free_list); 442 sc->sc_nexus = NULL; 443 acb = sc->sc_acb; 444 memset(acb, 0, sizeof(sc->sc_acb)); 445 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 446 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 447 acb++; 448 } 449 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 450 451 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 452 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 453 BUS_DMA_NOWAIT); 454 if (r) 455 panic("mha_init: cannot allocate DMA memory"); 456 if (sc->sc_ndmasegs != 1) 457 panic("mha_init: number of segment > 1??"); 458 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 459 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 460 if (r) 461 panic("mha_init: cannot map DMA memory"); 462 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 463 MAXBSIZE, 0, BUS_DMA_NOWAIT, 464 &sc->sc_dmamap); 465 if (r) 466 panic("mha_init: cannot create dmamap structure"); 467 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 468 sc->sc_dmabuf, MAXBSIZE, NULL, 469 BUS_DMA_NOWAIT); 470 if (r) 471 panic("mha_init: cannot load DMA buffer into dmamap"); 472 sc->sc_p = 0; 473 } else { 474 /* Cancel any active commands. */ 475 sc->sc_flags |= SPC_ABORTING; 476 sc->sc_state = SPC_IDLE; 477 if ((acb = sc->sc_nexus) != NULL) { 478 acb->xs->error = XS_DRIVER_STUFFUP; 479 mha_done(sc, acb); 480 } 481 while ((acb = sc->nexus_list.tqh_first) != NULL) { 482 acb->xs->error = XS_DRIVER_STUFFUP; 483 mha_done(sc, acb); 484 } 485 } 486 487 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 488 for (r = 0; r < 8; r++) { 489 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 490 491 ti->flags = 0; 492 #if SPC_USE_SYNCHRONOUS 493 ti->flags |= T_SYNCMODE; 494 ti->period = sc->sc_minsync; 495 ti->offset = SPC_SYNC_REQ_ACK_OFS; 496 #else 497 ti->period = ti->offset = 0; 498 #endif 499 ti->width = 0; 500 } 501 502 sc->sc_state = SPC_IDLE; 503 } 504 505 void 506 mha_free_acb(struct mha_softc *sc, struct acb *acb, int flags) 507 { 508 int s; 509 510 s = splbio(); 511 512 acb->flags = 0; 513 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 514 515 /* 516 * If there were none, wake anybody waiting for one to come free, 517 * starting with queued entries. 518 */ 519 if (acb->chain.tqe_next == 0) 520 wakeup(&sc->free_list); 521 522 splx(s); 523 } 524 525 /* 526 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 527 */ 528 529 /* 530 * Expected sequence: 531 * 1) Command inserted into ready list 532 * 2) Command selected for execution 533 * 3) Command won arbitration and has selected target device 534 * 4) Send message out (identify message, eventually also sync.negotiations) 535 * 5) Send command 536 * 5a) Receive disconnect message, disconnect. 537 * 5b) Reselected by target 538 * 5c) Receive identify message from target. 539 * 6) Send or receive data 540 * 7) Receive status 541 * 8) Receive message (command complete etc.) 542 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 543 * Repeat 2-8 (no disconnects please...) 544 */ 545 546 /* 547 * Start a selection. This is used by mha_sched() to select an idle target, 548 * and by mha_done() to immediately reselect a target to get sense information. 549 */ 550 void 551 mhaselect(struct mha_softc *sc, u_char target, u_char lun, u_char *cmd, 552 u_char clen) 553 { 554 int i; 555 int s; 556 557 s = splbio(); /* XXX */ 558 559 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 560 561 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 562 /* Now the command into the FIFO */ 563 WAIT; 564 #if 1 565 SPC_MISC(("[cmd:")); 566 for (i = 0; i < clen; i++) { 567 unsigned c = cmd[i]; 568 if (i == 1) 569 c |= lun << 5; 570 SPC_MISC((" %02x", c)); 571 sc->sc_pcx[i] = c; 572 } 573 SPC_MISC(("], target=%d\n", target)); 574 #else 575 memcpy(sc->sc_pcx, cmd, clen); 576 #endif 577 if (NSR & 0x80) 578 panic("scsistart: already selected..."); 579 sc->sc_phase = COMMAND_PHASE; 580 581 /* new state ASP_SELECTING */ 582 sc->sc_state = SPC_SELECTING; 583 584 SIR = target; 585 #if 0 586 CMR = CMD_SELECT; 587 #else 588 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 589 #endif 590 splx(s); 591 } 592 593 #if 0 594 int 595 mha_reselect(struct mha_softc *sc, u_char message) 596 { 597 u_char selid, target, lun; 598 struct acb *acb; 599 struct scsipi_periph *periph; 600 struct spc_tinfo *ti; 601 602 /* 603 * The SCSI chip made a snapshot of the data bus while the reselection 604 * was being negotiated. This enables us to determine which target did 605 * the reselect. 606 */ 607 selid = sc->sc_selid & ~(1 << sc->sc_id); 608 if (selid & (selid - 1)) { 609 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 610 sc->sc_dev.dv_xname, selid); 611 SPC_BREAK(); 612 goto reset; 613 } 614 615 /* 616 * Search wait queue for disconnected cmd 617 * The list should be short, so I haven't bothered with 618 * any more sophisticated structures than a simple 619 * singly linked list. 620 */ 621 target = ffs(selid) - 1; 622 lun = message & 0x07; 623 for (acb = sc->nexus_list.tqh_first; acb != NULL; 624 acb = acb->chain.tqe_next) { 625 periph = acb->xs->xs_periph; 626 if (periph->periph_target == target && 627 periph->periph_lun == lun) 628 break; 629 } 630 if (acb == NULL) { 631 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 632 sc->sc_dev.dv_xname, target, lun); 633 SPC_BREAK(); 634 goto abort; 635 } 636 637 /* Make this nexus active again. */ 638 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 639 sc->sc_state = SPC_HASNEXUS; 640 sc->sc_nexus = acb; 641 ti = &sc->sc_tinfo[target]; 642 ti->lubusy |= (1 << lun); 643 mha_setsync(sc, ti); 644 645 if (acb->flags & ACB_RESET) 646 mha_sched_msgout(sc, SEND_DEV_RESET); 647 else if (acb->flags & ACB_ABORTED) 648 mha_sched_msgout(sc, SEND_ABORT); 649 650 /* Do an implicit RESTORE POINTERS. */ 651 sc->sc_dp = acb->daddr; 652 sc->sc_dleft = acb->dleft; 653 sc->sc_cp = (u_char *)&acb->cmd; 654 sc->sc_cleft = acb->clen; 655 656 return (0); 657 658 reset: 659 mha_sched_msgout(sc, SEND_DEV_RESET); 660 return (1); 661 662 abort: 663 mha_sched_msgout(sc, SEND_ABORT); 664 return (1); 665 } 666 #endif 667 /* 668 * Start a SCSI-command 669 * This function is called by the higher level SCSI-driver to queue/run 670 * SCSI-commands. 671 */ 672 void 673 mha_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 674 void *arg) 675 { 676 struct scsipi_xfer *xs; 677 struct scsipi_periph *periph; 678 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 679 struct acb *acb; 680 int s, flags; 681 682 switch (req) { 683 case ADAPTER_REQ_RUN_XFER: 684 xs = arg; 685 periph = xs->xs_periph; 686 687 SPC_TRACE(("[mha_scsi_cmd] ")); 688 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 689 periph->periph_target)); 690 691 flags = xs->xs_control; 692 693 /* Get a mha command block */ 694 s = splbio(); 695 acb = sc->free_list.tqh_first; 696 if (acb) { 697 TAILQ_REMOVE(&sc->free_list, acb, chain); 698 ACB_SETQ(acb, ACB_QNONE); 699 } 700 701 if (acb == NULL) { 702 xs->error = XS_RESOURCE_SHORTAGE; 703 scsipi_done(xs); 704 splx(s); 705 return; 706 } 707 splx(s); 708 709 /* Initialize acb */ 710 acb->xs = xs; 711 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 712 acb->clen = xs->cmdlen; 713 acb->daddr = xs->data; 714 acb->dleft = xs->datalen; 715 acb->stat = 0; 716 717 s = splbio(); 718 ACB_SETQ(acb, ACB_QREADY); 719 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 720 #if 1 721 callout_reset(&acb->xs->xs_callout, 722 mstohz(xs->timeout), mha_timeout, acb); 723 #endif 724 725 /* 726 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 727 */ 728 if (sc->sc_state == SPC_IDLE) 729 mha_sched(sc); 730 731 splx(s); 732 733 if (flags & XS_CTL_POLL) { 734 /* Not allowed to use interrupts, use polling instead */ 735 mha_poll(sc, acb); 736 } 737 738 SPC_MISC(("SUCCESSFULLY_QUEUED")); 739 return; 740 741 case ADAPTER_REQ_GROW_RESOURCES: 742 /* XXX Not supported. */ 743 return; 744 745 case ADAPTER_REQ_SET_XFER_MODE: 746 /* XXX Not supported. */ 747 return; 748 } 749 } 750 751 /* 752 * Adjust transfer size in buffer structure 753 */ 754 void 755 mha_minphys(struct buf *bp) 756 { 757 758 SPC_TRACE(("mha_minphys ")); 759 minphys(bp); 760 } 761 762 /* 763 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 764 */ 765 void 766 mha_poll(struct mha_softc *sc, struct acb *acb) 767 { 768 struct scsipi_xfer *xs = acb->xs; 769 int count = xs->timeout * 100; 770 int s; 771 772 s = splbio(); 773 774 SPC_TRACE(("[mha_poll] ")); 775 776 while (count) { 777 /* 778 * If we had interrupts enabled, would we 779 * have got an interrupt? 780 */ 781 if (SSR & SS_IREQUEST) 782 mhaintr(sc); 783 if ((xs->xs_status & XS_STS_DONE) != 0) 784 break; 785 DELAY(10); 786 #if 1 787 if (sc->sc_state == SPC_IDLE) { 788 SPC_TRACE(("[mha_poll: rescheduling] ")); 789 mha_sched(sc); 790 } 791 #endif 792 count--; 793 } 794 795 if (count == 0) { 796 SPC_MISC(("mha_poll: timeout")); 797 mha_timeout((void *)acb); 798 } 799 splx(s); 800 scsipi_done(xs); 801 } 802 803 /* 804 * LOW LEVEL SCSI UTILITIES 805 */ 806 807 /* 808 * Set synchronous transfer offset and period. 809 */ 810 inline void 811 mha_setsync(struct mha_softc *sc, struct spc_tinfo *ti) 812 { 813 } 814 815 /* 816 * Schedule a SCSI operation. This has now been pulled out of the interrupt 817 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 818 * save us an unecessary interrupt just to get things going. Should only be 819 * called when state == SPC_IDLE and at bio pl. 820 */ 821 void 822 mha_sched(struct mha_softc *sc) 823 { 824 struct scsipi_periph *periph; 825 struct acb *acb; 826 int t; 827 828 SPC_TRACE(("[mha_sched] ")); 829 if (sc->sc_state != SPC_IDLE) 830 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 831 832 if (sc->sc_flags & SPC_ABORTING) 833 return; 834 835 /* 836 * Find first acb in ready queue that is for a target/lunit 837 * combinations that is not busy. 838 */ 839 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 840 struct spc_tinfo *ti; 841 periph = acb->xs->xs_periph; 842 t = periph->periph_target; 843 ti = &sc->sc_tinfo[t]; 844 if (!(ti->lubusy & (1 << periph->periph_lun))) { 845 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 846 panic("mha: busy entry on ready list"); 847 TAILQ_REMOVE(&sc->ready_list, acb, chain); 848 ACB_SETQ(acb, ACB_QNONE); 849 sc->sc_nexus = acb; 850 sc->sc_flags = 0; 851 sc->sc_prevphase = INVALID_PHASE; 852 sc->sc_dp = acb->daddr; 853 sc->sc_dleft = acb->dleft; 854 ti->lubusy |= (1<<periph->periph_lun); 855 mhaselect(sc, t, periph->periph_lun, 856 (u_char *)&acb->cmd, acb->clen); 857 break; 858 } else { 859 SPC_MISC(("%d:%d busy\n", 860 periph->periph_target, 861 periph->periph_lun)); 862 } 863 } 864 } 865 866 /* 867 * POST PROCESSING OF SCSI_CMD (usually current) 868 */ 869 void 870 mha_done(struct mha_softc *sc, struct acb *acb) 871 { 872 struct scsipi_xfer *xs = acb->xs; 873 struct scsipi_periph *periph = xs->xs_periph; 874 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 875 876 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 877 878 #if 1 879 callout_stop(&acb->xs->xs_callout); 880 #endif 881 882 /* 883 * Now, if we've come here with no error code, i.e. we've kept the 884 * initial XS_NOERROR, and the status code signals that we should 885 * check sense, we'll need to set up a request sense cmd block and 886 * push the command back into the ready queue *before* any other 887 * commands for this target/lunit, else we lose the sense info. 888 * We don't support chk sense conditions for the request sense cmd. 889 */ 890 if (xs->error == XS_NOERROR) { 891 if ((acb->flags & ACB_ABORTED) != 0) { 892 xs->error = XS_TIMEOUT; 893 } else if (acb->flags & ACB_CHKSENSE) { 894 xs->error = XS_SENSE; 895 } else { 896 xs->status = acb->stat & ST_MASK; 897 switch (xs->status) { 898 case SCSI_CHECK: 899 xs->resid = acb->dleft; 900 /* FALLTHROUGH */ 901 case SCSI_BUSY: 902 xs->error = XS_BUSY; 903 break; 904 case SCSI_OK: 905 xs->resid = acb->dleft; 906 break; 907 default: 908 xs->error = XS_DRIVER_STUFFUP; 909 #if SPC_DEBUG 910 printf("%s: mha_done: bad stat 0x%x\n", 911 sc->sc_dev.dv_xname, acb->stat); 912 #endif 913 break; 914 } 915 } 916 } 917 918 #if SPC_DEBUG 919 if ((mha_debug & SPC_SHOWMISC) != 0) { 920 if (xs->resid != 0) 921 printf("resid=%d ", xs->resid); 922 if (xs->error == XS_SENSE) 923 printf("sense=0x%02x\n", xs->sense.scsi_sense.response_code); 924 else 925 printf("error=%d\n", xs->error); 926 } 927 #endif 928 929 /* 930 * Remove the ACB from whatever queue it's on. 931 */ 932 switch (acb->flags & ACB_QBITS) { 933 case ACB_QNONE: 934 if (acb != sc->sc_nexus) { 935 panic("%s: floating acb", sc->sc_dev.dv_xname); 936 } 937 sc->sc_nexus = NULL; 938 sc->sc_state = SPC_IDLE; 939 ti->lubusy &= ~(1<<periph->periph_lun); 940 mha_sched(sc); 941 break; 942 case ACB_QREADY: 943 TAILQ_REMOVE(&sc->ready_list, acb, chain); 944 break; 945 case ACB_QNEXUS: 946 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 947 ti->lubusy &= ~(1<<periph->periph_lun); 948 break; 949 case ACB_QFREE: 950 panic("%s: dequeue: busy acb on free list", 951 sc->sc_dev.dv_xname); 952 break; 953 default: 954 panic("%s: dequeue: unknown queue %d", 955 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 956 } 957 958 /* Put it on the free list, and clear flags. */ 959 #if 0 960 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 961 acb->flags = ACB_QFREE; 962 #else 963 mha_free_acb(sc, acb, xs->xs_control); 964 #endif 965 966 ti->cmds++; 967 scsipi_done(xs); 968 } 969 970 void 971 mha_dequeue(struct mha_softc *sc, struct acb *acb) 972 { 973 974 if (acb->flags & ACB_QNEXUS) { 975 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 976 } else { 977 TAILQ_REMOVE(&sc->ready_list, acb, chain); 978 } 979 } 980 981 /* 982 * INTERRUPT/PROTOCOL ENGINE 983 */ 984 985 /* 986 * Schedule an outgoing message by prioritizing it, and asserting 987 * attention on the bus. We can only do this when we are the initiator 988 * else there will be an illegal command interrupt. 989 */ 990 #define mha_sched_msgout(m) \ 991 do { \ 992 SPC_MISC(("mha_sched_msgout %d ", m)); \ 993 CMR = CMD_SET_ATN; \ 994 sc->sc_msgpriq |= (m); \ 995 } while (0) 996 997 /* 998 * Precondition: 999 * The SCSI bus is already in the MSGI phase and there is a message byte 1000 * on the bus, along with an asserted REQ signal. 1001 */ 1002 void 1003 mha_msgin(struct mha_softc *sc) 1004 { 1005 int v; 1006 1007 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1008 1009 /* 1010 * Prepare for a new message. A message should (according 1011 * to the SCSI standard) be transmitted in one single 1012 * MESSAGE_IN_PHASE. If we have been in some other phase, 1013 * then this is a new message. 1014 */ 1015 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1016 sc->sc_flags &= ~SPC_DROP_MSGI; 1017 sc->sc_imlen = 0; 1018 } 1019 1020 WAIT; 1021 1022 v = MBR; /* modified byte */ 1023 v = sc->sc_pcx[0]; 1024 1025 sc->sc_imess[sc->sc_imlen] = v; 1026 1027 /* 1028 * If we're going to reject the message, don't bother storing 1029 * the incoming bytes. But still, we need to ACK them. 1030 */ 1031 1032 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1033 CMR = CMD_SET_ATN; 1034 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1035 printf("<dropping msg byte %x>", 1036 sc->sc_imess[sc->sc_imlen]); 1037 return; 1038 } 1039 1040 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1041 mha_sched_msgout(SEND_REJECT); 1042 sc->sc_flags |= SPC_DROP_MSGI; 1043 } else { 1044 sc->sc_imlen++; 1045 /* 1046 * This testing is suboptimal, but most 1047 * messages will be of the one byte variety, so 1048 * it should not effect performance 1049 * significantly. 1050 */ 1051 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1052 goto gotit; 1053 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1054 goto gotit; 1055 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1056 sc->sc_imlen == sc->sc_imess[1] + 2) 1057 goto gotit; 1058 } 1059 #if 0 1060 /* Ack what we have so far */ 1061 ESPCMD(sc, ESPCMD_MSGOK); 1062 #endif 1063 return; 1064 1065 gotit: 1066 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1067 /* 1068 * Now we should have a complete message (1 byte, 2 byte 1069 * and moderately long extended messages). We only handle 1070 * extended messages which total length is shorter than 1071 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1072 */ 1073 if (sc->sc_state == SPC_HASNEXUS) { 1074 struct acb *acb = sc->sc_nexus; 1075 struct spc_tinfo *ti = 1076 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1077 1078 switch (sc->sc_imess[0]) { 1079 case MSG_CMDCOMPLETE: 1080 SPC_MSGS(("cmdcomplete ")); 1081 if (sc->sc_dleft < 0) { 1082 struct scsipi_periph *periph = acb->xs->xs_periph; 1083 printf("mha: %d extra bytes from %d:%d\n", 1084 -sc->sc_dleft, 1085 periph->periph_target, 1086 periph->periph_lun); 1087 sc->sc_dleft = 0; 1088 } 1089 acb->xs->resid = acb->dleft = sc->sc_dleft; 1090 sc->sc_flags |= SPC_BUSFREE_OK; 1091 break; 1092 1093 case MSG_MESSAGE_REJECT: 1094 #if SPC_DEBUG 1095 if (mha_debug & SPC_SHOWMSGS) 1096 printf("%s: our msg rejected by target\n", 1097 sc->sc_dev.dv_xname); 1098 #endif 1099 #if 1 /* XXX - must remember last message */ 1100 scsipi_printaddr(acb->xs->xs_periph); 1101 printf("MSG_MESSAGE_REJECT>>"); 1102 #endif 1103 if (sc->sc_flags & SPC_SYNCHNEGO) { 1104 ti->period = ti->offset = 0; 1105 sc->sc_flags &= ~SPC_SYNCHNEGO; 1106 ti->flags &= ~T_NEGOTIATE; 1107 } 1108 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1109 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1110 mha_sched_msgout(SEND_ABORT); 1111 break; 1112 case MSG_NOOP: 1113 SPC_MSGS(("noop ")); 1114 break; 1115 case MSG_DISCONNECT: 1116 SPC_MSGS(("disconnect ")); 1117 ti->dconns++; 1118 sc->sc_flags |= SPC_DISCON; 1119 sc->sc_flags |= SPC_BUSFREE_OK; 1120 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1121 break; 1122 /*FALLTHROUGH*/ 1123 case MSG_SAVEDATAPOINTER: 1124 SPC_MSGS(("save datapointer ")); 1125 acb->dleft = sc->sc_dleft; 1126 acb->daddr = sc->sc_dp; 1127 break; 1128 case MSG_RESTOREPOINTERS: 1129 SPC_MSGS(("restore datapointer ")); 1130 if (!acb) { 1131 mha_sched_msgout(SEND_ABORT); 1132 printf("%s: no DATAPOINTERs to restore\n", 1133 sc->sc_dev.dv_xname); 1134 break; 1135 } 1136 sc->sc_dp = acb->daddr; 1137 sc->sc_dleft = acb->dleft; 1138 break; 1139 case MSG_PARITY_ERROR: 1140 printf("%s:target%d: MSG_PARITY_ERROR\n", 1141 sc->sc_dev.dv_xname, 1142 acb->xs->xs_periph->periph_target); 1143 break; 1144 case MSG_EXTENDED: 1145 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1146 switch (sc->sc_imess[2]) { 1147 case MSG_EXT_SDTR: 1148 SPC_MSGS(("SDTR period %d, offset %d ", 1149 sc->sc_imess[3], sc->sc_imess[4])); 1150 ti->period = sc->sc_imess[3]; 1151 ti->offset = sc->sc_imess[4]; 1152 if (sc->sc_minsync == 0) { 1153 /* We won't do synch */ 1154 ti->offset = 0; 1155 mha_sched_msgout(SEND_SDTR); 1156 } else if (ti->offset == 0) { 1157 printf("%s:%d: async\n", "mha", 1158 acb->xs->xs_periph->periph_target); 1159 ti->offset = 0; 1160 sc->sc_flags &= ~SPC_SYNCHNEGO; 1161 } else if (ti->period > 124) { 1162 printf("%s:%d: async\n", "mha", 1163 acb->xs->xs_periph->periph_target); 1164 ti->offset = 0; 1165 mha_sched_msgout(SEND_SDTR); 1166 } else { 1167 #if 0 1168 int p; 1169 p = mha_stp2cpb(sc, ti->period); 1170 ti->period = mha_cpb2stp(sc, p); 1171 #endif 1172 1173 #if SPC_DEBUG 1174 scsipi_printaddr(acb->xs->xs_periph); 1175 #endif 1176 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1177 /* Target initiated negotiation */ 1178 if (ti->flags & T_SYNCMODE) { 1179 ti->flags &= ~T_SYNCMODE; 1180 #if SPC_DEBUG 1181 printf("renegotiated "); 1182 #endif 1183 } 1184 TMR=TM_ASYNC; 1185 /* Clamp to our maxima */ 1186 if (ti->period < sc->sc_minsync) 1187 ti->period = sc->sc_minsync; 1188 if (ti->offset > 15) 1189 ti->offset = 15; 1190 mha_sched_msgout(SEND_SDTR); 1191 } else { 1192 /* we are sync */ 1193 sc->sc_flags &= ~SPC_SYNCHNEGO; 1194 TMR = TM_SYNC; 1195 ti->flags |= T_SYNCMODE; 1196 } 1197 } 1198 ti->flags &= ~T_NEGOTIATE; 1199 break; 1200 default: /* Extended messages we don't handle */ 1201 CMR = CMD_SET_ATN; /* XXX? */ 1202 break; 1203 } 1204 break; 1205 default: 1206 SPC_MSGS(("ident ")); 1207 /* thanks for that ident... */ 1208 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1209 SPC_MISC(("unknown ")); 1210 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1211 CMR = CMD_SET_ATN; /* XXX? */ 1212 } 1213 break; 1214 } 1215 } else if (sc->sc_state == SPC_RESELECTED) { 1216 struct scsipi_periph *periph = NULL; 1217 struct acb *acb; 1218 struct spc_tinfo *ti; 1219 u_char lunit; 1220 1221 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1222 SPC_MISC(("searching ")); 1223 /* 1224 * Search wait queue for disconnected cmd 1225 * The list should be short, so I haven't bothered with 1226 * any more sophisticated structures than a simple 1227 * singly linked list. 1228 */ 1229 lunit = sc->sc_imess[0] & 0x07; 1230 for (acb = sc->nexus_list.tqh_first; acb; 1231 acb = acb->chain.tqe_next) { 1232 periph = acb->xs->xs_periph; 1233 if (periph->periph_lun == lunit && 1234 sc->sc_selid == (1<<periph->periph_target)) { 1235 TAILQ_REMOVE(&sc->nexus_list, acb, 1236 chain); 1237 ACB_SETQ(acb, ACB_QNONE); 1238 break; 1239 } 1240 } 1241 1242 if (!acb) { /* Invalid reselection! */ 1243 mha_sched_msgout(SEND_ABORT); 1244 printf("mha: invalid reselect (idbit=0x%2x)\n", 1245 sc->sc_selid); 1246 } else { /* Reestablish nexus */ 1247 /* 1248 * Setup driver data structures and 1249 * do an implicit RESTORE POINTERS 1250 */ 1251 ti = &sc->sc_tinfo[periph->periph_target]; 1252 sc->sc_nexus = acb; 1253 sc->sc_dp = acb->daddr; 1254 sc->sc_dleft = acb->dleft; 1255 sc->sc_tinfo[periph->periph_target].lubusy 1256 |= (1<<periph->periph_lun); 1257 if (ti->flags & T_SYNCMODE) { 1258 TMR = TM_SYNC; /* XXX */ 1259 } else { 1260 TMR = TM_ASYNC; 1261 } 1262 SPC_MISC(("... found acb")); 1263 sc->sc_state = SPC_HASNEXUS; 1264 } 1265 } else { 1266 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1267 sc->sc_dev.dv_xname, sc->sc_selid); 1268 mha_sched_msgout(SEND_DEV_RESET); 1269 } 1270 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1271 printf("%s: unexpected message in; will send DEV_RESET\n", 1272 sc->sc_dev.dv_xname); 1273 mha_sched_msgout(SEND_DEV_RESET); 1274 } 1275 1276 /* Ack last message byte */ 1277 #if 0 1278 ESPCMD(sc, ESPCMD_MSGOK); 1279 #endif 1280 1281 /* Done, reset message pointer. */ 1282 sc->sc_flags &= ~SPC_DROP_MSGI; 1283 sc->sc_imlen = 0; 1284 } 1285 1286 /* 1287 * Send the highest priority, scheduled message. 1288 */ 1289 void 1290 mha_msgout(struct mha_softc *sc) 1291 { 1292 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE) 1293 struct spc_tinfo *ti; 1294 #endif 1295 int n; 1296 1297 SPC_TRACE(("mha_msgout ")); 1298 1299 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1300 if (sc->sc_omp == sc->sc_omess) { 1301 /* 1302 * This is a retransmission. 1303 * 1304 * We get here if the target stayed in MESSAGE OUT 1305 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1306 * that all of the previously transmitted messages must 1307 * be sent again, in the same order. Therefore, we 1308 * requeue all the previously transmitted messages, and 1309 * start again from the top. Our simple priority 1310 * scheme keeps the messages in the right order. 1311 */ 1312 SPC_MISC(("retransmitting ")); 1313 sc->sc_msgpriq |= sc->sc_msgoutq; 1314 /* 1315 * Set ATN. If we're just sending a trivial 1-byte 1316 * message, we'll clear ATN later on anyway. 1317 */ 1318 CMR = CMD_SET_ATN; /* XXX? */ 1319 } else { 1320 /* This is a continuation of the previous message. */ 1321 n = sc->sc_omp - sc->sc_omess; 1322 goto nextbyte; 1323 } 1324 } 1325 1326 /* No messages transmitted so far. */ 1327 sc->sc_msgoutq = 0; 1328 sc->sc_lastmsg = 0; 1329 1330 nextmsg: 1331 /* Pick up highest priority message. */ 1332 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1333 sc->sc_msgpriq &= ~sc->sc_currmsg; 1334 sc->sc_msgoutq |= sc->sc_currmsg; 1335 1336 /* Build the outgoing message data. */ 1337 switch (sc->sc_currmsg) { 1338 case SEND_IDENTIFY: 1339 SPC_ASSERT(sc->sc_nexus != NULL); 1340 sc->sc_omess[0] = 1341 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1342 n = 1; 1343 break; 1344 1345 #if SPC_USE_SYNCHRONOUS 1346 case SEND_SDTR: 1347 SPC_ASSERT(sc->sc_nexus != NULL); 1348 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1349 sc->sc_omess[4] = MSG_EXTENDED; 1350 sc->sc_omess[3] = 3; 1351 sc->sc_omess[2] = MSG_EXT_SDTR; 1352 sc->sc_omess[1] = ti->period >> 2; 1353 sc->sc_omess[0] = ti->offset; 1354 n = 5; 1355 break; 1356 #endif 1357 1358 #if SPC_USE_WIDE 1359 case SEND_WDTR: 1360 SPC_ASSERT(sc->sc_nexus != NULL); 1361 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1362 sc->sc_omess[3] = MSG_EXTENDED; 1363 sc->sc_omess[2] = 2; 1364 sc->sc_omess[1] = MSG_EXT_WDTR; 1365 sc->sc_omess[0] = ti->width; 1366 n = 4; 1367 break; 1368 #endif 1369 1370 case SEND_DEV_RESET: 1371 sc->sc_flags |= SPC_ABORTING; 1372 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1373 n = 1; 1374 break; 1375 1376 case SEND_REJECT: 1377 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1378 n = 1; 1379 break; 1380 1381 case SEND_PARITY_ERROR: 1382 sc->sc_omess[0] = MSG_PARITY_ERROR; 1383 n = 1; 1384 break; 1385 1386 case SEND_INIT_DET_ERR: 1387 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1388 n = 1; 1389 break; 1390 1391 case SEND_ABORT: 1392 sc->sc_flags |= SPC_ABORTING; 1393 sc->sc_omess[0] = MSG_ABORT; 1394 n = 1; 1395 break; 1396 1397 default: 1398 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1399 sc->sc_dev.dv_xname); 1400 SPC_BREAK(); 1401 sc->sc_omess[0] = MSG_NOOP; 1402 n = 1; 1403 break; 1404 } 1405 sc->sc_omp = &sc->sc_omess[n]; 1406 1407 nextbyte: 1408 /* Send message bytes. */ 1409 /* send TRANSFER command. */ 1410 sc->sc_ps[3] = 1; 1411 sc->sc_ps[4] = n >> 8; 1412 sc->sc_pc[10] = n; 1413 sc->sc_ps[-1] = 0x000F; /* burst */ 1414 __asm volatile ("nop"); 1415 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1416 for (;;) { 1417 if ((SSR & SS_BUSY) != 0) 1418 break; 1419 if (SSR & SS_IREQUEST) 1420 goto out; 1421 } 1422 for (;;) { 1423 #if 0 1424 for (;;) { 1425 if ((PSNS & PSNS_REQ) != 0) 1426 break; 1427 /* Wait for REQINIT. XXX Need timeout. */ 1428 } 1429 #endif 1430 if (SSR & SS_IREQUEST) { 1431 /* 1432 * Target left MESSAGE OUT, possibly to reject 1433 * our message. 1434 * 1435 * If this is the last message being sent, then we 1436 * deassert ATN, since either the target is going to 1437 * ignore this message, or it's going to ask for a 1438 * retransmission via MESSAGE PARITY ERROR (in which 1439 * case we reassert ATN anyway). 1440 */ 1441 #if 0 1442 if (sc->sc_msgpriq == 0) 1443 CMR = CMD_RESET_ATN; 1444 #endif 1445 goto out; 1446 } 1447 1448 #if 0 1449 /* Clear ATN before last byte if this is the last message. */ 1450 if (n == 1 && sc->sc_msgpriq == 0) 1451 CMR = CMD_RESET_ATN; 1452 #endif 1453 1454 while ((SSR & SS_DREG_FULL) != 0) 1455 ; 1456 /* Send message byte. */ 1457 sc->sc_pc[0] = *--sc->sc_omp; 1458 --n; 1459 /* Keep track of the last message we've sent any bytes of. */ 1460 sc->sc_lastmsg = sc->sc_currmsg; 1461 1462 if (n == 0) 1463 break; 1464 } 1465 1466 /* We get here only if the entire message has been transmitted. */ 1467 if (sc->sc_msgpriq != 0) { 1468 /* There are more outgoing messages. */ 1469 goto nextmsg; 1470 } 1471 1472 /* 1473 * The last message has been transmitted. We need to remember the last 1474 * message transmitted (in case the target switches to MESSAGE IN phase 1475 * and sends a MESSAGE REJECT), and the list of messages transmitted 1476 * this time around (in case the target stays in MESSAGE OUT phase to 1477 * request a retransmit). 1478 */ 1479 1480 out: 1481 /* Disable REQ/ACK protocol. */ 1482 return; 1483 } 1484 1485 /*************************************************************** 1486 * 1487 * datain/dataout 1488 * 1489 */ 1490 1491 int 1492 mha_datain_pio(struct mha_softc *sc, u_char *p, int n) 1493 { 1494 u_short d; 1495 int a; 1496 int total_n = n; 1497 1498 SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n)); 1499 1500 WAIT; 1501 sc->sc_ps[3] = 1; 1502 sc->sc_ps[4] = n >> 8; 1503 sc->sc_pc[10] = n; 1504 /* $BHa$7$-%=%U%HE>Aw(B */ 1505 CMR = CMD_RECEIVE_TO_MPU; 1506 for (;;) { 1507 a = SSR; 1508 if (a & 0x04) { 1509 d = sc->sc_ps[0]; 1510 *p++ = d >> 8; 1511 if (--n > 0) { 1512 *p++ = d; 1513 --n; 1514 } 1515 a = SSR; 1516 } 1517 if (a & 0x40) 1518 continue; 1519 if (a & 0x80) 1520 break; 1521 } 1522 SPC_TRACE(("...%d resd]", n)); 1523 return total_n - n; 1524 } 1525 1526 int 1527 mha_dataout_pio(struct mha_softc *sc, u_char *p, int n) 1528 { 1529 u_short d; 1530 int a; 1531 int total_n = n; 1532 1533 SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n)); 1534 1535 WAIT; 1536 sc->sc_ps[3] = 1; 1537 sc->sc_ps[4] = n >> 8; 1538 sc->sc_pc[10] = n; 1539 /* $BHa$7$-%=%U%HE>Aw(B */ 1540 CMR = CMD_SEND_FROM_MPU; 1541 for (;;) { 1542 a = SSR; 1543 if (a & 0x04) { 1544 d = *p++ << 8; 1545 if (--n > 0) { 1546 d |= *p++; 1547 --n; 1548 } 1549 sc->sc_ps[0] = d; 1550 a = SSR; 1551 } 1552 if (a & 0x40) 1553 continue; 1554 if (a & 0x80) 1555 break; 1556 } 1557 SPC_TRACE(("...%d resd]", n)); 1558 return total_n - n; 1559 } 1560 1561 /* 1562 * dw: DMA word 1563 * cw: CMR word 1564 */ 1565 static int 1566 mha_dataio_dma(int dw, int cw, struct mha_softc *sc, u_char *p, int n) 1567 { 1568 char *paddr; 1569 1570 if (n > MAXBSIZE) 1571 panic("transfer size exceeds MAXBSIZE"); 1572 if (sc->sc_dmasize > 0) 1573 panic("DMA request while another DMA transfer is in pregress"); 1574 1575 if (cw == CMD_SEND_FROM_DMA) { 1576 memcpy(sc->sc_dmabuf, p, n); 1577 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1578 } else { 1579 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1580 } 1581 sc->sc_p = p; 1582 sc->sc_dmasize = n; 1583 1584 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1585 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1586 if ((*(volatile int *)&IODEVbase->io_sram[0xac]) & 1587 (1 << ((paddr_t)paddr >> 19))) 1588 dw &= ~(1 << 3); 1589 #endif 1590 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1591 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1592 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1593 WAIT; 1594 sc->sc_ps[3] = 1; 1595 sc->sc_ps[4] = n >> 8; 1596 sc->sc_pc[10] = n; 1597 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1598 3 ... short bus cycle 1599 2 ... MAXIMUM XFER. 1600 1 ... BURST XFER. 1601 0 ... R/W */ 1602 sc->sc_ps[-1] = dw; /* burst */ 1603 __asm volatile ("nop"); 1604 CMR = cw; /* receive to DMA */ 1605 return n; 1606 } 1607 1608 int 1609 mha_dataout(struct mha_softc *sc, u_char *p, int n) 1610 { 1611 if (n == 0) 1612 return n; 1613 1614 if (n & 1) 1615 return mha_dataout_pio(sc, p, n); 1616 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1617 } 1618 1619 int 1620 mha_datain(struct mha_softc *sc, u_char *p, int n) 1621 { 1622 struct acb *acb = sc->sc_nexus; 1623 1624 if (n == 0) 1625 return n; 1626 if (acb->cmd.opcode == SCSI_REQUEST_SENSE || (n & 1)) 1627 return mha_datain_pio(sc, p, n); 1628 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1629 } 1630 1631 /* 1632 * Catch an interrupt from the adaptor 1633 */ 1634 /* 1635 * This is the workhorse routine of the driver. 1636 * Deficiencies (for now): 1637 * 1) always uses programmed I/O 1638 */ 1639 int 1640 mhaintr(void *arg) 1641 { 1642 struct mha_softc *sc = arg; 1643 #if 0 1644 u_char ints; 1645 #endif 1646 struct acb *acb; 1647 u_char ph; 1648 u_short r; 1649 int n; 1650 1651 #if 1 /* XXX called during attach? */ 1652 if (tmpsc != NULL) { 1653 SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc)); 1654 sc = tmpsc; 1655 } else { 1656 #endif 1657 1658 #if 1 /* XXX */ 1659 } 1660 #endif 1661 1662 #if 0 1663 /* 1664 * $B3d$j9~$_6X;_$K$9$k(B 1665 */ 1666 SCTL &= ~SCTL_INTR_ENAB; 1667 #endif 1668 1669 SPC_TRACE(("[mhaintr]")); 1670 1671 /* 1672 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1673 */ 1674 /* 1675 * First check for abnormal conditions, such as reset. 1676 */ 1677 #if 0 1678 #if 1 /* XXX? */ 1679 while (((ints = SSR) & SS_IREQUEST) == 0) 1680 delay(1); 1681 SPC_MISC(("ints = 0x%x ", ints)); 1682 #else /* usually? */ 1683 ints = SSR; 1684 #endif 1685 #endif 1686 while (SSR & SS_IREQUEST) { 1687 acb = sc->sc_nexus; 1688 r = ISCSR; 1689 SPC_MISC(("[r=0x%x]", r)); 1690 switch (r >> 8) { 1691 default: 1692 printf("[addr=%p\n" 1693 "result=0x%x\n" 1694 "cmd=0x%x\n" 1695 "ph=0x%x(ought to be %d)]\n", 1696 &ISCSR, 1697 r, 1698 acb->xs->cmd->opcode, 1699 SCR, sc->sc_phase); 1700 panic("unexpected result."); 1701 case 0x82: /* selection timeout */ 1702 SPC_MISC(("selection timeout ")); 1703 sc->sc_phase = BUSFREE_PHASE; 1704 SPC_ASSERT(sc->sc_nexus != NULL); 1705 acb = sc->sc_nexus; 1706 delay(250); 1707 acb->xs->error = XS_SELTIMEOUT; 1708 mha_done(sc, acb); 1709 continue; /* XXX ??? msaitoh */ 1710 case 0x60: /* command completed */ 1711 sc->sc_spcinitialized++; 1712 if (sc->sc_phase == BUSFREE_PHASE) 1713 continue; 1714 ph = SCR; 1715 if (ph & PSNS_ACK) { 1716 int s; 1717 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1718 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1719 ph & PHASE_MASK, sc->sc_phase)); 1720 #if 0 1721 /* switch (sc->sc_phase) {*/ 1722 #else 1723 switch (ph & PHASE_MASK) { 1724 #endif 1725 case STATUS_PHASE: 1726 if (sc->sc_state != SPC_HASNEXUS) 1727 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1728 sc->sc_state); 1729 SPC_ASSERT(sc->sc_nexus != NULL); 1730 acb = sc->sc_nexus; 1731 WAIT; 1732 s = MBR; 1733 SPC_ASSERT(s == 1); 1734 acb->stat = sc->sc_pcx[0]; /* XXX */ 1735 SPC_MISC(("stat=0x%02x ", acb->stat)); 1736 sc->sc_prevphase = STATUS_PHASE; 1737 break; 1738 case MESSAGE_IN_PHASE: 1739 mha_msgin(sc); 1740 sc->sc_prevphase = MESSAGE_IN_PHASE; 1741 /* thru */ 1742 case DATA_IN_PHASE: 1743 if (sc->sc_dmasize == 0) 1744 break; 1745 bus_dmamap_sync(sc->sc_dmat, 1746 sc->sc_dmamap, 1747 0, sc->sc_dmasize, 1748 BUS_DMASYNC_POSTREAD); 1749 memcpy(sc->sc_p, sc->sc_dmabuf, 1750 sc->sc_dmasize); 1751 sc->sc_dmasize = 0; 1752 break; 1753 case DATA_OUT_PHASE: 1754 if (sc->sc_dmasize == 0) 1755 break; 1756 bus_dmamap_sync(sc->sc_dmat, 1757 sc->sc_dmamap, 1758 0, sc->sc_dmasize, 1759 BUS_DMASYNC_POSTWRITE); 1760 sc->sc_dmasize = 0; 1761 break; 1762 } 1763 WAIT; 1764 CMR = CMD_RESET_ACK; /* reset ack */ 1765 /*mha_done(sc, acb); XXX */ 1766 continue; 1767 } else if (NSR & 0x80) { /* nexus */ 1768 #if 1 1769 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1770 sc->sc_state = SPC_HASNEXUS; 1771 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1772 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1773 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1774 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1775 WAIT; 1776 if (SSR & SS_IREQUEST) 1777 continue; 1778 switch (sc->sc_phase) { 1779 default: 1780 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1781 case MESSAGE_IN_PHASE: 1782 /* $B2?$b$7$J$$(B */ 1783 continue; 1784 case STATUS_PHASE: 1785 sc->sc_phase = MESSAGE_IN_PHASE; 1786 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1787 continue; 1788 case DATA_IN_PHASE: 1789 sc->sc_prevphase = DATA_IN_PHASE; 1790 if (sc->sc_dleft == 0) { 1791 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1792 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1793 sc->sc_phase = STATUS_PHASE; 1794 CMR = CMD_RECEIVE_STS; /* receive sts */ 1795 continue; 1796 } 1797 n = mha_datain(sc, sc->sc_dp, 1798 sc->sc_dleft); 1799 sc->sc_dp += n; 1800 sc->sc_dleft -= n; 1801 continue; 1802 case DATA_OUT_PHASE: 1803 sc->sc_prevphase = DATA_OUT_PHASE; 1804 if (sc->sc_dleft == 0) { 1805 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1806 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1807 sc->sc_phase = STATUS_PHASE; 1808 CMR = CMD_RECEIVE_STS; /* receive sts */ 1809 continue; 1810 } 1811 /* data phase $B$NB3$-$r$d$m$&(B */ 1812 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1813 sc->sc_dp += n; 1814 sc->sc_dleft -= n; 1815 continue; 1816 case COMMAND_PHASE: 1817 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1818 if (acb->dleft) { 1819 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1820 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1821 sc->sc_phase = DATA_IN_PHASE; 1822 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1823 sc->sc_dp += n; 1824 sc->sc_dleft -= n; 1825 } 1826 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1827 sc->sc_phase = DATA_OUT_PHASE; 1828 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1829 sc->sc_dp += n; 1830 sc->sc_dleft -= n; 1831 } 1832 continue; 1833 } 1834 else { 1835 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1836 WAIT; 1837 sc->sc_phase = STATUS_PHASE; 1838 CMR = CMD_RECEIVE_STS; /* receive sts */ 1839 continue; 1840 } 1841 } 1842 #endif 1843 } 1844 continue; 1845 case 0x31: /* disconnected in xfer progress. */ 1846 SPC_MISC(("[0x31]")); 1847 case 0x70: /* disconnected. */ 1848 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1849 sc->sc_phase = BUSFREE_PHASE; 1850 sc->sc_state = SPC_IDLE; 1851 #if 1 1852 acb = sc->sc_nexus; 1853 SPC_ASSERT(sc->sc_nexus != NULL); 1854 acb->xs->error = XS_NOERROR; 1855 mha_done(sc, acb); 1856 #else 1857 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1858 mha_sched(sc); 1859 #endif 1860 continue; 1861 case 0x32: /* phase error in xfer progress. */ 1862 SPC_MISC(("[0x32]")); 1863 #if 0 1864 case 0x65: /* invalid command. 1865 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1866 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1867 #if 1 1868 SPC_MISC(("[0x%04x]", r)); 1869 #endif 1870 #endif 1871 case 0x54: /* initial-phase error. */ 1872 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1873 NSR, 1874 SCR, sc->sc_phase)); 1875 /* thru */ 1876 case 0x71: /* assert req */ 1877 WAIT; 1878 if (SSR & 0x40) { 1879 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1880 SSR, r, NSR, SCR); 1881 WAIT; 1882 } 1883 ph = SCR; 1884 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1885 sc->sc_state = SPC_HASNEXUS; 1886 } 1887 if (ph & 0x80) { 1888 switch (ph & PHASE_MASK) { 1889 default: 1890 printf("phase = %x\n", ph); 1891 panic("assert req: the phase I don't know!"); 1892 case DATA_IN_PHASE: 1893 sc->sc_prevphase = DATA_IN_PHASE; 1894 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1895 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1896 sc->sc_dp += n; 1897 sc->sc_dleft -= n; 1898 SPC_MISC(("done\n")); 1899 continue; 1900 case DATA_OUT_PHASE: 1901 sc->sc_prevphase = DATA_OUT_PHASE; 1902 SPC_MISC(("DATAOUT\n")); 1903 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1904 sc->sc_dp += n; 1905 sc->sc_dleft -= n; 1906 continue; 1907 case STATUS_PHASE: 1908 sc->sc_phase = STATUS_PHASE; 1909 SPC_MISC(("[RECV_STS]")); 1910 WAIT; 1911 CMR = CMD_RECEIVE_STS; /* receive sts */ 1912 continue; 1913 case MESSAGE_IN_PHASE: 1914 sc->sc_phase = MESSAGE_IN_PHASE; 1915 WAIT; 1916 CMR = CMD_RECEIVE_MSG; 1917 continue; 1918 } 1919 } 1920 continue; 1921 } 1922 } 1923 1924 return 1; 1925 } 1926 1927 void 1928 mha_abort(struct mha_softc *sc, struct acb *acb) 1929 { 1930 acb->flags |= ACB_ABORTED; 1931 1932 if (acb == sc->sc_nexus) { 1933 /* 1934 * If we're still selecting, the message will be scheduled 1935 * after selection is complete. 1936 */ 1937 if (sc->sc_state == SPC_HASNEXUS) { 1938 sc->sc_flags |= SPC_ABORTING; 1939 mha_sched_msgout(SEND_ABORT); 1940 } 1941 } else { 1942 if (sc->sc_state == SPC_IDLE) 1943 mha_sched(sc); 1944 } 1945 } 1946 1947 void 1948 mha_timeout(void *arg) 1949 { 1950 struct acb *acb = (struct acb *)arg; 1951 struct scsipi_xfer *xs = acb->xs; 1952 struct scsipi_periph *periph = xs->xs_periph; 1953 struct mha_softc *sc = 1954 (void *)periph->periph_channel->chan_adapter->adapt_dev; 1955 int s; 1956 1957 s = splbio(); 1958 1959 scsipi_printaddr(periph); 1960 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 1961 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 1962 sc->sc_dev.dv_xname, 1963 acb, acb->flags, acb->dleft, acb->stat, 1964 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 1965 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 1966 ); 1967 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 1968 panic("timeout, ouch!"); 1969 1970 if (acb->flags & ACB_ABORTED) { 1971 /* abort timed out */ 1972 printf(" AGAIN\n"); 1973 #if 0 1974 mha_init(sc, 1); /* XXX 1?*/ 1975 #endif 1976 } else { 1977 /* abort the operation that has timed out */ 1978 printf("\n"); 1979 xs->error = XS_TIMEOUT; 1980 mha_abort(sc, acb); 1981 } 1982 1983 splx(s); 1984 } 1985 1986 #if SPC_DEBUG 1987 /* 1988 * The following functions are mostly used for debugging purposes, either 1989 * directly called from the driver or from the kernel debugger. 1990 */ 1991 1992 void 1993 mha_show_scsi_cmd(struct acb *acb) 1994 { 1995 u_char *b = (u_char *)&acb->cmd; 1996 struct scsipi_periph *periph = acb->xs->xs_periph; 1997 int i; 1998 1999 scsipi_printaddr(periph); 2000 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2001 for (i = 0; i < acb->clen; i++) { 2002 if (i) 2003 printf(","); 2004 printf("%x", b[i]); 2005 } 2006 printf("\n"); 2007 } else 2008 printf("RESET\n"); 2009 } 2010 2011 void 2012 mha_print_acb(struct acb *acb) 2013 { 2014 2015 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2016 printf(" dp=%p dleft=%d stat=%x\n", 2017 acb->daddr, acb->dleft, acb->stat); 2018 mha_show_scsi_cmd(acb); 2019 } 2020 2021 void 2022 mha_print_active_acb(void) 2023 { 2024 struct acb *acb; 2025 struct mha_softc *sc = device_lookup_private(&mha_cd, 0); /* XXX */ 2026 2027 printf("ready list:\n"); 2028 for (acb = sc->ready_list.tqh_first; acb != NULL; 2029 acb = acb->chain.tqe_next) 2030 mha_print_acb(acb); 2031 printf("nexus:\n"); 2032 if (sc->sc_nexus != NULL) 2033 mha_print_acb(sc->sc_nexus); 2034 printf("nexus list:\n"); 2035 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2036 acb = acb->chain.tqe_next) 2037 mha_print_acb(acb); 2038 } 2039 2040 void 2041 mha_dump_driver(struct mha_softc *sc) 2042 { 2043 struct spc_tinfo *ti; 2044 int i; 2045 2046 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2047 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2048 sc->sc_state, sc->sc_imess[0], 2049 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2050 for (i = 0; i < 7; i++) { 2051 ti = &sc->sc_tinfo[i]; 2052 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2053 i, ti->cmds, ti->dconns, ti->touts); 2054 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2055 } 2056 } 2057 #endif 2058