xref: /netbsd-src/sys/arch/x68k/dev/intiovar.h (revision 1e72df6a037fdd3c6d3014a2679ffff7daab84ca)
1*1e72df6aStsutsui /*	$NetBSD: intiovar.h,v 1.15 2019/12/15 16:48:26 tsutsui Exp $	*/
2ba80d2c6Sminoura 
3ba80d2c6Sminoura /*
4ba80d2c6Sminoura  *
5ba80d2c6Sminoura  * Copyright (c) 1998 NetBSD Foundation, Inc.
6ba80d2c6Sminoura  * All rights reserved.
7ba80d2c6Sminoura  *
8ba80d2c6Sminoura  * Redistribution and use in source and binary forms, with or without
9ba80d2c6Sminoura  * modification, are permitted provided that the following conditions
10ba80d2c6Sminoura  * are met:
11ba80d2c6Sminoura  * 1. Redistributions of source code must retain the above copyright
12ba80d2c6Sminoura  *    notice, this list of conditions and the following disclaimer.
13ba80d2c6Sminoura  * 2. Redistributions in binary form must reproduce the above copyright
14ba80d2c6Sminoura  *    notice, this list of conditions and the following disclaimer in the
15ba80d2c6Sminoura  *    documentation and/or other materials provided with the distribution.
16ba80d2c6Sminoura  *
172a71e2c1Sminoura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
182a71e2c1Sminoura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
192a71e2c1Sminoura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
202a71e2c1Sminoura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
212a71e2c1Sminoura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
222a71e2c1Sminoura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
232a71e2c1Sminoura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
242a71e2c1Sminoura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
252a71e2c1Sminoura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
262a71e2c1Sminoura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
272a71e2c1Sminoura  * POSSIBILITY OF SUCH DAMAGE.
28ba80d2c6Sminoura  */
29ba80d2c6Sminoura 
30ba80d2c6Sminoura /*
31ba80d2c6Sminoura  * NetBSD/x68k internal I/O virtual bus.
32ba80d2c6Sminoura  */
33ba80d2c6Sminoura 
34ba80d2c6Sminoura #ifndef _INTIOVAR_H_
35ba80d2c6Sminoura #define _INTIOVAR_H_
36ba80d2c6Sminoura 
37ba80d2c6Sminoura #include <machine/frame.h>
38ba80d2c6Sminoura #include <sys/malloc.h>
39ba80d2c6Sminoura #include <sys/extent.h>
40ba80d2c6Sminoura #include "locators.h"
41ba80d2c6Sminoura 
42ba80d2c6Sminoura #define cf_addr		cf_loc[INTIOCF_ADDR]
43ba80d2c6Sminoura #define cf_intr		cf_loc[INTIOCF_INTR]
44ba80d2c6Sminoura #define cf_dma		cf_loc[INTIOCF_DMA]
45ba80d2c6Sminoura #define cf_dmaintr	cf_loc[INTIOCF_DMAINTR]
46ba80d2c6Sminoura 
47ba80d2c6Sminoura 
48ba80d2c6Sminoura struct intio_attach_args {
49ba80d2c6Sminoura 	bus_space_tag_t	ia_bst;	/* bus_space tag */
50ba80d2c6Sminoura 	bus_dma_tag_t	ia_dmat; /* bus_dma tag */
51ba80d2c6Sminoura 
522a8a7954Sisaki 	const char	*ia_name; /* device name */
53ba80d2c6Sminoura 	int		ia_addr; /* addr */
54ba80d2c6Sminoura 	int		ia_size;
55ba80d2c6Sminoura 	int		ia_intr; /* interrupt vector */
56ba80d2c6Sminoura 	int		ia_dma;	/* dma channel */
57ba80d2c6Sminoura 	int		ia_dmaintr; /* interrupt vector for dmac */
58ba80d2c6Sminoura };
59ba80d2c6Sminoura 
60ba80d2c6Sminoura struct intio_softc {
61ba80d2c6Sminoura 	bus_space_tag_t	sc_bst;
62ba80d2c6Sminoura 	bus_dma_tag_t	sc_dmat;
63ba80d2c6Sminoura 	struct extent	*sc_map;
642830b81aSisaki 	device_t	sc_dmac;
65ba80d2c6Sminoura };
66ba80d2c6Sminoura 
67ba80d2c6Sminoura enum intio_map_flag {
68ba80d2c6Sminoura 	INTIO_MAP_ALLOCATE = 0,
69ba80d2c6Sminoura 	INTIO_MAP_TESTONLY = 1
70ba80d2c6Sminoura };
712830b81aSisaki int intio_map_allocate_region(device_t, struct intio_attach_args *,
72d57ca0cfSchs 	enum intio_map_flag);
732830b81aSisaki int intio_map_free_region(device_t, struct intio_attach_args *);
74ba80d2c6Sminoura 
75d57ca0cfSchs typedef int (*intio_intr_handler_t)(void *);
76ba80d2c6Sminoura 
77d57ca0cfSchs int intio_intr_establish(int, const char *, intio_intr_handler_t, void *);
78af8a8d96Sisaki int intio_intr_establish_ext(int, const char *, const char *,
79af8a8d96Sisaki 	intio_intr_handler_t, void *);
80d57ca0cfSchs int intio_intr_disestablish(int, void *);
81d57ca0cfSchs int intio_intr(struct frame *);
82ba80d2c6Sminoura 
83ba80d2c6Sminoura 
84ba80d2c6Sminoura #define INTIO_SYSPORT		(0x00e8e000)
853b878f89Sisaki #define intio_sysport		((volatile uint8_t *)IIOV(INTIO_SYSPORT))
86ba80d2c6Sminoura #define sysport_contrast	1
87ba80d2c6Sminoura #define sysport_tvctrl		3
88ba80d2c6Sminoura #define sysport_imageunit	5
89ba80d2c6Sminoura #define sysport_keyctrl		7
90ba80d2c6Sminoura #define sysport_waitctrl	9
91ba80d2c6Sminoura #define sysport_mpustat		11
92ba80d2c6Sminoura #define sysport_sramwp		13
93ba80d2c6Sminoura #define sysport_powoff		15
94ba80d2c6Sminoura 
95ba80d2c6Sminoura #define intio_set_sysport_contrast(a) \
96ba80d2c6Sminoura 	intio_sysport[sysport_contrast] = (a) /* 0-15 */
97ba80d2c6Sminoura #define intio_set_sysport_tvctrl(a) \
98ba80d2c6Sminoura 	intio_sysport[sysport_tvctrl] = (a)
99ba80d2c6Sminoura #define INTIO_SYSPORT_TVCTRL	0x08
100ba80d2c6Sminoura #define intio_set_sysport_imageunit(a) \
101ba80d2c6Sminoura 	intio_sysport[sysport_imageunit] = (a)
102ba80d2c6Sminoura #define intio_set_sysport_keyctrl(a) \
103ba80d2c6Sminoura 	intio_sysport[sysport_keyctrl] = (a)
104ba80d2c6Sminoura #define INTIO_SYSPORT_KBENABLE	0x08
105ba80d2c6Sminoura #define intio_set_sysport_waitctrl(a) \
106ba80d2c6Sminoura 	intio_sysport[sysport_waitctrl] = (a) /* X68030 only */
107ba80d2c6Sminoura #define intio_set_sysport_sramwp(a) \
108ba80d2c6Sminoura 	intio_sysport[sysport_sramwp] = (a)
109ba80d2c6Sminoura #define INTIO_SYSPORT_SRAMWP	0x31
110ba80d2c6Sminoura #define intio_set_sysport_powoff(a) \
111ba80d2c6Sminoura 	intio_sysport[sysport_powoff] = (a)
112ba80d2c6Sminoura 
113ba80d2c6Sminoura #define intio_get_sysport_contrast() \
114ba80d2c6Sminoura 	(intio_sysport[sysport_contrast])
115ba80d2c6Sminoura #define intio_get_sysport_tvctrl() \
116ba80d2c6Sminoura 	(intio_sysport[sysport_tvctrl])
117ba80d2c6Sminoura #define INTIO_SYSPORT_TVSTAT	0x08
118ba80d2c6Sminoura #define intio_get_sysport_keyctrl() \
119ba80d2c6Sminoura 	(intio_sysport[sysport_keyctrl])
120ba80d2c6Sminoura #define INTIO_SYSPORT_KBEXIST	0x08
121ba80d2c6Sminoura #define intio_get_sysport_waitctrl() \
122ba80d2c6Sminoura 	(intio_sysport[sysport_waitctrl])
12350aab03cSisaki #define intio_get_sysport_sramwp() \
12450aab03cSisaki 	(intio_sysport[sysport_sramwp])
125ba80d2c6Sminoura #define intio_get_sysport_mpustat() \
126ba80d2c6Sminoura 	(intio_sysport[sysport_mpustat])
127ba80d2c6Sminoura 
128a5bf3b3cSwiz /* I/O controller (sicilian/pluto) */
129ba80d2c6Sminoura #define INTIO_SICILIAN		(0x00e9c000)
1303b878f89Sisaki #define intio_sicilian		((volatile uint8_t *)IIOV(INTIO_SICILIAN))
131ba80d2c6Sminoura #define sicilian_intr		1
132ba80d2c6Sminoura #define sicilian_ivec		3
133ba80d2c6Sminoura 
134ba80d2c6Sminoura #define intio_get_sicilian_intr() \
135ba80d2c6Sminoura 	(intio_sicilian[sicilian_intr])
136ba80d2c6Sminoura #define intio_set_sicilian_intr(a) \
137ba80d2c6Sminoura 	intio_sicilian[sicilian_intr] = (a)
138ba80d2c6Sminoura #define SICILIAN_INTR_PAR 0x01
139ba80d2c6Sminoura #define SICILIAN_INTR_FDD 0x02
140ba80d2c6Sminoura #define SICILIAN_INTR_FDC 0x04
141ba80d2c6Sminoura #define SICILIAN_INTR_HDD 0x08
142ba80d2c6Sminoura #define SICILIAN_STAT_HDD 0x10
143ba80d2c6Sminoura #define SICILIAN_STAT_PAR 0x20
144ba80d2c6Sminoura #define SICILIAN_STAT_FDD 0x40
145ba80d2c6Sminoura #define SICILIAN_STAT_FDC 0x80
146ba80d2c6Sminoura 
147ba80d2c6Sminoura #define intio_enable_intr(a) \
148ba80d2c6Sminoura 	intio_sicilian[sicilian_intr] = ((a) | intio_sicilian[sicilian_intr])
149ba80d2c6Sminoura #define intio_disable_intr(a) \
150ba80d2c6Sminoura 	intio_sicilian[sicilian_intr] = (~(a) & intio_sicilian[sicilian_intr])
151ba80d2c6Sminoura 
152ba80d2c6Sminoura #define intio_set_sicilian_ivec(a) \
153ba80d2c6Sminoura 	intio_sicilian[sicilian_ivec] = (a)
154d57ca0cfSchs void intio_set_ivec(int);
155ba80d2c6Sminoura 
156ba80d2c6Sminoura struct intio_dma_cookie {
157ba80d2c6Sminoura 	int	id_flags;		/* flags; see below */
158ba80d2c6Sminoura 
159ba80d2c6Sminoura 	/*
160ba80d2c6Sminoura 	 * Information about the original buffer used during
161ba80d2c6Sminoura 	 * DMA map syncs.  Note that origibuflen is only used
162ba80d2c6Sminoura 	 * for ID_BUFTYPE_LINEAR.
163ba80d2c6Sminoura 	 */
164ba80d2c6Sminoura 	void	*id_origbuf;		/* pointer to orig buffer if
165ba80d2c6Sminoura 					   bouncing */
166ba80d2c6Sminoura 	bus_size_t id_origbuflen;	/* ...and size */
167ba80d2c6Sminoura 	int	id_buftype;		/* type of buffer */
168ba80d2c6Sminoura 
169ba80d2c6Sminoura 	void	*id_bouncebuf;		/* pointer to the bounce buffer */
170ba80d2c6Sminoura 	bus_size_t id_bouncebuflen;	/* ...and size */
171ba80d2c6Sminoura 	int	id_nbouncesegs;		/* number of valid bounce segs */
172ba80d2c6Sminoura 	bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer
173ba80d2c6Sminoura 					       physical memory segments */
174ba80d2c6Sminoura };
175ba80d2c6Sminoura 
176ba80d2c6Sminoura /* id_flags */
177ba80d2c6Sminoura #define	ID_MIGHT_NEED_BOUNCE	0x01	/* map could need bounce buffers */
178ba80d2c6Sminoura #define	ID_HAS_BOUNCE		0x02	/* map currently has bounce buffers */
179ba80d2c6Sminoura #define	ID_IS_BOUNCING		0x04	/* map is bouncing current xfer */
180ba80d2c6Sminoura 
181ba80d2c6Sminoura /* id_buftype */
182ba80d2c6Sminoura #define	ID_BUFTYPE_INVALID	0
183ba80d2c6Sminoura #define	ID_BUFTYPE_LINEAR	1
184ba80d2c6Sminoura #define	ID_BUFTYPE_MBUF		2
185ba80d2c6Sminoura #define	ID_BUFTYPE_UIO		3
186ba80d2c6Sminoura #define	ID_BUFTYPE_RAW		4
187ba80d2c6Sminoura 
188ba80d2c6Sminoura #endif
189