xref: /netbsd-src/sys/arch/x68k/dev/dmacvar.h (revision ac90edd39294ab80fad71d7779b34375501a00e4)
1*ac90edd3Sisaki /*	$NetBSD: dmacvar.h,v 1.12 2017/08/11 07:30:01 isaki Exp $	*/
2ba80d2c6Sminoura 
3ba80d2c6Sminoura /*-
4ba80d2c6Sminoura  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5ba80d2c6Sminoura  * All rights reserved.
6ba80d2c6Sminoura  *
7ba80d2c6Sminoura  * This code is derived from software contributed to The NetBSD Foundation
8ba80d2c6Sminoura  * by Minoura Makoto.
9ba80d2c6Sminoura  *
10ba80d2c6Sminoura  * Redistribution and use in source and binary forms, with or without
11ba80d2c6Sminoura  * modification, are permitted provided that the following conditions
12ba80d2c6Sminoura  * are met:
13ba80d2c6Sminoura  * 1. Redistributions of source code must retain the above copyright
14ba80d2c6Sminoura  *    notice, this list of conditions and the following disclaimer.
15ba80d2c6Sminoura  * 2. Redistributions in binary form must reproduce the above copyright
16ba80d2c6Sminoura  *    notice, this list of conditions and the following disclaimer in the
17ba80d2c6Sminoura  *    documentation and/or other materials provided with the distribution.
18ba80d2c6Sminoura  *
19ba80d2c6Sminoura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20ba80d2c6Sminoura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21ba80d2c6Sminoura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22ba80d2c6Sminoura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23ba80d2c6Sminoura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24ba80d2c6Sminoura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25ba80d2c6Sminoura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26ba80d2c6Sminoura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27ba80d2c6Sminoura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28ba80d2c6Sminoura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29ba80d2c6Sminoura  * POSSIBILITY OF SUCH DAMAGE.
30ba80d2c6Sminoura  */
31ba80d2c6Sminoura 
32ba80d2c6Sminoura /*
33ba80d2c6Sminoura  * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k.
34ba80d2c6Sminoura  */
35ba80d2c6Sminoura 
36ba80d2c6Sminoura #include <dev/ic/mc68450reg.h>
37fc97cb8aSminoura #include <machine/bus.h>
38ba80d2c6Sminoura 
39fc97cb8aSminoura #define DMAC_MAPSIZE 64
40ba80d2c6Sminoura 
41d57ca0cfSchs typedef int (*dmac_intr_handler_t)(void *);
42ba80d2c6Sminoura 
43ba80d2c6Sminoura /*
44fc97cb8aSminoura  * Structure that describes a single transfer.
45fc97cb8aSminoura  */
46fc97cb8aSminoura struct dmac_channel_stat;
47fc97cb8aSminoura struct dmac_dma_xfer {
48fc97cb8aSminoura 	struct dmac_channel_stat *dx_channel;
49fc97cb8aSminoura 	bus_dmamap_t	dx_dmamap;	/* dmamap tag */
50fc97cb8aSminoura 	bus_dma_tag_t	dx_tag;		/* dma tag for the transfer */
51fc97cb8aSminoura 	int		dx_ocr;		/* direction */
52fc97cb8aSminoura 	int		dx_scr;		/* SCR value */
53fc97cb8aSminoura 	void		*dx_device;	/* (initial) device address */
5447d22455Sminoura #ifdef DMAC_ARRAYCHAIN
55fc97cb8aSminoura 	struct dmac_sg_array *dx_array;	/* DMAC array chain */
56fc97cb8aSminoura 	int		dx_done;
5747d22455Sminoura #endif
58fc97cb8aSminoura };
59fc97cb8aSminoura 
60fc97cb8aSminoura /*
61ba80d2c6Sminoura  * Struct that holds the channel status.
62ba80d2c6Sminoura  * Embedded in the device softc for each channel.
63ba80d2c6Sminoura  */
64ba80d2c6Sminoura struct dmac_channel_stat {
65ba80d2c6Sminoura 	int			ch_channel; /* channel number */
66ba80d2c6Sminoura 	char			ch_name[8]; /* user device name */
67ba80d2c6Sminoura 	bus_space_handle_t	ch_bht;	/* bus_space handle */
68ba80d2c6Sminoura 	int			ch_dcr;	/* device description */
69ba80d2c6Sminoura 	int			ch_ocr;	/* operation size, request mode */
70ba80d2c6Sminoura 	int			ch_normalv; /* normal interrupt vector */
71ba80d2c6Sminoura 	int			ch_errorv; /* error interrupt vector */
72ba80d2c6Sminoura 	dmac_intr_handler_t	ch_normal; /* normal interrupt handler */
73ba80d2c6Sminoura 	dmac_intr_handler_t	ch_error; /* error interrupt handler */
74ba80d2c6Sminoura 	void			*ch_normalarg;
75ba80d2c6Sminoura 	void			*ch_errorarg;
76fc97cb8aSminoura 	struct dmac_dma_xfer	ch_xfer;
77fc97cb8aSminoura 	struct dmac_sg_array	*ch_map; /* transfer map for arraychain mode */
78fc97cb8aSminoura 	bus_dma_segment_t	ch_seg[1];
79b50b2ac3Sisaki 	struct dmac_softc	*ch_softc; /* device softc link */
80ba80d2c6Sminoura };
81ba80d2c6Sminoura 
82ba80d2c6Sminoura /*
83ba80d2c6Sminoura  * DMAC softc
84ba80d2c6Sminoura  */
85ba80d2c6Sminoura struct dmac_softc {
862830b81aSisaki 	device_t		sc_dev;
87ba80d2c6Sminoura 
88ba80d2c6Sminoura 	bus_space_tag_t		sc_bst;
89ba80d2c6Sminoura 	bus_space_handle_t	sc_bht;
90ba80d2c6Sminoura 
91ba80d2c6Sminoura 	struct dmac_channel_stat sc_channels[DMAC_NCHAN];
92ba80d2c6Sminoura };
93ba80d2c6Sminoura 
94ba80d2c6Sminoura 
95ba80d2c6Sminoura #define DMAC_ADDR	0xe84000
96ba80d2c6Sminoura 
97ba80d2c6Sminoura #define DMAC_MAXSEGSZ	0xff00
98ba80d2c6Sminoura #define DMAC_BOUNDARY	0
99ba80d2c6Sminoura 
100f5c75e2eSisaki struct dmac_channel_stat *dmac_alloc_channel(device_t,
101f5c75e2eSisaki 	int,		/* ch */
102f5c75e2eSisaki 	const char *,	/* name */
103f5c75e2eSisaki 	int, dmac_intr_handler_t, void *,	/* normal handler */
104f5c75e2eSisaki 	int, dmac_intr_handler_t, void *,	/* error handler */
105f5c75e2eSisaki 	uint8_t,	/* dcr */
106f5c75e2eSisaki 	uint8_t		/* ocr */
107f5c75e2eSisaki );
1082830b81aSisaki int dmac_free_channel(device_t, int, void *);
109ba80d2c6Sminoura 		/* ch, channel */
110d57ca0cfSchs struct dmac_dma_xfer *dmac_alloc_xfer(struct dmac_channel_stat *,
111d57ca0cfSchs 	bus_dma_tag_t, bus_dmamap_t);
112b50b2ac3Sisaki int dmac_load_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
11347d22455Sminoura 
114b50b2ac3Sisaki int dmac_start_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
115b50b2ac3Sisaki int dmac_start_xfer_offset(struct dmac_softc *, struct dmac_dma_xfer *,
116b50b2ac3Sisaki 	u_int, u_int);
117b50b2ac3Sisaki int dmac_abort_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
11847d22455Sminoura /* Compatibility function: alloc, fill defaults, load */
119d57ca0cfSchs struct dmac_dma_xfer *dmac_prepare_xfer(struct dmac_channel_stat *,
120d57ca0cfSchs 	bus_dma_tag_t, bus_dmamap_t, int, int, void *);
121ba80d2c6Sminoura 	/* chan, dmat, map, dir, sequence, dar */
122