1 /* $NetBSD: bus.h,v 1.35 2019/09/24 14:26:32 maya Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _VAX_BUS_H_ 65 #define _VAX_BUS_H_ 66 67 #ifdef BUS_SPACE_DEBUG 68 #include <sys/systm.h> /* for printf() prototype */ 69 /* 70 * Macros for sanity-checking the aligned-ness of pointers passed to 71 * bus space ops. These are not strictly necessary on the VAX, but 72 * could lead to performance improvements, and help catch problems 73 * with drivers that would creep up on other architectures. 74 */ 75 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 76 ((((u_long)(p)) & (sizeof(t)-1)) == 0) 77 78 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 79 ({ \ 80 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 81 printf("%s 0x%lx not aligned to %d bytes %s:%d\n", \ 82 d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \ 83 } \ 84 (void) 0; \ 85 }) 86 87 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 88 #else 89 #define __BUS_SPACE_ADDRESS_SANITY(p,t,d) (void) 0 90 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 91 #endif /* BUS_SPACE_DEBUG */ 92 93 /* 94 * Bus address and size types 95 */ 96 typedef paddr_t bus_addr_t; 97 typedef psize_t bus_size_t; 98 99 #define PRIxBUSADDR PRIxPADDR 100 #define PRIxBUSSIZE PRIxPSIZE 101 #define PRIuBUSSIZE PRIuPSIZE 102 /* 103 * Access methods for bus resources and address space. 104 */ 105 typedef struct vax_bus_space *bus_space_tag_t; 106 typedef vaddr_t bus_space_handle_t; 107 108 #define PRIxBSH PRIxVADDR 109 110 struct vax_bus_space { 111 /* cookie */ 112 void *vbs_cookie; 113 114 /* mapping/unmapping */ 115 int (*vbs_map)(void *, bus_addr_t, bus_size_t, int, 116 bus_space_handle_t *, int); 117 void (*vbs_unmap)(void *, bus_space_handle_t, bus_size_t, 118 int); 119 int (*vbs_subregion)(void *, bus_space_handle_t, bus_size_t, 120 bus_size_t, bus_space_handle_t *); 121 122 /* allocation/deallocation */ 123 int (*vbs_alloc)(void *, bus_addr_t, bus_addr_t, bus_size_t, 124 bus_size_t, bus_size_t, int, bus_addr_t *, 125 bus_space_handle_t *); 126 void (*vbs_free)(void *, bus_space_handle_t, bus_size_t); 127 /* mmap bus space for user */ 128 paddr_t (*vbs_mmap)(void *, bus_addr_t, off_t, int, int); 129 }; 130 131 /* 132 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 133 * bus_size_t size, int flags, bus_space_handle_t *bshp); 134 * 135 * Map a region of bus space. 136 */ 137 138 #define BUS_SPACE_MAP_CACHEABLE 0x01 139 #define BUS_SPACE_MAP_LINEAR 0x02 140 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 141 142 #define bus_space_map(t, a, s, f, hp) \ 143 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 1) 144 #define vax_bus_space_map_noacct(t, a, s, f, hp) \ 145 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 0) 146 147 /* 148 * int bus_space_unmap(bus_space_tag_t t, 149 * bus_space_handle_t bsh, bus_size_t size); 150 * 151 * Unmap a region of bus space. 152 */ 153 154 #define bus_space_unmap(t, h, s) \ 155 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 1) 156 #define vax_bus_space_unmap_noacct(t, h, s) \ 157 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 0) 158 159 /* 160 * int bus_space_subregion(bus_space_tag_t t, 161 * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, 162 * bus_space_handle_t *nbshp); 163 * 164 * Get a new handle for a subregion of an already-mapped area of bus space. 165 */ 166 167 #define bus_space_subregion(t, h, o, s, nhp) \ 168 (*(t)->vbs_subregion)((t)->vbs_cookie, (h), (o), (s), (nhp)) 169 170 /* 171 * int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, 172 * bus_addr_t rend, bus_size_t size, bus_size_t align, 173 * bus_size_t boundary, int flags, bus_addr_t *addrp, 174 * bus_space_handle_t *bshp); 175 * 176 * Allocate a region of bus space. 177 */ 178 179 #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \ 180 (*(t)->vbs_alloc)((t)->vbs_cookie, (rs), (re), (s), (a), (b), \ 181 (f), (ap), (hp)) 182 183 /* 184 * int bus_space_free(bus_space_tag_t t, 185 * bus_space_handle_t bsh, bus_size_t size); 186 * 187 * Free a region of bus space. 188 */ 189 190 #define bus_space_free(t, h, s) \ 191 (*(t)->vbs_free)((t)->vbs_cookie, (h), (s)) 192 /* 193 * Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR. 194 */ 195 #define bus_space_vaddr(t, h) \ 196 ((void *) (h)) 197 /* 198 * Mmap bus space for a user application. 199 */ 200 #define bus_space_mmap(t, a, o, p, f) \ 201 (*(t)->vbs_mmap)((t)->vbs_cookie, (a), (o), (p), (f)) 202 203 204 /* 205 * u_intN_t bus_space_read_N(bus_space_tag_t tag, 206 * bus_space_handle_t bsh, bus_size_t offset); 207 * 208 * Read a 1, 2, 4, or 8 byte quantity from bus space 209 * described by tag/handle/offset. 210 */ 211 212 #define bus_space_read_1(t, h, o) \ 213 (__USE(t), (*(volatile uint8_t *)((h) + (o)))) 214 215 #define bus_space_read_2(t, h, o) \ 216 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"), \ 217 __USE(t), (*(volatile uint16_t *)((h) + (o)))) 218 219 #define bus_space_read_4(t, h, o) \ 220 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"), \ 221 __USE(t), (*(volatile uint32_t *)((h) + (o)))) 222 223 #if 0 /* Cause a link error for bus_space_read_8 */ 224 #define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! 225 #endif 226 227 /* 228 * void bus_space_read_multi_N(bus_space_tag_t tag, 229 * bus_space_handle_t bsh, bus_size_t offset, 230 * u_intN_t *addr, size_t count); 231 * 232 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 233 * described by tag/handle/offset and copy into buffer provided. 234 */ 235 static __inline void 236 vax_mem_read_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 237 uint8_t *, size_t), 238 vax_mem_read_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 239 uint16_t *, size_t), 240 vax_mem_read_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 241 uint32_t *, size_t); 242 243 #define bus_space_read_multi_1(t, h, o, a, c) \ 244 vax_mem_read_multi_1((t), (h), (o), (a), (c)) 245 246 #define bus_space_read_multi_2(t, h, o, a, c) \ 247 do { \ 248 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \ 249 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 250 vax_mem_read_multi_2((t), (h), (o), (a), (c)); \ 251 } while (0) 252 253 #define bus_space_read_multi_4(t, h, o, a, c) \ 254 do { \ 255 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \ 256 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 257 vax_mem_read_multi_4((t), (h), (o), (a), (c)); \ 258 } while (0) 259 260 #if 0 /* Cause a link error for bus_space_read_multi_8 */ 261 #define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! 262 #endif 263 264 static __inline void 265 vax_mem_read_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 266 uint8_t *a, size_t c) 267 { 268 const bus_addr_t addr = h + o; 269 270 for (; c != 0; c--, a++) 271 *a = *(volatile uint8_t *)(addr); 272 } 273 274 static __inline void 275 vax_mem_read_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 276 uint16_t *a, size_t c) 277 { 278 const bus_addr_t addr = h + o; 279 280 for (; c != 0; c--, a++) 281 *a = *(volatile uint16_t *)(addr); 282 } 283 284 static __inline void 285 vax_mem_read_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 286 uint32_t *a, size_t c) 287 { 288 const bus_addr_t addr = h + o; 289 290 for (; c != 0; c--, a++) 291 *a = *(volatile uint32_t *)(addr); 292 } 293 294 /* 295 * void bus_space_read_region_N(bus_space_tag_t tag, 296 * bus_space_handle_t bsh, bus_size_t offset, 297 * u_intN_t *addr, size_t count); 298 * 299 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 300 * described by tag/handle and starting at `offset' and copy into 301 * buffer provided. 302 */ 303 304 static __inline void vax_mem_read_region_1(bus_space_tag_t, 305 bus_space_handle_t, bus_size_t, uint8_t *, size_t); 306 static __inline void vax_mem_read_region_2(bus_space_tag_t, 307 bus_space_handle_t, bus_size_t, uint16_t *, size_t); 308 static __inline void vax_mem_read_region_4(bus_space_tag_t, 309 bus_space_handle_t, bus_size_t, uint32_t *, size_t); 310 311 #define bus_space_read_region_1(t, h, o, a, c) \ 312 do { \ 313 vax_mem_read_region_1((t), (h), (o), (a), (c)); \ 314 } while (0) 315 316 #define bus_space_read_region_2(t, h, o, a, c) \ 317 do { \ 318 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \ 319 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 320 vax_mem_read_region_2((t), (h), (o), (a), (c)); \ 321 } while (0) 322 323 #define bus_space_read_region_4(t, h, o, a, c) \ 324 do { \ 325 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \ 326 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 327 vax_mem_read_region_4((t), (h), (o), (a), (c)); \ 328 } while (0) 329 330 #if 0 /* Cause a link error for bus_space_read_region_8 */ 331 #define bus_space_read_region_8 \ 332 !!! bus_space_read_region_8 unimplemented !!! 333 #endif 334 335 static __inline void 336 vax_mem_read_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 337 uint8_t *a, size_t c) 338 { 339 bus_addr_t addr = h + o; 340 341 for (; c != 0; c--, addr++, a++) 342 *a = *(volatile uint8_t *)(addr); 343 } 344 345 static __inline void 346 vax_mem_read_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 347 uint16_t *a, size_t c) 348 { 349 bus_addr_t addr = h + o; 350 351 for (; c != 0; c--, addr += 2, a++) 352 *a = *(volatile uint16_t *)(addr); 353 } 354 355 static __inline void 356 vax_mem_read_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 357 uint32_t *a, size_t c) 358 { 359 bus_addr_t addr = h + o; 360 361 for (; c != 0; c--, addr += 4, a++) 362 *a = *(volatile uint32_t *)(addr); 363 } 364 365 /* 366 * void bus_space_write_N(bus_space_tag_t tag, 367 * bus_space_handle_t bsh, bus_size_t offset, 368 * u_intN_t value); 369 * 370 * Write the 1, 2, 4, or 8 byte value `value' to bus space 371 * described by tag/handle/offset. 372 */ 373 374 #define bus_space_write_1(t, h, o, v) \ 375 do { \ 376 __USE(t); \ 377 ((void)(*(volatile uint8_t *)((h) + (o)) = (v))); \ 378 } while (0) 379 380 #define bus_space_write_2(t, h, o, v) \ 381 do { \ 382 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 383 __USE(t); \ 384 ((void)(*(volatile uint16_t *)((h) + (o)) = (v))); \ 385 } while (0) 386 387 #define bus_space_write_4(t, h, o, v) \ 388 do { \ 389 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 390 __USE(t); \ 391 ((void)(*(volatile uint32_t *)((h) + (o)) = (v))); \ 392 } while (0) 393 394 #if 0 /* Cause a link error for bus_space_write_8 */ 395 #define bus_space_write_8 !!! bus_space_write_8 not implemented !!! 396 #endif 397 398 /* 399 * void bus_space_write_multi_N(bus_space_tag_t tag, 400 * bus_space_handle_t bsh, bus_size_t offset, 401 * const u_intN_t *addr, size_t count); 402 * 403 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 404 * provided to bus space described by tag/handle/offset. 405 */ 406 static __inline void 407 vax_mem_write_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 408 const uint8_t *, size_t), 409 vax_mem_write_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 410 const uint16_t *, size_t), 411 vax_mem_write_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 412 const uint32_t *, size_t); 413 414 #define bus_space_write_multi_1(t, h, o, a, c) \ 415 do { \ 416 vax_mem_write_multi_1((t), (h), (o), (a), (c)); \ 417 } while (0) 418 419 #define bus_space_write_multi_2(t, h, o, a, c) \ 420 do { \ 421 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \ 422 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 423 vax_mem_write_multi_2((t), (h), (o), (a), (c)); \ 424 } while (0) 425 426 #define bus_space_write_multi_4(t, h, o, a, c) \ 427 do { \ 428 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \ 429 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 430 vax_mem_write_multi_4((t), (h), (o), (a), (c)); \ 431 } while (0) 432 433 #if 0 /* Cause a link error for bus_space_write_multi_8 */ 434 #define bus_space_write_multi_8(t, h, o, a, c) \ 435 !!! bus_space_write_multi_8 unimplemented !!! 436 #endif 437 438 static __inline void 439 vax_mem_write_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 440 const uint8_t *a, size_t c) 441 { 442 const bus_addr_t addr = h + o; 443 444 for (; c != 0; c--, a++) 445 *(volatile uint8_t *)(addr) = *a; 446 } 447 448 static __inline void 449 vax_mem_write_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 450 const uint16_t *a, size_t c) 451 { 452 const bus_addr_t addr = h + o; 453 454 for (; c != 0; c--, a++) 455 *(volatile uint16_t *)(addr) = *a; 456 } 457 458 static __inline void 459 vax_mem_write_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 460 const uint32_t *a, size_t c) 461 { 462 const bus_addr_t addr = h + o; 463 464 for (; c != 0; c--, a++) 465 *(volatile uint32_t *)(addr) = *a; 466 } 467 468 /* 469 * void bus_space_write_region_N(bus_space_tag_t tag, 470 * bus_space_handle_t bsh, bus_size_t offset, 471 * const u_intN_t *addr, size_t count); 472 * 473 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 474 * to bus space described by tag/handle starting at `offset'. 475 */ 476 static __inline void 477 vax_mem_write_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 478 const uint8_t *, size_t), 479 vax_mem_write_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 480 const uint16_t *, size_t), 481 vax_mem_write_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 482 const uint32_t *, size_t); 483 484 #define bus_space_write_region_1(t, h, o, a, c) \ 485 vax_mem_write_region_1((t), (h), (o), (a), (c)) 486 487 #define bus_space_write_region_2(t, h, o, a, c) \ 488 do { \ 489 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \ 490 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 491 vax_mem_write_region_2((t), (h), (o), (a), (c)); \ 492 } while (0) 493 494 #define bus_space_write_region_4(t, h, o, a, c) \ 495 do { \ 496 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \ 497 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 498 vax_mem_write_region_4((t), (h), (o), (a), (c)); \ 499 } while (0) 500 501 #if 0 /* Cause a link error for bus_space_write_region_8 */ 502 #define bus_space_write_region_8 \ 503 !!! bus_space_write_region_8 unimplemented !!! 504 #endif 505 506 static __inline void 507 vax_mem_write_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 508 const uint8_t *a, size_t c) 509 { 510 bus_addr_t addr = h + o; 511 512 for (; c != 0; c--, addr++, a++) 513 *(volatile uint8_t *)(addr) = *a; 514 } 515 516 static __inline void 517 vax_mem_write_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 518 const uint16_t *a, size_t c) 519 { 520 bus_addr_t addr = h + o; 521 522 for (; c != 0; c--, addr++, a++) 523 *(volatile uint16_t *)(addr) = *a; 524 } 525 526 static __inline void 527 vax_mem_write_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 528 const uint32_t *a, size_t c) 529 { 530 bus_addr_t addr = h + o; 531 532 for (; c != 0; c--, addr++, a++) 533 *(volatile uint32_t *)(addr) = *a; 534 } 535 536 /* 537 * void bus_space_set_multi_N(bus_space_tag_t tag, 538 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 539 * size_t count); 540 * 541 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 542 * by tag/handle/offset `count' times. 543 */ 544 545 static __inline void 546 vax_mem_set_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 547 uint8_t, size_t), 548 vax_mem_set_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 549 uint16_t, size_t), 550 vax_mem_set_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 551 uint32_t, size_t); 552 553 #define bus_space_set_multi_1(t, h, o, v, c) \ 554 vax_mem_set_multi_1((t), (h), (o), (v), (c)) 555 556 #define bus_space_set_multi_2(t, h, o, v, c) \ 557 do { \ 558 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 559 vax_mem_set_multi_2((t), (h), (o), (v), (c)); \ 560 } while (0) 561 562 #define bus_space_set_multi_4(t, h, o, v, c) \ 563 do { \ 564 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 565 vax_mem_set_multi_4((t), (h), (o), (v), (c)); \ 566 } while (0) 567 568 static __inline void 569 vax_mem_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 570 uint8_t v, size_t c) 571 { 572 bus_addr_t addr = h + o; 573 574 while (c--) 575 *(volatile uint8_t *)(addr) = v; 576 } 577 578 static __inline void 579 vax_mem_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 580 uint16_t v, size_t c) 581 { 582 bus_addr_t addr = h + o; 583 584 while (c--) 585 *(volatile uint16_t *)(addr) = v; 586 } 587 588 static __inline void 589 vax_mem_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 590 uint32_t v, size_t c) 591 { 592 bus_addr_t addr = h + o; 593 594 while (c--) 595 *(volatile uint32_t *)(addr) = v; 596 } 597 598 #if 0 /* Cause a link error for bus_space_set_multi_8 */ 599 #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 600 #endif 601 602 /* 603 * void bus_space_set_region_N(bus_space_tag_t tag, 604 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 605 * size_t count); 606 * 607 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 608 * by tag/handle starting at `offset'. 609 */ 610 611 static __inline void 612 vax_mem_set_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 613 uint8_t, size_t), 614 vax_mem_set_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 615 uint16_t, size_t), 616 vax_mem_set_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 617 uint32_t, size_t); 618 619 #define bus_space_set_region_1(t, h, o, v, c) \ 620 vax_mem_set_region_1((t), (h), (o), (v), (c)) 621 622 #define bus_space_set_region_2(t, h, o, v, c) \ 623 do { \ 624 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \ 625 vax_mem_set_region_2((t), (h), (o), (v), (c)); \ 626 } while (0) 627 628 #define bus_space_set_region_4(t, h, o, v, c) \ 629 do { \ 630 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \ 631 vax_mem_set_region_4((t), (h), (o), (v), (c)); \ 632 } while (0) 633 634 static __inline void 635 vax_mem_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 636 uint8_t v, size_t c) 637 { 638 bus_addr_t addr = h + o; 639 640 for (; c != 0; c--, addr++) 641 *(volatile uint8_t *)(addr) = v; 642 } 643 644 static __inline void 645 vax_mem_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 646 uint16_t v, size_t c) 647 { 648 bus_addr_t addr = h + o; 649 650 for (; c != 0; c--, addr += 2) 651 *(volatile uint16_t *)(addr) = v; 652 } 653 654 static __inline void 655 vax_mem_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, 656 uint32_t v, size_t c) 657 { 658 bus_addr_t addr = h + o; 659 660 for (; c != 0; c--, addr += 4) 661 *(volatile uint32_t *)(addr) = v; 662 } 663 664 #if 0 /* Cause a link error for bus_space_set_region_8 */ 665 #define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! 666 #endif 667 668 /* 669 * void bus_space_copy_region_N(bus_space_tag_t tag, 670 * bus_space_handle_t bsh1, bus_size_t off1, 671 * bus_space_handle_t bsh2, bus_size_t off2, 672 * size_t count); 673 * 674 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 675 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. 676 */ 677 678 static __inline void 679 vax_mem_copy_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t, 680 bus_space_handle_t, bus_size_t, size_t), 681 vax_mem_copy_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t, 682 bus_space_handle_t, bus_size_t, size_t), 683 vax_mem_copy_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, 684 bus_space_handle_t, bus_size_t, size_t); 685 686 #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ 687 vax_mem_copy_region_1((t), (h1), (o1), (h2), (o2), (c)) 688 689 #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ 690 do { \ 691 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), uint16_t, "bus addr 1"); \ 692 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), uint16_t, "bus addr 2"); \ 693 vax_mem_copy_region_2((t), (h1), (o1), (h2), (o2), (c)); \ 694 } while (0) 695 696 #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ 697 do { \ 698 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), uint32_t, "bus addr 1"); \ 699 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), uint32_t, "bus addr 2"); \ 700 vax_mem_copy_region_4((t), (h1), (o1), (h2), (o2), (c)); \ 701 } while (0) 702 703 static __inline void 704 vax_mem_copy_region_1(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1, 705 bus_space_handle_t h2, bus_size_t o2, size_t c) 706 { 707 bus_addr_t addr1 = h1 + o1; 708 bus_addr_t addr2 = h2 + o2; 709 710 if (addr1 >= addr2) { 711 /* src after dest: copy forward */ 712 for (; c != 0; c--, addr1++, addr2++) 713 *(volatile uint8_t *)(addr2) = 714 *(volatile uint8_t *)(addr1); 715 } else { 716 /* dest after src: copy backwards */ 717 for (addr1 += (c - 1), addr2 += (c - 1); 718 c != 0; c--, addr1--, addr2--) 719 *(volatile uint8_t *)(addr2) = 720 *(volatile uint8_t *)(addr1); 721 } 722 } 723 724 static __inline void 725 vax_mem_copy_region_2(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1, 726 bus_space_handle_t h2, bus_size_t o2, size_t c) 727 { 728 bus_addr_t addr1 = h1 + o1; 729 bus_addr_t addr2 = h2 + o2; 730 731 if (addr1 >= addr2) { 732 /* src after dest: copy forward */ 733 for (; c != 0; c--, addr1 += 2, addr2 += 2) 734 *(volatile uint16_t *)(addr2) = 735 *(volatile uint16_t *)(addr1); 736 } else { 737 /* dest after src: copy backwards */ 738 for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1); 739 c != 0; c--, addr1 -= 2, addr2 -= 2) 740 *(volatile uint16_t *)(addr2) = 741 *(volatile uint16_t *)(addr1); 742 } 743 } 744 745 static __inline void 746 vax_mem_copy_region_4(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1, 747 bus_space_handle_t h2, bus_size_t o2, size_t c) 748 { 749 bus_addr_t addr1 = h1 + o1; 750 bus_addr_t addr2 = h2 + o2; 751 752 if (addr1 >= addr2) { 753 /* src after dest: copy forward */ 754 for (; c != 0; c--, addr1 += 4, addr2 += 4) 755 *(volatile uint32_t *)(addr2) = 756 *(volatile uint32_t *)(addr1); 757 } else { 758 /* dest after src: copy backwards */ 759 for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1); 760 c != 0; c--, addr1 -= 4, addr2 -= 4) 761 *(volatile uint32_t *)(addr2) = 762 *(volatile uint32_t *)(addr1); 763 } 764 } 765 766 #if 0 /* Cause a link error for bus_space_copy_8 */ 767 #define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! 768 #endif 769 770 771 /* 772 * Bus read/write barrier methods. 773 * 774 * void bus_space_barrier(bus_space_tag_t tag, 775 * bus_space_handle_t bsh, bus_size_t offset, 776 * bus_size_t len, int flags); 777 * 778 * Note: the vax does not currently require barriers, but we must 779 * provide the flags to MI code. 780 */ 781 #define bus_space_barrier(t, h, o, l, f) \ 782 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f))) 783 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 784 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 785 786 787 /* 788 * Flags used in various bus DMA methods. 789 */ 790 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 791 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 792 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 793 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 794 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 795 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 796 #define BUS_DMA_BUS2 0x020 797 #define BUS_DMA_BUS3 0x040 798 #define BUS_DMA_BUS4 0x080 799 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 800 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 801 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 802 803 #define VAX_BUS_DMA_SPILLPAGE BUS_DMA_BUS1 /* VS4000 kludge */ 804 /* 805 * Private flags stored in the DMA map. 806 */ 807 #define DMAMAP_HAS_SGMAP 0x80000000 /* sgva/len are valid */ 808 809 /* Forwards needed by prototypes below. */ 810 struct mbuf; 811 struct uio; 812 struct vax_sgmap; 813 814 /* 815 * Operations performed by bus_dmamap_sync(). 816 */ 817 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 818 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 819 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 820 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 821 822 /* 823 * vax_bus_t 824 * 825 * Busses supported by NetBSD/vax, used by internal 826 * utility functions. NOT TO BE USED BY MACHINE-INDEPENDENT 827 * CODE! 828 */ 829 typedef enum { 830 VAX_BUS_MAINBUS, 831 VAX_BUS_SBI, 832 VAX_BUS_MASSBUS, 833 VAX_BUS_UNIBUS, /* Also handles QBUS */ 834 VAX_BUS_BI, 835 VAX_BUS_XMI, 836 VAX_BUS_TURBOCHANNEL 837 } vax_bus_t; 838 839 typedef struct vax_bus_dma_tag *bus_dma_tag_t; 840 typedef struct vax_bus_dmamap *bus_dmamap_t; 841 842 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 843 844 /* 845 * bus_dma_segment_t 846 * 847 * Describes a single contiguous DMA transaction. Values 848 * are suitable for programming into DMA registers. 849 */ 850 struct vax_bus_dma_segment { 851 bus_addr_t ds_addr; /* DMA address */ 852 bus_size_t ds_len; /* length of transfer */ 853 }; 854 typedef struct vax_bus_dma_segment bus_dma_segment_t; 855 856 struct proc; 857 858 /* 859 * bus_dma_tag_t 860 * 861 * A machine-dependent opaque type describing the implementation of 862 * DMA for a given bus. 863 */ 864 struct vax_bus_dma_tag { 865 void *_cookie; /* cookie used in the guts */ 866 bus_addr_t _wbase; /* DMA window base */ 867 bus_size_t _wsize; /* DMA window size */ 868 869 /* 870 * Some chipsets have a built-in boundary constraint, independent 871 * of what the device requests. This allows that boundary to 872 * be specified. If the device has a more restrictive constraint, 873 * the map will use that, otherwise this boundary will be used. 874 * This value is ignored if 0. 875 */ 876 bus_size_t _boundary; 877 878 /* 879 * A bus may have more than one SGMAP window, so SGMAP 880 * windows also get a pointer to their SGMAP state. 881 */ 882 struct vax_sgmap *_sgmap; 883 884 /* 885 * Internal-use only utility methods. NOT TO BE USED BY 886 * MACHINE-INDEPENDENT CODE! 887 */ 888 bus_dma_tag_t (*_get_tag)(bus_dma_tag_t, vax_bus_t); 889 890 /* 891 * DMA mapping methods. 892 */ 893 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 894 bus_size_t, bus_size_t, int, bus_dmamap_t *); 895 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 896 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 897 bus_size_t, struct proc *, int); 898 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 899 struct mbuf *, int); 900 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 901 struct uio *, int); 902 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 903 bus_dma_segment_t *, int, bus_size_t, int); 904 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 905 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 906 bus_addr_t, bus_size_t, int); 907 908 /* 909 * DMA memory utility functions. 910 */ 911 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 912 bus_size_t, bus_dma_segment_t *, int, int *, int); 913 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int); 914 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 915 int, size_t, void **, int); 916 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 917 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 918 int, off_t, int, int); 919 }; 920 921 #define vaxbus_dma_get_tag(t, b) \ 922 (*(t)->_get_tag)(t, b) 923 924 #define bus_dmamap_create(t, s, n, m, b, f, p) \ 925 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 926 #define bus_dmamap_destroy(t, p) \ 927 (*(t)->_dmamap_destroy)((t), (p)) 928 #define bus_dmamap_load(t, m, b, s, p, f) \ 929 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 930 #define bus_dmamap_load_mbuf(t, m, b, f) \ 931 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 932 #define bus_dmamap_load_uio(t, m, u, f) \ 933 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 934 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 935 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 936 #define bus_dmamap_unload(t, p) \ 937 (*(t)->_dmamap_unload)((t), (p)) 938 #define bus_dmamap_sync(t, p, o, l, ops) \ 939 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) 940 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 941 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 942 #define bus_dmamem_free(t, sg, n) \ 943 (*(t)->_dmamem_free)((t), (sg), (n)) 944 #define bus_dmamem_map(t, sg, n, s, k, f) \ 945 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 946 #define bus_dmamem_unmap(t, k, s) \ 947 (*(t)->_dmamem_unmap)((t), (k), (s)) 948 #define bus_dmamem_mmap(t, sg, n, o, p, f) \ 949 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 950 951 #define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP 952 #define bus_dmatag_destroy(t) 953 954 /* 955 * bus_dmamap_t 956 * 957 * Describes a DMA mapping. 958 */ 959 struct vax_bus_dmamap { 960 /* 961 * PRIVATE MEMBERS: not for use my machine-independent code. 962 */ 963 bus_size_t _dm_size; /* largest DMA transfer mappable */ 964 int _dm_segcnt; /* number of segs this map can map */ 965 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 966 bus_size_t _dm_boundary; /* don't cross this */ 967 int _dm_flags; /* misc. flags */ 968 969 /* 970 * This is used only for SGMAP-mapped DMA, but we keep it 971 * here to avoid pointless indirection. 972 */ 973 int _dm_pteidx; /* PTE index */ 974 int _dm_ptecnt; /* PTE count */ 975 u_long _dm_sgva; /* allocated sgva */ 976 bus_size_t _dm_sgvalen; /* svga length */ 977 978 /* 979 * PUBLIC MEMBERS: these are used by machine-independent code. 980 */ 981 bus_size_t dm_maxsegsz; /* largest possible segment */ 982 bus_size_t dm_mapsize; /* size of the mapping */ 983 int dm_nsegs; /* # valid segments in mapping */ 984 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 985 }; 986 987 /*#ifdef _VAX_BUS_DMA_PRIVATE */ 988 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 989 bus_size_t, int, bus_dmamap_t *); 990 void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 991 992 int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, 993 void *, bus_size_t, struct proc *, int); 994 int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int); 995 int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int); 996 int _bus_dmamap_load_raw(bus_dma_tag_t, 997 bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int); 998 999 void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 1000 void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1001 bus_size_t, int); 1002 1003 int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, 1004 bus_size_t alignment, bus_size_t boundary, 1005 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags); 1006 void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs); 1007 int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, 1008 int nsegs, size_t size, void **kvap, int flags); 1009 void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, size_t size); 1010 paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, 1011 int nsegs, off_t off, int prot, int flags); 1012 /*#endif*/ /* _VAX_BUS_DMA_PRIVATE */ 1013 1014 #endif /* _VAX_BUS_H_ */ 1015