1 /* $NetBSD: bus.h,v 1.8 1999/06/18 04:49:26 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Christopher G. Demetriou 55 * for the NetBSD Project. 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #ifndef _VAX_BUS_H_ 72 #define _VAX_BUS_H_ 73 74 #ifdef BUS_SPACE_DEBUG 75 /* 76 * Macros for sanity-checking the aligned-ness of pointers passed to 77 * bus space ops. These are not strictly necessary on the VAX, but 78 * could lead to performance improvements, and help catch problems 79 * with drivers that would creep up on other architectures. 80 */ 81 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 82 ((((u_long)(p)) & (sizeof(t)-1)) == 0) 83 84 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 85 ({ \ 86 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 87 printf("%s 0x%lx not aligned to %d bytes %s:%d\n", \ 88 d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \ 89 } \ 90 (void) 0; \ 91 }) 92 93 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 94 #else 95 #define __BUS_SPACE_ADDRESS_SANITY(p,t,d) (void) 0 96 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 97 #endif /* BUS_SPACE_DEBUG */ 98 99 /* 100 * Bus address and size types 101 */ 102 typedef u_long bus_addr_t; 103 typedef u_long bus_size_t; 104 105 /* 106 * Access methods for bus resources and address space. 107 */ 108 typedef struct vax_bus_space *bus_space_tag_t; 109 typedef u_long bus_space_handle_t; 110 111 struct vax_bus_space { 112 /* cookie */ 113 void *vbs_cookie; 114 115 /* mapping/unmapping */ 116 int (*vbs_map) __P((void *, bus_addr_t, bus_size_t, 117 int, bus_space_handle_t *, int)); 118 void (*vbs_unmap) __P((void *, bus_space_handle_t, 119 bus_size_t, int)); 120 int (*vbs_subregion) __P((void *, bus_space_handle_t, 121 bus_size_t, bus_size_t, bus_space_handle_t *)); 122 123 /* allocation/deallocation */ 124 int (*vbs_alloc) __P((void *, bus_addr_t, bus_addr_t, 125 bus_size_t, bus_size_t, bus_size_t, int, 126 bus_addr_t *, bus_space_handle_t *)); 127 void (*vbs_free) __P((void *, bus_space_handle_t, 128 bus_size_t)); 129 }; 130 131 /* 132 * int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr, 133 * bus_size_t size, int flags, bus_space_handle_t *bshp)); 134 * 135 * Map a region of bus space. 136 */ 137 138 #define BUS_SPACE_MAP_CACHEABLE 0x01 139 #define BUS_SPACE_MAP_LINEAR 0x02 140 141 #define bus_space_map(t, a, s, f, hp) \ 142 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 1) 143 #define vax_bus_space_map_noacct(t, a, s, f, hp) \ 144 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 0) 145 146 /* 147 * int bus_space_unmap __P((bus_space_tag_t t, 148 * bus_space_handle_t bsh, bus_size_t size)); 149 * 150 * Unmap a region of bus space. 151 */ 152 153 #define bus_space_unmap(t, h, s) \ 154 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 1) 155 #define vax_bus_space_unmap_noacct(t, h, s) \ 156 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 0) 157 158 /* 159 * int bus_space_subregion __P((bus_space_tag_t t, 160 * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, 161 * bus_space_handle_t *nbshp)); 162 * 163 * Get a new handle for a subregion of an already-mapped area of bus space. 164 */ 165 166 #define bus_space_subregion(t, h, o, s, nhp) \ 167 (*(t)->vbs_subregion)((t)->vbs_cookie, (h), (o), (s), (hp)) 168 169 /* 170 * int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t rstart, 171 * bus_addr_t rend, bus_size_t size, bus_size_t align, 172 * bus_size_t boundary, int flags, bus_addr_t *addrp, 173 * bus_space_handle_t *bshp)); 174 * 175 * Allocate a region of bus space. 176 */ 177 178 #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \ 179 (*(t)->vbs_alloc)((t)->vbs_cookie, (rs), (re), (s), (a), (b), \ 180 (f), (ap), (hp)) 181 182 /* 183 * int bus_space_free __P((bus_space_tag_t t, 184 * bus_space_handle_t bsh, bus_size_t size)); 185 * 186 * Free a region of bus space. 187 */ 188 189 #define bus_space_free(t, h, s) \ 190 (*(t)->vbs_free)((t)->vbs_cookie, (h), (s)) 191 192 /* 193 * u_intN_t bus_space_read_N __P((bus_space_tag_t tag, 194 * bus_space_handle_t bsh, bus_size_t offset)); 195 * 196 * Read a 1, 2, 4, or 8 byte quantity from bus space 197 * described by tag/handle/offset. 198 */ 199 200 #define bus_space_read_1(t, h, o) \ 201 (*(volatile u_int8_t *)((h) + (o))) 202 203 #define bus_space_read_2(t, h, o) \ 204 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"), \ 205 (*(volatile u_int16_t *)((h) + (o)))) 206 207 #define bus_space_read_4(t, h, o) \ 208 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"), \ 209 (*(volatile u_int32_t *)((h) + (o)))) 210 211 #if 0 /* Cause a link error for bus_space_read_8 */ 212 #define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! 213 #endif 214 215 /* 216 * void bus_space_read_multi_N __P((bus_space_tag_t tag, 217 * bus_space_handle_t bsh, bus_size_t offset, 218 * u_intN_t *addr, size_t count)); 219 * 220 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 221 * described by tag/handle/offset and copy into buffer provided. 222 */ 223 static __inline void vax_mem_read_multi_1 __P((bus_space_tag_t, 224 bus_space_handle_t, bus_size_t, u_int8_t *, size_t)); 225 static __inline void vax_mem_read_multi_2 __P((bus_space_tag_t, 226 bus_space_handle_t, bus_size_t, u_int16_t *, size_t)); 227 static __inline void vax_mem_read_multi_4 __P((bus_space_tag_t, 228 bus_space_handle_t, bus_size_t, u_int32_t *, size_t)); 229 230 #define bus_space_read_multi_1(t, h, o, a, c) \ 231 vax_mem_read_multi_1((t), (h), (o), (a), (c)) 232 233 #define bus_space_read_multi_2(t, h, o, a, c) \ 234 do { \ 235 __BUS_SPACE_ADDRESS_SANITY((a), u_int16_t, "buffer"); \ 236 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 237 vax_mem_read_multi_2((t), (h), (o), (a), (c)); \ 238 } while (0) 239 240 #define bus_space_read_multi_4(t, h, o, a, c) \ 241 do { \ 242 __BUS_SPACE_ADDRESS_SANITY((a), u_int32_t, "buffer"); \ 243 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 244 vax_mem_read_multi_4((t), (h), (o), (a), (c)); \ 245 } while (0) 246 247 #if 0 /* Cause a link error for bus_space_read_multi_8 */ 248 #define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! 249 #endif 250 251 static __inline void 252 vax_mem_read_multi_1(t, h, o, a, c) 253 bus_space_tag_t t; 254 bus_space_handle_t h; 255 bus_size_t o; 256 u_int8_t *a; 257 size_t c; 258 { 259 const bus_addr_t addr = h + o; 260 261 for (; c != 0; c--, a++) 262 *a = *(volatile u_int8_t *)(addr); 263 } 264 265 static __inline void 266 vax_mem_read_multi_2(t, h, o, a, c) 267 bus_space_tag_t t; 268 bus_space_handle_t h; 269 bus_size_t o; 270 u_int16_t *a; 271 size_t c; 272 { 273 const bus_addr_t addr = h + o; 274 275 for (; c != 0; c--, a++) 276 *a = *(volatile u_int16_t *)(addr); 277 } 278 279 static __inline void 280 vax_mem_read_multi_4(t, h, o, a, c) 281 bus_space_tag_t t; 282 bus_space_handle_t h; 283 bus_size_t o; 284 u_int32_t *a; 285 size_t c; 286 { 287 const bus_addr_t addr = h + o; 288 289 for (; c != 0; c--, a++) 290 *a = *(volatile u_int32_t *)(addr); 291 } 292 293 /* 294 * void bus_space_read_region_N __P((bus_space_tag_t tag, 295 * bus_space_handle_t bsh, bus_size_t offset, 296 * u_intN_t *addr, size_t count)); 297 * 298 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 299 * described by tag/handle and starting at `offset' and copy into 300 * buffer provided. 301 */ 302 303 static __inline void vax_mem_read_region_1 __P((bus_space_tag_t, 304 bus_space_handle_t, bus_size_t, u_int8_t *, size_t)); 305 static __inline void vax_mem_read_region_2 __P((bus_space_tag_t, 306 bus_space_handle_t, bus_size_t, u_int16_t *, size_t)); 307 static __inline void vax_mem_read_region_4 __P((bus_space_tag_t, 308 bus_space_handle_t, bus_size_t, u_int32_t *, size_t)); 309 310 #define bus_space_read_region_1(t, h, o, a, c) \ 311 do { \ 312 vax_mem_read_region_1((t), (h), (o), (a), (c)); \ 313 } while (0) 314 315 #define bus_space_read_region_2(t, h, o, a, c) \ 316 do { \ 317 __BUS_SPACE_ADDRESS_SANITY((a), u_int16_t, "buffer"); \ 318 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 319 vax_mem_read_region_2((t), (h), (o), (a), (c)); \ 320 } while (0) 321 322 #define bus_space_read_region_4(t, h, o, a, c) \ 323 do { \ 324 __BUS_SPACE_ADDRESS_SANITY((a), u_int32_t, "buffer"); \ 325 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 326 vax_mem_read_region_4((t), (h), (o), (a), (c)); \ 327 } while (0) 328 329 #if 0 /* Cause a link error for bus_space_read_region_8 */ 330 #define bus_space_read_region_8 \ 331 !!! bus_space_read_region_8 unimplemented !!! 332 #endif 333 334 static __inline void 335 vax_mem_read_region_1(t, h, o, a, c) 336 bus_space_tag_t t; 337 bus_space_handle_t h; 338 bus_size_t o; 339 u_int8_t *a; 340 size_t c; 341 { 342 bus_addr_t addr = h + o; 343 344 for (; c != 0; c--, addr++, a++) 345 *a = *(volatile u_int8_t *)(addr); 346 } 347 348 static __inline void 349 vax_mem_read_region_2(t, h, o, a, c) 350 bus_space_tag_t t; 351 bus_space_handle_t h; 352 bus_size_t o; 353 u_int16_t *a; 354 size_t c; 355 { 356 bus_addr_t addr = h + o; 357 358 for (; c != 0; c--, addr++, a++) 359 *a = *(volatile u_int16_t *)(addr); 360 } 361 362 static __inline void 363 vax_mem_read_region_4(t, h, o, a, c) 364 bus_space_tag_t t; 365 bus_space_handle_t h; 366 bus_size_t o; 367 u_int32_t *a; 368 size_t c; 369 { 370 bus_addr_t addr = h + o; 371 372 for (; c != 0; c--, addr++, a++) 373 *a = *(volatile u_int32_t *)(addr); 374 } 375 376 /* 377 * void bus_space_write_N __P((bus_space_tag_t tag, 378 * bus_space_handle_t bsh, bus_size_t offset, 379 * u_intN_t value)); 380 * 381 * Write the 1, 2, 4, or 8 byte value `value' to bus space 382 * described by tag/handle/offset. 383 */ 384 385 #define bus_space_write_1(t, h, o, v) \ 386 do { \ 387 ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \ 388 } while (0) 389 390 #define bus_space_write_2(t, h, o, v) \ 391 do { \ 392 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 393 ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \ 394 } while (0) 395 396 #define bus_space_write_4(t, h, o, v) \ 397 do { \ 398 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 399 ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \ 400 } while (0) 401 402 #if 0 /* Cause a link error for bus_space_write_8 */ 403 #define bus_space_write_8 !!! bus_space_write_8 not implemented !!! 404 #endif 405 406 /* 407 * void bus_space_write_multi_N __P((bus_space_tag_t tag, 408 * bus_space_handle_t bsh, bus_size_t offset, 409 * const u_intN_t *addr, size_t count)); 410 * 411 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 412 * provided to bus space described by tag/handle/offset. 413 */ 414 static __inline void vax_mem_write_multi_1 __P((bus_space_tag_t, 415 bus_space_handle_t, bus_size_t, const u_int8_t *, size_t)); 416 static __inline void vax_mem_write_multi_2 __P((bus_space_tag_t, 417 bus_space_handle_t, bus_size_t, const u_int16_t *, size_t)); 418 static __inline void vax_mem_write_multi_4 __P((bus_space_tag_t, 419 bus_space_handle_t, bus_size_t, const u_int32_t *, size_t)); 420 421 #define bus_space_write_multi_1(t, h, o, a, c) \ 422 do { \ 423 vax_mem_write_multi_1((t), (h), (o), (a), (c)); \ 424 } while (0) 425 426 #define bus_space_write_multi_2(t, h, o, a, c) \ 427 do { \ 428 __BUS_SPACE_ADDRESS_SANITY((a), u_int16_t, "buffer"); \ 429 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 430 vax_mem_write_multi_2((t), (h), (o), (a), (c)); \ 431 } while (0) 432 433 #define bus_space_write_multi_4(t, h, o, a, c) \ 434 do { \ 435 __BUS_SPACE_ADDRESS_SANITY((a), u_int32_t, "buffer"); \ 436 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 437 vax_mem_write_multi_4((t), (h), (o), (a), (c)); \ 438 } while (0) 439 440 #if 0 /* Cause a link error for bus_space_write_multi_8 */ 441 #define bus_space_write_multi_8(t, h, o, a, c) \ 442 !!! bus_space_write_multi_8 unimplemented !!! 443 #endif 444 445 static __inline void 446 vax_mem_write_multi_1(t, h, o, a, c) 447 bus_space_tag_t t; 448 bus_space_handle_t h; 449 bus_size_t o; 450 const u_int8_t *a; 451 size_t c; 452 { 453 const bus_addr_t addr = h + o; 454 455 for (; c != 0; c--, a++) 456 *(volatile u_int8_t *)(addr) = *a; 457 } 458 459 static __inline void 460 vax_mem_write_multi_2(t, h, o, a, c) 461 bus_space_tag_t t; 462 bus_space_handle_t h; 463 bus_size_t o; 464 const u_int16_t *a; 465 size_t c; 466 { 467 const bus_addr_t addr = h + o; 468 469 for (; c != 0; c--, a++) 470 *(volatile u_int16_t *)(addr) = *a; 471 } 472 473 static __inline void 474 vax_mem_write_multi_4(t, h, o, a, c) 475 bus_space_tag_t t; 476 bus_space_handle_t h; 477 bus_size_t o; 478 const u_int32_t *a; 479 size_t c; 480 { 481 const bus_addr_t addr = h + o; 482 483 for (; c != 0; c--, a++) 484 *(volatile u_int32_t *)(addr) = *a; 485 } 486 487 /* 488 * void bus_space_write_region_N __P((bus_space_tag_t tag, 489 * bus_space_handle_t bsh, bus_size_t offset, 490 * const u_intN_t *addr, size_t count)); 491 * 492 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 493 * to bus space described by tag/handle starting at `offset'. 494 */ 495 static __inline void vax_mem_write_region_1 __P((bus_space_tag_t, 496 bus_space_handle_t, bus_size_t, const u_int8_t *, size_t)); 497 static __inline void vax_mem_write_region_2 __P((bus_space_tag_t, 498 bus_space_handle_t, bus_size_t, const u_int16_t *, size_t)); 499 static __inline void vax_mem_write_region_4 __P((bus_space_tag_t, 500 bus_space_handle_t, bus_size_t, const u_int32_t *, size_t)); 501 502 #define bus_space_write_region_1(t, h, o, a, c) \ 503 vax_mem_write_region_1((t), (h), (o), (a), (c)) 504 505 #define bus_space_write_region_2(t, h, o, a, c) \ 506 do { \ 507 __BUS_SPACE_ADDRESS_SANITY((a), u_int16_t, "buffer"); \ 508 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 509 vax_mem_write_region_2((t), (h), (o), (a), (c)); \ 510 } while (0) 511 512 #define bus_space_write_region_4(t, h, o, a, c) \ 513 do { \ 514 __BUS_SPACE_ADDRESS_SANITY((a), u_int32_t, "buffer"); \ 515 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 516 vax_mem_write_region_4((t), (h), (o), (a), (c)); \ 517 } while (0) 518 519 #if 0 /* Cause a link error for bus_space_write_region_8 */ 520 #define bus_space_write_region_8 \ 521 !!! bus_space_write_region_8 unimplemented !!! 522 #endif 523 524 static __inline void 525 vax_mem_write_region_1(t, h, o, a, c) 526 bus_space_tag_t t; 527 bus_space_handle_t h; 528 bus_size_t o; 529 const u_int8_t *a; 530 size_t c; 531 { 532 bus_addr_t addr = h + o; 533 534 for (; c != 0; c--, addr++, a++) 535 *(volatile u_int8_t *)(addr) = *a; 536 } 537 538 static __inline void 539 vax_mem_write_region_2(t, h, o, a, c) 540 bus_space_tag_t t; 541 bus_space_handle_t h; 542 bus_size_t o; 543 const u_int16_t *a; 544 size_t c; 545 { 546 bus_addr_t addr = h + o; 547 548 for (; c != 0; c--, addr++, a++) 549 *(volatile u_int16_t *)(addr) = *a; 550 } 551 552 static __inline void 553 vax_mem_write_region_4(t, h, o, a, c) 554 bus_space_tag_t t; 555 bus_space_handle_t h; 556 bus_size_t o; 557 const u_int32_t *a; 558 size_t c; 559 { 560 bus_addr_t addr = h + o; 561 562 for (; c != 0; c--, addr++, a++) 563 *(volatile u_int32_t *)(addr) = *a; 564 } 565 566 /* 567 * void bus_space_set_multi_N __P((bus_space_tag_t tag, 568 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 569 * size_t count)); 570 * 571 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 572 * by tag/handle/offset `count' times. 573 */ 574 575 static __inline void vax_mem_set_multi_1 __P((bus_space_tag_t, 576 bus_space_handle_t, bus_size_t, u_int8_t, size_t)); 577 static __inline void vax_mem_set_multi_2 __P((bus_space_tag_t, 578 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 579 static __inline void vax_mem_set_multi_4 __P((bus_space_tag_t, 580 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 581 582 #define bus_space_set_multi_1(t, h, o, v, c) \ 583 vax_mem_set_multi_1((t), (h), (o), (v), (c)) 584 585 #define bus_space_set_multi_2(t, h, o, v, c) \ 586 do { \ 587 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 588 vax_mem_set_multi_2((t), (h), (o), (v), (c)); \ 589 } while (0) 590 591 #define bus_space_set_multi_4(t, h, o, v, c) \ 592 do { \ 593 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 594 vax_mem_set_multi_4((t), (h), (o), (v), (c)); \ 595 } while (0) 596 597 static __inline void 598 vax_mem_set_multi_1(t, h, o, v, c) 599 bus_space_tag_t t; 600 bus_space_handle_t h; 601 bus_size_t o; 602 u_int8_t v; 603 size_t c; 604 { 605 bus_addr_t addr = h + o; 606 607 while (c--) 608 *(volatile u_int8_t *)(addr) = v; 609 } 610 611 static __inline void 612 vax_mem_set_multi_2(t, h, o, v, c) 613 bus_space_tag_t t; 614 bus_space_handle_t h; 615 bus_size_t o; 616 u_int16_t v; 617 size_t c; 618 { 619 bus_addr_t addr = h + o; 620 621 while (c--) 622 *(volatile u_int16_t *)(addr) = v; 623 } 624 625 static __inline void 626 vax_mem_set_multi_4(t, h, o, v, c) 627 bus_space_tag_t t; 628 bus_space_handle_t h; 629 bus_size_t o; 630 u_int32_t v; 631 size_t c; 632 { 633 bus_addr_t addr = h + o; 634 635 while (c--) 636 *(volatile u_int32_t *)(addr) = v; 637 } 638 639 #if 0 /* Cause a link error for bus_space_set_multi_8 */ 640 #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 641 #endif 642 643 /* 644 * void bus_space_set_region_N __P((bus_space_tag_t tag, 645 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 646 * size_t count)); 647 * 648 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 649 * by tag/handle starting at `offset'. 650 */ 651 652 static __inline void vax_mem_set_region_1 __P((bus_space_tag_t, 653 bus_space_handle_t, bus_size_t, u_int8_t, size_t)); 654 static __inline void vax_mem_set_region_2 __P((bus_space_tag_t, 655 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 656 static __inline void vax_mem_set_region_4 __P((bus_space_tag_t, 657 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 658 659 #define bus_space_set_region_1(t, h, o, v, c) \ 660 vax_mem_set_region_1((t), (h), (o), (v), (c)) 661 662 #define bus_space_set_region_2(t, h, o, v, c) \ 663 do { \ 664 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int16_t, "bus addr"); \ 665 vax_mem_set_region_2((t), (h), (o), (v), (c)); \ 666 } while (0) 667 668 #define bus_space_set_region_4(t, h, o, v, c) \ 669 do { \ 670 __BUS_SPACE_ADDRESS_SANITY((h) + (o), u_int32_t, "bus addr"); \ 671 vax_mem_set_region_4((t), (h), (o), (v), (c)); \ 672 } while (0) 673 674 static __inline void 675 vax_mem_set_region_1(t, h, o, v, c) 676 bus_space_tag_t t; 677 bus_space_handle_t h; 678 bus_size_t o; 679 u_int8_t v; 680 size_t c; 681 { 682 bus_addr_t addr = h + o; 683 684 for (; c != 0; c--, addr++) 685 *(volatile u_int8_t *)(addr) = v; 686 } 687 688 static __inline void 689 vax_mem_set_region_2(t, h, o, v, c) 690 bus_space_tag_t t; 691 bus_space_handle_t h; 692 bus_size_t o; 693 u_int16_t v; 694 size_t c; 695 { 696 bus_addr_t addr = h + o; 697 698 for (; c != 0; c--, addr += 2) 699 *(volatile u_int16_t *)(addr) = v; 700 } 701 702 static __inline void 703 vax_mem_set_region_4(t, h, o, v, c) 704 bus_space_tag_t t; 705 bus_space_handle_t h; 706 bus_size_t o; 707 u_int32_t v; 708 size_t c; 709 { 710 bus_addr_t addr = h + o; 711 712 for (; c != 0; c--, addr += 4) 713 *(volatile u_int32_t *)(addr) = v; 714 } 715 716 #if 0 /* Cause a link error for bus_space_set_region_8 */ 717 #define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! 718 #endif 719 720 /* 721 * void bus_space_copy_region_N __P((bus_space_tag_t tag, 722 * bus_space_handle_t bsh1, bus_size_t off1, 723 * bus_space_handle_t bsh2, bus_size_t off2, 724 * size_t count)); 725 * 726 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 727 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. 728 */ 729 730 static __inline void vax_mem_copy_region_1 __P((bus_space_tag_t, 731 bus_space_handle_t, bus_size_t, bus_space_handle_t, 732 bus_size_t, size_t)); 733 static __inline void vax_mem_copy_region_2 __P((bus_space_tag_t, 734 bus_space_handle_t, bus_size_t, bus_space_handle_t, 735 bus_size_t, size_t)); 736 static __inline void vax_mem_copy_region_4 __P((bus_space_tag_t, 737 bus_space_handle_t, bus_size_t, bus_space_handle_t, 738 bus_size_t, size_t)); 739 740 #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ 741 vax_mem_copy_region_1((t), (h1), (o1), (h2), (o2), (c)) 742 743 #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ 744 do { \ 745 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), u_int16_t, "bus addr 1"); \ 746 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), u_int16_t, "bus addr 2"); \ 747 vax_mem_copy_region_2((t), (h1), (o1), (h2), (o2), (c)); \ 748 } while (0) 749 750 #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ 751 do { \ 752 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), u_int32_t, "bus addr 1"); \ 753 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), u_int32_t, "bus addr 2"); \ 754 vax_mem_copy_region_4((t), (h1), (o1), (h2), (o2), (c)); \ 755 } while (0) 756 757 static __inline void 758 vax_mem_copy_region_1(t, h1, o1, h2, o2, c) 759 bus_space_tag_t t; 760 bus_space_handle_t h1; 761 bus_size_t o1; 762 bus_space_handle_t h2; 763 bus_size_t o2; 764 size_t c; 765 { 766 bus_addr_t addr1 = h1 + o1; 767 bus_addr_t addr2 = h2 + o2; 768 769 if (addr1 >= addr2) { 770 /* src after dest: copy forward */ 771 for (; c != 0; c--, addr1++, addr2++) 772 *(volatile u_int8_t *)(addr2) = 773 *(volatile u_int8_t *)(addr1); 774 } else { 775 /* dest after src: copy backwards */ 776 for (addr1 += (c - 1), addr2 += (c - 1); 777 c != 0; c--, addr1--, addr2--) 778 *(volatile u_int8_t *)(addr2) = 779 *(volatile u_int8_t *)(addr1); 780 } 781 } 782 783 static __inline void 784 vax_mem_copy_region_2(t, h1, o1, h2, o2, c) 785 bus_space_tag_t t; 786 bus_space_handle_t h1; 787 bus_size_t o1; 788 bus_space_handle_t h2; 789 bus_size_t o2; 790 size_t c; 791 { 792 bus_addr_t addr1 = h1 + o1; 793 bus_addr_t addr2 = h2 + o2; 794 795 if (addr1 >= addr2) { 796 /* src after dest: copy forward */ 797 for (; c != 0; c--, addr1 += 2, addr2 += 2) 798 *(volatile u_int16_t *)(addr2) = 799 *(volatile u_int16_t *)(addr1); 800 } else { 801 /* dest after src: copy backwards */ 802 for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1); 803 c != 0; c--, addr1 -= 2, addr2 -= 2) 804 *(volatile u_int16_t *)(addr2) = 805 *(volatile u_int16_t *)(addr1); 806 } 807 } 808 809 static __inline void 810 vax_mem_copy_region_4(t, h1, o1, h2, o2, c) 811 bus_space_tag_t t; 812 bus_space_handle_t h1; 813 bus_size_t o1; 814 bus_space_handle_t h2; 815 bus_size_t o2; 816 size_t c; 817 { 818 bus_addr_t addr1 = h1 + o1; 819 bus_addr_t addr2 = h2 + o2; 820 821 if (addr1 >= addr2) { 822 /* src after dest: copy forward */ 823 for (; c != 0; c--, addr1 += 4, addr2 += 4) 824 *(volatile u_int32_t *)(addr2) = 825 *(volatile u_int32_t *)(addr1); 826 } else { 827 /* dest after src: copy backwards */ 828 for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1); 829 c != 0; c--, addr1 -= 4, addr2 -= 4) 830 *(volatile u_int32_t *)(addr2) = 831 *(volatile u_int32_t *)(addr1); 832 } 833 } 834 835 #if 0 /* Cause a link error for bus_space_copy_8 */ 836 #define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! 837 #endif 838 839 840 /* 841 * Bus read/write barrier methods. 842 * 843 * void bus_space_barrier __P((bus_space_tag_t tag, 844 * bus_space_handle_t bsh, bus_size_t offset, 845 * bus_size_t len, int flags)); 846 * 847 * Note: the vax does not currently require barriers, but we must 848 * provide the flags to MI code. 849 */ 850 #define bus_space_barrier(t, h, o, l, f) \ 851 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f))) 852 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 853 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 854 855 856 /* 857 * Flags used in various bus DMA methods. 858 */ 859 #define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */ 860 #define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */ 861 #define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */ 862 #define BUS_DMA_COHERENT 0x04 /* hint: map memory DMA coherent */ 863 #define BUS_DMA_BUS1 0x10 /* placeholders for bus functions... */ 864 #define BUS_DMA_BUS2 0x20 865 #define BUS_DMA_BUS3 0x40 866 #define BUS_DMA_BUS4 0x80 867 868 /* 869 * Private flags stored in the DMA map. 870 */ 871 #define DMAMAP_HAS_SGMAP 0x80000000 /* sgva/len are valid */ 872 873 /* Forwards needed by prototypes below. */ 874 struct mbuf; 875 struct uio; 876 struct vax_sgmap; 877 878 /* 879 * Operations performed by bus_dmamap_sync(). 880 */ 881 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 882 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 883 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 884 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 885 886 /* 887 * vax_bus_t 888 * 889 * Busses supported by NetBSD/vax, used by internal 890 * utility functions. NOT TO BE USED BY MACHINE-INDEPENDENT 891 * CODE! 892 */ 893 typedef enum { 894 VAX_BUS_MAINBUS, 895 VAX_BUS_SBI, 896 VAX_BUS_MASSBUS, 897 VAX_BUS_UNIBUS, /* Also handles QBUS */ 898 VAX_BUS_BI, 899 VAX_BUS_XMI, 900 VAX_BUS_TURBOCHANNEL 901 } vax_bus_t; 902 903 typedef struct vax_bus_dma_tag *bus_dma_tag_t; 904 typedef struct vax_bus_dmamap *bus_dmamap_t; 905 906 /* 907 * bus_dma_segment_t 908 * 909 * Describes a single contiguous DMA transaction. Values 910 * are suitable for programming into DMA registers. 911 */ 912 struct vax_bus_dma_segment { 913 bus_addr_t ds_addr; /* DMA address */ 914 bus_size_t ds_len; /* length of transfer */ 915 }; 916 typedef struct vax_bus_dma_segment bus_dma_segment_t; 917 918 /* 919 * bus_dma_tag_t 920 * 921 * A machine-dependent opaque type describing the implementation of 922 * DMA for a given bus. 923 */ 924 struct vax_bus_dma_tag { 925 void *_cookie; /* cookie used in the guts */ 926 bus_addr_t _wbase; /* DMA window base */ 927 bus_size_t _wsize; /* DMA window size */ 928 929 /* 930 * Some chipsets have a built-in boundary constraint, independent 931 * of what the device requests. This allows that boundary to 932 * be specified. If the device has a more restrictive contraint, 933 * the map will use that, otherwise this boundary will be used. 934 * This value is ignored if 0. 935 */ 936 bus_size_t _boundary; 937 938 /* 939 * A bus may have more than one SGMAP window, so SGMAP 940 * windows also get a pointer to their SGMAP state. 941 */ 942 struct vax_sgmap *_sgmap; 943 944 /* 945 * Internal-use only utility methods. NOT TO BE USED BY 946 * MACHINE-INDEPENDENT CODE! 947 */ 948 bus_dma_tag_t (*_get_tag) __P((bus_dma_tag_t, vax_bus_t)); 949 950 /* 951 * DMA mapping methods. 952 */ 953 int (*_dmamap_create) __P((bus_dma_tag_t, bus_size_t, int, 954 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 955 void (*_dmamap_destroy) __P((bus_dma_tag_t, bus_dmamap_t)); 956 int (*_dmamap_load) __P((bus_dma_tag_t, bus_dmamap_t, void *, 957 bus_size_t, struct proc *, int)); 958 int (*_dmamap_load_mbuf) __P((bus_dma_tag_t, bus_dmamap_t, 959 struct mbuf *, int)); 960 int (*_dmamap_load_uio) __P((bus_dma_tag_t, bus_dmamap_t, 961 struct uio *, int)); 962 int (*_dmamap_load_raw) __P((bus_dma_tag_t, bus_dmamap_t, 963 bus_dma_segment_t *, int, bus_size_t, int)); 964 void (*_dmamap_unload) __P((bus_dma_tag_t, bus_dmamap_t)); 965 void (*_dmamap_sync) __P((bus_dma_tag_t, bus_dmamap_t, 966 bus_addr_t, bus_size_t, int)); 967 968 /* 969 * DMA memory utility functions. 970 */ 971 int (*_dmamem_alloc) __P((bus_dma_tag_t, bus_size_t, bus_size_t, 972 bus_size_t, bus_dma_segment_t *, int, int *, int)); 973 void (*_dmamem_free) __P((bus_dma_tag_t, 974 bus_dma_segment_t *, int)); 975 int (*_dmamem_map) __P((bus_dma_tag_t, bus_dma_segment_t *, 976 int, size_t, caddr_t *, int)); 977 void (*_dmamem_unmap) __P((bus_dma_tag_t, caddr_t, size_t)); 978 int (*_dmamem_mmap) __P((bus_dma_tag_t, bus_dma_segment_t *, 979 int, int, int, int)); 980 }; 981 982 #define vaxbus_dma_get_tag(t, b) \ 983 (*(t)->_get_tag)(t, b) 984 985 #define bus_dmamap_create(t, s, n, m, b, f, p) \ 986 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 987 #define bus_dmamap_destroy(t, p) \ 988 (*(t)->_dmamap_destroy)((t), (p)) 989 #define bus_dmamap_load(t, m, b, s, p, f) \ 990 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 991 #define bus_dmamap_load_mbuf(t, m, b, f) \ 992 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 993 #define bus_dmamap_load_uio(t, m, u, f) \ 994 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 995 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 996 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 997 #define bus_dmamap_unload(t, p) \ 998 (*(t)->_dmamap_unload)((t), (p)) 999 #define bus_dmamap_sync(t, p, o, l, ops) \ 1000 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) 1001 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 1002 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 1003 #define bus_dmamem_free(t, sg, n) \ 1004 (*(t)->_dmamem_free)((t), (sg), (n)) 1005 #define bus_dmamem_map(t, sg, n, s, k, f) \ 1006 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 1007 #define bus_dmamem_unmap(t, k, s) \ 1008 (*(t)->_dmamem_unmap)((t), (k), (s)) 1009 #define bus_dmamem_mmap(t, sg, n, o, p, f) \ 1010 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 1011 1012 /* 1013 * bus_dmamap_t 1014 * 1015 * Describes a DMA mapping. 1016 */ 1017 struct vax_bus_dmamap { 1018 /* 1019 * PRIVATE MEMBERS: not for use my machine-independent code. 1020 */ 1021 bus_size_t _dm_size; /* largest DMA transfer mappable */ 1022 int _dm_segcnt; /* number of segs this map can map */ 1023 bus_size_t _dm_maxsegsz; /* largest possible segment */ 1024 bus_size_t _dm_boundary; /* don't cross this */ 1025 int _dm_flags; /* misc. flags */ 1026 1027 /* 1028 * This is used only for SGMAP-mapped DMA, but we keep it 1029 * here to avoid pointless indirection. 1030 */ 1031 int _dm_pteidx; /* PTE index */ 1032 int _dm_ptecnt; /* PTE count */ 1033 u_long _dm_sgva; /* allocated sgva */ 1034 bus_size_t _dm_sgvalen; /* svga length */ 1035 1036 /* 1037 * PUBLIC MEMBERS: these are used by machine-independent code. 1038 */ 1039 bus_size_t dm_mapsize; /* size of the mapping */ 1040 int dm_nsegs; /* # valid segments in mapping */ 1041 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 1042 }; 1043 1044 #ifdef _VAX_BUS_DMA_PRIVATE 1045 int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 1046 bus_size_t, int, bus_dmamap_t *)); 1047 void _bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 1048 1049 int _bus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 1050 void *, bus_size_t, struct proc *, int)); 1051 int _bus_dmamap_load_mbuf __P((bus_dma_tag_t, 1052 bus_dmamap_t, struct mbuf *, int)); 1053 int _bus_dmamap_load_uio __P((bus_dma_tag_t, 1054 bus_dmamap_t, struct uio *, int)); 1055 int _bus_dmamap_load_raw __P((bus_dma_tag_t, 1056 bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int)); 1057 1058 void _bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 1059 void _bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1060 bus_size_t, int)); 1061 1062 int _bus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 1063 bus_size_t alignment, bus_size_t boundary, 1064 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags)); 1065 void _bus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1066 int nsegs)); 1067 int _bus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1068 int nsegs, size_t size, caddr_t *kvap, int flags)); 1069 void _bus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 1070 size_t size)); 1071 int _bus_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1072 int nsegs, int off, int prot, int flags)); 1073 #endif /* _VAX_BUS_DMA_PRIVATE */ 1074 1075 #endif /* _VAX_BUS_H_ */ 1076