1 /* $NetBSD: cpu.h,v 1.15 1995/03/28 18:20:44 jtc Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Gordon W. Ross 5 * Copyright (c) 1993 Adam Glass 6 * Copyright (c) 1988 University of Utah. 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * This code is derived from software contributed to Berkeley by 11 * the Systems Programming Group of the University of Utah Computer 12 * Science Department. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * from: Utah Hdr: cpu.h 1.16 91/03/25 43 * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 44 * cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp 45 */ 46 47 #ifdef _KERNEL 48 49 /* 50 * Exported definitions unique to sun3/68k cpu support. 51 */ 52 53 /* 54 * definitions of cpu-dependent requirements 55 * referenced in generic code 56 */ 57 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 58 59 #define cpu_exec(p) /* nothing */ 60 #define cpu_wait(p) /* nothing */ 61 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 62 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 63 64 /* 65 * Arguments to hardclock and gatherstats encapsulate the previous 66 * machine state in an opaque clockframe. One the sun3, we use 67 * what the hardware pushes on an interrupt (frame format 0). 68 */ 69 struct clockframe { 70 u_short sr; /* sr at time of interrupt */ 71 u_long pc; /* pc at time of interrupt */ 72 u_short vo; /* vector offset (4-word frame) */ 73 }; 74 75 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 76 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 77 #define CLKF_PC(framep) ((framep)->pc) 78 #if 0 79 /* We would like to do it this way... */ 80 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 81 #else 82 /* but until we start using PSL_M, we have to do this instead */ 83 #define CLKF_INTR(framep) (0) /* XXX */ 84 #endif 85 86 extern int astpending; /* need to trap before returning to user mode */ 87 #define aston() (astpending++) 88 89 /* 90 * Preempt the current process if in interrupt from user mode, 91 * or after the current trap/syscall if in system mode. 92 */ 93 extern int want_resched; /* resched() was called */ 94 #define need_resched() { want_resched++; aston(); } 95 96 /* 97 * Give a profiling tick to the current process when the user profiling 98 * buffer pages are invalid. On the sun3, request an ast to send us 99 * through trap, marking the proc as needing a profiling tick. 100 */ 101 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 102 103 /* 104 * Notify the current process (p) that it has a signal pending, 105 * process as soon as possible. 106 */ 107 #define signotify(p) aston() 108 109 /* 110 * Software Interrupt Register (SIR) 111 * The sun3 has a real software interrupt register set by 112 * isr_soft_request() so this scheme just multiplexes four 113 * software interrupt `sources' on the level one handler. 114 */ 115 union sun3sir { 116 int sir_any; 117 char sir_which[4]; 118 } sun3sir; 119 120 #define SIR_NET 0 121 #define SIR_CLOCK 1 122 #define SIR_SPARE2 2 123 #define SIR_SPARE3 3 124 125 #define setsoftint() isr_soft_request(1) 126 #define setsoftnet() (sun3sir.sir_which[SIR_NET] = 1, setsoftint()) 127 #define setsoftclock() (sun3sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 128 129 130 /* 131 * CTL_MACHDEP definitions. 132 */ 133 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 134 #define CPU_MAXID 2 /* number of valid machdep ids */ 135 136 #define CTL_MACHDEP_NAMES { \ 137 { 0, 0 }, \ 138 { "console_device", CTLTYPE_STRUCT }, \ 139 } 140 141 /* values for machineid */ 142 143 #define CPU_ARCH_MASK 0xf0 144 #define SUN3_ARCH 0x10 145 #define SUN3_IMPL_MASK 0x0f 146 #define SUN3_MACH_160 0x01 147 #define SUN3_MACH_50 0x02 148 #define SUN3_MACH_260 0x03 149 #define SUN3_MACH_110 0x04 150 #define SUN3_MACH_60 0x07 151 #define SUN3_MACH_E 0x08 152 153 extern int machineid, mmutype, ectype; 154 extern char *intiobase, *intiolimit; 155 156 /* 680X0 function codes */ 157 #define FC_USERD 1 /* user data space */ 158 #define FC_USERP 2 /* user program space */ 159 #define FC_CONTROL 3 /* sun control space */ 160 #define FC_SUPERD 5 /* supervisor data space */ 161 #define FC_SUPERP 6 /* supervisor program space */ 162 #define FC_CPU 7 /* CPU space */ 163 164 /* fields in the 68020 cache control register */ 165 #define IC_ENABLE 0x0001 /* enable instruction cache */ 166 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 167 #define IC_CE 0x0004 /* clear instruction cache entry */ 168 #define IC_CLR 0x0008 /* clear entire instruction cache */ 169 170 #define IC_CLEAR (IC_CLR|IC_ENABLE) 171 172 #endif /* _KERNEL */ 173