xref: /netbsd-src/sys/arch/sun3/include/cpu.h (revision 76dfffe33547c37f8bdd446e3e4ab0f3c16cea4b)
1 /*	$NetBSD: cpu.h,v 1.20 1995/12/21 05:02:10 mycroft Exp $	*/
2 
3 /*
4  * Copyright (c) 1994 Gordon W. Ross
5  * Copyright (c) 1993 Adam Glass
6  * Copyright (c) 1988 University of Utah.
7  * Copyright (c) 1982, 1990 The Regents of the University of California.
8  * All rights reserved.
9  *
10  * This code is derived from software contributed to Berkeley by
11  * the Systems Programming Group of the University of Utah Computer
12  * Science Department.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in the
21  *    documentation and/or other materials provided with the distribution.
22  * 3. All advertising materials mentioning features or use of this software
23  *    must display the following acknowledgement:
24  *	This product includes software developed by the University of
25  *	California, Berkeley and its contributors.
26  * 4. Neither the name of the University nor the names of its contributors
27  *    may be used to endorse or promote products derived from this software
28  *    without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40  * SUCH DAMAGE.
41  *
42  *	from: Utah Hdr: cpu.h 1.16 91/03/25
43  *	from: @(#)cpu.h	7.7 (Berkeley) 6/27/91
44  *	cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp
45  */
46 
47 #ifdef _KERNEL
48 
49 /*
50  * Exported definitions unique to sun3/68k cpu support.
51  */
52 
53 /*
54  * definitions of cpu-dependent requirements
55  * referenced in generic code
56  */
57 #define	cpu_swapin(p)			/* nothing */
58 #define	cpu_wait(p)			/* nothing */
59 
60 /*
61  * Arguments to hardclock and gatherstats encapsulate the previous
62  * machine state in an opaque clockframe.  One the sun3, we use
63  * what the hardware pushes on an interrupt (frame format 0).
64  */
65 struct clockframe {
66 	u_short	sr;		/* sr at time of interrupt */
67 	u_long	pc;		/* pc at time of interrupt */
68 	u_short	vo;		/* vector offset (4-word frame) */
69 };
70 
71 #define	CLKF_USERMODE(framep)	(((framep)->sr & PSL_S) == 0)
72 #define	CLKF_BASEPRI(framep)	(((framep)->sr & PSL_IPL) == 0)
73 #define	CLKF_PC(framep)		((framep)->pc)
74 #if 0
75 /* We would like to do it this way... */
76 #define	CLKF_INTR(framep)	(((framep)->sr & PSL_M) == 0)
77 #else
78 /* but until we start using PSL_M, we have to do this instead */
79 #define	CLKF_INTR(framep)	(0)	/* XXX */
80 #endif
81 
82 extern int astpending;	 /* need to trap before returning to user mode */
83 #define aston() (astpending++)
84 
85 /*
86  * Preempt the current process if in interrupt from user mode,
87  * or after the current trap/syscall if in system mode.
88  */
89 extern int want_resched; /* resched() was called */
90 #define	need_resched()	{ want_resched++; aston(); }
91 
92 /*
93  * Give a profiling tick to the current process when the user profiling
94  * buffer pages are invalid.  On the sun3, request an ast to send us
95  * through trap, marking the proc as needing a profiling tick.
96  */
97 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, aston())
98 
99 /*
100  * Notify the current process (p) that it has a signal pending,
101  * process as soon as possible.
102  */
103 #define	signotify(p)	aston()
104 
105 /*
106  * Software Interrupt Register (SIR)
107  * The sun3 has a real software interrupt register set by
108  * isr_soft_request() so this scheme just multiplexes four
109  * software interrupt `sources' on the level one handler.
110  */
111 union sun3sir {
112 	int 	sir_any;
113 	char	sir_which[4];
114 } sun3sir;
115 
116 #define SIR_NET  	0
117 #define SIR_CLOCK	1
118 #define SIR_SPARE2	2
119 #define SIR_SPARE3	3
120 
121 #define	setsoftint()	isr_soft_request(1)
122 #define setsoftnet()	(sun3sir.sir_which[SIR_NET] = 1, setsoftint())
123 #define setsoftclock()	(sun3sir.sir_which[SIR_CLOCK] = 1, setsoftint())
124 
125 
126 /*
127  * CTL_MACHDEP definitions.
128  */
129 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */
130 #define	CPU_MAXID		2	/* number of valid machdep ids */
131 
132 #define	CTL_MACHDEP_NAMES { \
133 	{ 0, 0 }, \
134 	{ "console_device", CTLTYPE_STRUCT }, \
135 }
136 
137 /* values for cpu_machine_id */
138 
139 #define CPU_ARCH_MASK  0xf0
140 #define SUN3_ARCH      0x10
141 #define SUN3_IMPL_MASK 0x0f
142 #define SUN3_MACH_160  0x01
143 #define SUN3_MACH_50   0x02
144 #define SUN3_MACH_260  0x03
145 #define SUN3_MACH_110  0x04
146 #define SUN3_MACH_60   0x07
147 #define SUN3_MACH_E    0x08
148 
149 extern	unsigned char cpu_machine_id;
150 
151 /* 680X0 function codes */
152 #define	FC_USERD	1	/* user data space */
153 #define	FC_USERP	2	/* user program space */
154 #define	FC_CONTROL	3	/* sun control space */
155 #define	FC_SUPERD	5	/* supervisor data space */
156 #define	FC_SUPERP	6	/* supervisor program space */
157 #define	FC_CPU		7	/* CPU space */
158 
159 /* fields in the 68020 cache control register */
160 #define	IC_ENABLE	0x0001	/* enable instruction cache */
161 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
162 #define	IC_CE		0x0004	/* clear instruction cache entry */
163 #define	IC_CLR		0x0008	/* clear entire instruction cache */
164 
165 #define IC_CLEAR (IC_CLR|IC_ENABLE)
166 
167 #endif	/* _KERNEL */
168