1 /* Copyright (c) 1993 Adam Glass 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Utah Hdr: cpu.h 1.16 91/03/25 39 * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 40 * cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp 41 * $Id: cpu.h,v 1.12 1994/06/28 21:47:56 gwr Exp $ 42 */ 43 44 #ifdef KERNEL 45 46 /* 47 * Exported definitions unique to sun3/68k cpu support. 48 */ 49 50 /* 51 * definitions of cpu-dependent requirements 52 * referenced in generic code 53 */ 54 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 55 56 #define cpu_exec(p) /* nothing */ 57 #define cpu_swapin(p) /* nothing */ 58 #define cpu_wait(p) /* nothing */ 59 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 60 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 61 62 /* 63 * Arguments to hardclock and gatherstats encapsulate the previous 64 * machine state in an opaque clockframe. One the sun3, we use 65 * what the hardware pushes on an interrupt (frame format 0). 66 */ 67 struct clockframe { 68 u_short sr; /* sr at time of interrupt */ 69 u_long pc; /* pc at time of interrupt */ 70 u_short vo; /* vector offset (4-word frame) */ 71 }; 72 73 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 74 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 75 #define CLKF_PC(framep) ((framep)->pc) 76 #if 0 77 /* We would like to do it this way... */ 78 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 79 #else 80 /* but until we start using PSL_M, we have to do this instead */ 81 #define CLKF_INTR(framep) (0) /* XXX */ 82 #endif 83 84 extern int astpending; /* need to trap before returning to user mode */ 85 #define aston() (astpending++) 86 87 /* 88 * Preempt the current process if in interrupt from user mode, 89 * or after the current trap/syscall if in system mode. 90 */ 91 extern int want_resched; /* resched() was called */ 92 #define need_resched() { want_resched++; aston(); } 93 94 /* 95 * Give a profiling tick to the current process when the user profiling 96 * buffer pages are invalid. On the sun3, request an ast to send us 97 * through trap, marking the proc as needing a profiling tick. 98 */ 99 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 100 101 /* 102 * Notify the current process (p) that it has a signal pending, 103 * process as soon as possible. 104 */ 105 #define signotify(p) aston() 106 107 /* 108 * Software Interrupt Register (SIR) 109 * The sun3 has a real software interrupt register set by 110 * isr_soft_request() so this scheme just multiplexes four 111 * software interrupt `sources' on the level one handler. 112 */ 113 union sun3sir { 114 int sir_any; 115 char sir_which[4]; 116 } sun3sir; 117 118 #define SIR_NET 0 119 #define SIR_CLOCK 1 120 #define SIR_SPARE2 2 121 #define SIR_SPARE3 3 122 123 #define setsoftint() isr_soft_request(1) 124 #define setsoftnet() (sun3sir.sir_which[SIR_NET] = 1, setsoftint()) 125 #define setsoftclock() (sun3sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 126 127 128 /* 129 * CTL_MACHDEP definitions. 130 */ 131 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 132 #define CPU_MAXID 2 /* number of valid machdep ids */ 133 134 #define CTL_MACHDEP_NAMES { \ 135 { 0, 0 }, \ 136 { "console_device", CTLTYPE_STRUCT }, \ 137 } 138 139 /* values for machineid */ 140 141 #define CPU_ARCH_MASK 0xf0 142 #define SUN3_ARCH 0x10 143 #define SUN3_IMPL_MASK 0x0f 144 #define SUN3_MACH_160 0x01 145 #define SUN3_MACH_50 0x02 146 #define SUN3_MACH_260 0x03 147 #define SUN3_MACH_110 0x04 148 #define SUN3_MACH_60 0x07 149 #define SUN3_MACH_E 0x08 150 151 extern int machineid, mmutype, ectype; 152 extern char *intiobase, *intiolimit; 153 154 /* 680X0 function codes */ 155 #define FC_USERD 1 /* user data space */ 156 #define FC_USERP 2 /* user program space */ 157 #define FC_CONTROL 3 /* sun control space */ 158 #define FC_SUPERD 5 /* supervisor data space */ 159 #define FC_SUPERP 6 /* supervisor program space */ 160 #define FC_CPU 7 /* CPU space */ 161 162 /* fields in the 68020 cache control register */ 163 #define IC_ENABLE 0x0001 /* enable instruction cache */ 164 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 165 #define IC_CE 0x0004 /* clear instruction cache entry */ 166 #define IC_CLR 0x0008 /* clear entire instruction cache */ 167 168 #define IC_CLEAR (IC_CLR|IC_ENABLE) 169 170 #endif 171