1 /* $NetBSD: si_vme.c,v 1.10 1997/02/26 22:26:03 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * VME functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <scsi/scsi_all.h> 94 #include <scsi/scsi_debug.h> 95 #include <scsi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/dvma.h> 99 100 #define DEBUG XXX 101 102 #include <dev/ic/ncr5380reg.h> 103 #include <dev/ic/ncr5380var.h> 104 105 #include "sireg.h" 106 #include "sivar.h" 107 108 void si_vme_dma_setup __P((struct ncr5380_softc *)); 109 void si_vme_dma_start __P((struct ncr5380_softc *)); 110 void si_vme_dma_eop __P((struct ncr5380_softc *)); 111 void si_vme_dma_stop __P((struct ncr5380_softc *)); 112 113 void si_vme_intr_on __P((struct ncr5380_softc *)); 114 void si_vme_intr_off __P((struct ncr5380_softc *)); 115 116 /* 117 * New-style autoconfig attachment 118 */ 119 120 static int si_vmes_match __P((struct device *, struct cfdata *, void *)); 121 static void si_vmes_attach __P((struct device *, struct device *, void *)); 122 123 struct cfattach si_vmes_ca = { 124 sizeof(struct si_softc), si_vmes_match, si_vmes_attach 125 }; 126 127 /* 128 * Options for disconnect/reselect, DMA, and interrupts. 129 * By default, allow disconnect/reselect on targets 4-6. 130 * Those are normally tapes that really need it enabled. 131 */ 132 int si_vme_options = 0x0f; 133 134 135 static int 136 si_vmes_match(parent, cf, args) 137 struct device *parent; 138 struct cfdata *cf; 139 void *args; 140 { 141 struct confargs *ca = args; 142 int probe_addr; 143 144 #ifdef DIAGNOSTIC 145 if (ca->ca_bustype != BUS_VME16) { 146 printf("si_vmes_match: bustype %d?\n", ca->ca_bustype); 147 return (0); 148 } 149 #endif 150 151 /* 152 * Other Sun3 models may have VME "si" or "sc". 153 * This driver has no default address. 154 */ 155 if (ca->ca_paddr == -1) 156 return (0); 157 158 /* Make sure there is something there... */ 159 probe_addr = ca->ca_paddr + 1; 160 if (bus_peek(ca->ca_bustype, probe_addr, 1) == -1) 161 return (0); 162 163 /* 164 * If this is a VME SCSI board, we have to determine whether 165 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 166 * be determined using the fact that the "sc" board occupies 167 * 4K bytes in VME space but the "si" board occupies 2K bytes. 168 */ 169 /* Note: the "si" board should NOT respond here. */ 170 probe_addr = ca->ca_paddr + 0x801; 171 if (bus_peek(ca->ca_bustype, probe_addr, 1) != -1) { 172 /* Something responded at 2K+1. Maybe an "sc" board? */ 173 #ifdef DEBUG 174 printf("si_vmes_match: May be an `sc' board at pa=0x%x\n", 175 ca->ca_paddr); 176 #endif 177 return(0); 178 } 179 180 /* Default interrupt priority (always splbio==2) */ 181 if (ca->ca_intpri == -1) 182 ca->ca_intpri = 2; 183 184 return (1); 185 } 186 187 static void 188 si_vmes_attach(parent, self, args) 189 struct device *parent, *self; 190 void *args; 191 { 192 struct si_softc *sc = (struct si_softc *) self; 193 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 194 struct cfdata *cf = self->dv_cfdata; 195 struct confargs *ca = args; 196 197 /* Get options from config flags if specified. */ 198 if (cf->cf_flags) 199 sc->sc_options = cf->cf_flags; 200 else 201 sc->sc_options = si_vme_options; 202 203 printf(": options=0x%x\n", sc->sc_options); 204 205 sc->sc_adapter_type = ca->ca_bustype; 206 sc->sc_regs = (struct si_regs *) 207 bus_mapin(ca->ca_bustype, ca->ca_paddr, 208 sizeof(struct si_regs)); 209 sc->sc_adapter_iv_am = 210 VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 211 212 /* 213 * MD function pointers used by the MI code. 214 */ 215 ncr_sc->sc_pio_out = ncr5380_pio_out; 216 ncr_sc->sc_pio_in = ncr5380_pio_in; 217 ncr_sc->sc_dma_alloc = si_dma_alloc; 218 ncr_sc->sc_dma_free = si_dma_free; 219 ncr_sc->sc_dma_setup = si_vme_dma_setup; 220 ncr_sc->sc_dma_start = si_vme_dma_start; 221 ncr_sc->sc_dma_poll = si_dma_poll; 222 ncr_sc->sc_dma_eop = si_vme_dma_eop; 223 ncr_sc->sc_dma_stop = si_vme_dma_stop; 224 ncr_sc->sc_intr_on = si_vme_intr_on; 225 ncr_sc->sc_intr_off = si_vme_intr_off; 226 227 /* Attach interrupt handler. */ 228 isr_add_vectored(si_intr, (void *)sc, 229 ca->ca_intpri, ca->ca_intvec); 230 231 /* Do the common attach stuff. */ 232 si_attach(sc); 233 } 234 235 236 /* 237 * This is called when the bus is going idle, 238 * so we want to enable the SBC interrupts. 239 * That is controlled by the DMA enable! 240 * Who would have guessed! 241 * What a NASTY trick! 242 */ 243 void 244 si_vme_intr_on(ncr_sc) 245 struct ncr5380_softc *ncr_sc; 246 { 247 struct si_softc *sc = (struct si_softc *)ncr_sc; 248 volatile struct si_regs *si = sc->sc_regs; 249 250 /* receive mode should be safer */ 251 si->si_csr &= ~SI_CSR_SEND; 252 253 /* Clear the count so nothing happens. */ 254 si->dma_counth = 0; 255 si->dma_countl = 0; 256 257 /* Clear the start address too. (paranoid?) */ 258 si->dma_addrh = 0; 259 si->dma_addrl = 0; 260 261 /* Finally, enable the DMA engine. */ 262 si->si_csr |= SI_CSR_DMA_EN; 263 } 264 265 /* 266 * This is called when the bus is idle and we are 267 * about to start playing with the SBC chip. 268 */ 269 void 270 si_vme_intr_off(ncr_sc) 271 struct ncr5380_softc *ncr_sc; 272 { 273 struct si_softc *sc = (struct si_softc *)ncr_sc; 274 volatile struct si_regs *si = sc->sc_regs; 275 276 si->si_csr &= ~SI_CSR_DMA_EN; 277 } 278 279 /* 280 * This function is called during the COMMAND or MSG_IN phase 281 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 282 * to setup the DMA engine before the bus enters a DATA phase. 283 * 284 * XXX: The VME adapter appears to suppress SBC interrupts 285 * when the FIFO is not empty or the FIFO count is non-zero! 286 * 287 * On the VME version, setup the start addres, but clear the 288 * count (to make sure it stays idle) and set that later. 289 */ 290 void 291 si_vme_dma_setup(ncr_sc) 292 struct ncr5380_softc *ncr_sc; 293 { 294 struct si_softc *sc = (struct si_softc *)ncr_sc; 295 struct sci_req *sr = ncr_sc->sc_current; 296 struct si_dma_handle *dh = sr->sr_dma_hand; 297 volatile struct si_regs *si = sc->sc_regs; 298 long data_pa; 299 int xlen; 300 301 /* 302 * Get the DVMA mapping for this segment. 303 * XXX - Should separate allocation and mapin. 304 */ 305 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 306 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 307 if (data_pa & 1) 308 panic("si_dma_start: bad pa=0x%x", data_pa); 309 xlen = ncr_sc->sc_datalen; 310 xlen &= ~1; /* XXX: necessary? */ 311 sc->sc_reqlen = xlen; /* XXX: or less? */ 312 313 #ifdef DEBUG 314 if (si_debug & 2) { 315 printf("si_dma_setup: dh=%p, pa=0x%x, xlen=0x%x\n", 316 dh, data_pa, xlen); 317 } 318 #endif 319 320 /* Set direction (send/recv) */ 321 if (dh->dh_flags & SIDH_OUT) { 322 si->si_csr |= SI_CSR_SEND; 323 } else { 324 si->si_csr &= ~SI_CSR_SEND; 325 } 326 327 /* Reset the FIFO. */ 328 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 329 si->si_csr |= SI_CSR_FIFO_RES; 330 331 if (data_pa & 2) { 332 si->si_csr |= SI_CSR_BPCON; 333 } else { 334 si->si_csr &= ~SI_CSR_BPCON; 335 } 336 337 /* Load the start address. */ 338 si->dma_addrh = (ushort)(data_pa >> 16); 339 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 340 341 /* 342 * Keep the count zero or it may start early! 343 */ 344 si->dma_counth = 0; 345 si->dma_countl = 0; 346 347 #if 0 348 /* Clear FIFO counter. (also hits dma_count) */ 349 si->fifo_cnt_hi = 0; 350 si->fifo_count = 0; 351 #endif 352 } 353 354 355 void 356 si_vme_dma_start(ncr_sc) 357 struct ncr5380_softc *ncr_sc; 358 { 359 struct si_softc *sc = (struct si_softc *)ncr_sc; 360 struct sci_req *sr = ncr_sc->sc_current; 361 struct si_dma_handle *dh = sr->sr_dma_hand; 362 volatile struct si_regs *si = sc->sc_regs; 363 int s, xlen; 364 365 xlen = sc->sc_reqlen; 366 367 /* This MAY be time critical (not sure). */ 368 s = splhigh(); 369 370 si->dma_counth = (ushort)(xlen >> 16); 371 si->dma_countl = (ushort)(xlen & 0xFFFF); 372 373 /* Set it anyway, even though dma_count hits it. */ 374 si->fifo_cnt_hi = (ushort)(xlen >> 16); 375 si->fifo_count = (ushort)(xlen & 0xFFFF); 376 377 /* 378 * Acknowledge the phase change. (After DMA setup!) 379 * Put the SBIC into DMA mode, and start the transfer. 380 */ 381 if (dh->dh_flags & SIDH_OUT) { 382 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 383 SCI_CLR_INTR(ncr_sc); 384 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 385 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 386 *ncr_sc->sci_dma_send = 0; /* start it */ 387 } else { 388 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 389 SCI_CLR_INTR(ncr_sc); 390 *ncr_sc->sci_icmd = 0; 391 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 392 *ncr_sc->sci_irecv = 0; /* start it */ 393 } 394 395 /* Let'er rip! */ 396 si->si_csr |= SI_CSR_DMA_EN; 397 398 splx(s); 399 ncr_sc->sc_state |= NCR_DOINGDMA; 400 401 #ifdef DEBUG 402 if (si_debug & 2) { 403 printf("si_dma_start: started, flags=0x%x\n", 404 ncr_sc->sc_state); 405 } 406 #endif 407 } 408 409 410 void 411 si_vme_dma_eop(ncr_sc) 412 struct ncr5380_softc *ncr_sc; 413 { 414 415 /* Not needed - DMA was stopped prior to examining sci_csr */ 416 } 417 418 419 void 420 si_vme_dma_stop(ncr_sc) 421 struct ncr5380_softc *ncr_sc; 422 { 423 struct si_softc *sc = (struct si_softc *)ncr_sc; 424 struct sci_req *sr = ncr_sc->sc_current; 425 struct si_dma_handle *dh = sr->sr_dma_hand; 426 volatile struct si_regs *si = sc->sc_regs; 427 int resid, ntrans; 428 429 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 430 #ifdef DEBUG 431 printf("si_dma_stop: dma not running\n"); 432 #endif 433 return; 434 } 435 ncr_sc->sc_state &= ~NCR_DOINGDMA; 436 437 /* First, halt the DMA engine. */ 438 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 439 440 /* Set an impossible phase to prevent data movement? */ 441 *ncr_sc->sci_tcmd = PHASE_INVALID; 442 443 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 444 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 445 sr->sr_xs->error = XS_DRIVER_STUFFUP; 446 ncr_sc->sc_state |= NCR_ABORTING; 447 si_reset_adapter(ncr_sc); 448 goto out; 449 } 450 451 /* Note that timeout may have set the error flag. */ 452 if (ncr_sc->sc_state & NCR_ABORTING) 453 goto out; 454 455 /* XXX: Wait for DMA to actually finish? */ 456 457 /* 458 * Now try to figure out how much actually transferred 459 * 460 * The fifo_count does not reflect how many bytes were 461 * actually transferred for VME. 462 * 463 * SCSI-3 VME interface is a little funny on writes: 464 * if we have a disconnect, the dma has overshot by 465 * one byte and the resid needs to be incremented. 466 * Only happens for partial transfers. 467 * (Thanks to Matt Jacob) 468 */ 469 470 resid = si->fifo_count & 0xFFFF; 471 if (dh->dh_flags & SIDH_OUT) 472 if ((resid > 0) && (resid < sc->sc_reqlen)) 473 resid++; 474 ntrans = sc->sc_reqlen - resid; 475 476 #ifdef DEBUG 477 if (si_debug & 2) { 478 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 479 resid, ntrans); 480 } 481 #endif 482 483 if (ntrans < MIN_DMA_LEN) { 484 printf("si: fifo count: 0x%x\n", resid); 485 ncr_sc->sc_state |= NCR_ABORTING; 486 goto out; 487 } 488 if (ntrans > ncr_sc->sc_datalen) 489 panic("si_dma_stop: excess transfer"); 490 491 /* Adjust data pointer */ 492 ncr_sc->sc_dataptr += ntrans; 493 ncr_sc->sc_datalen -= ntrans; 494 495 /* 496 * After a read, we may need to clean-up 497 * "Left-over bytes" (yuck!) 498 */ 499 if (((dh->dh_flags & SIDH_OUT) == 0) && 500 ((si->si_csr & SI_CSR_LOB) != 0)) 501 { 502 char *cp = ncr_sc->sc_dataptr; 503 #ifdef DEBUG 504 printf("si: Got Left-over bytes!\n"); 505 #endif 506 if (si->si_csr & SI_CSR_BPCON) { 507 /* have SI_CSR_BPCON */ 508 cp[-1] = (si->si_bprl & 0xff00) >> 8; 509 } else { 510 switch (si->si_csr & SI_CSR_LOB) { 511 case SI_CSR_LOB_THREE: 512 cp[-3] = (si->si_bprh & 0xff00) >> 8; 513 cp[-2] = (si->si_bprh & 0x00ff); 514 cp[-1] = (si->si_bprl & 0xff00) >> 8; 515 break; 516 case SI_CSR_LOB_TWO: 517 cp[-2] = (si->si_bprh & 0xff00) >> 8; 518 cp[-1] = (si->si_bprh & 0x00ff); 519 break; 520 case SI_CSR_LOB_ONE: 521 cp[-1] = (si->si_bprh & 0xff00) >> 8; 522 break; 523 } 524 } 525 } 526 527 out: 528 si->dma_addrh = 0; 529 si->dma_addrl = 0; 530 531 si->dma_counth = 0; 532 si->dma_countl = 0; 533 534 si->fifo_cnt_hi = 0; 535 si->fifo_count = 0; 536 537 /* Put SBIC back in PIO mode. */ 538 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 539 *ncr_sc->sci_icmd = 0; 540 } 541