1 /* $NetBSD: si_vme.c,v 1.27 2007/03/12 12:03:18 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * VME functions for DMA 81 ****************************************************************/ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: si_vme.c,v 1.27 2007/03/12 12:03:18 tsutsui Exp $"); 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/errno.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/device.h> 92 #include <sys/buf.h> 93 #include <sys/proc.h> 94 #include <sys/user.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsipi_debug.h> 99 #include <dev/scsipi/scsiconf.h> 100 101 #include <machine/autoconf.h> 102 #include <machine/dvma.h> 103 104 /* #define DEBUG XXX */ 105 106 #include <dev/ic/ncr5380reg.h> 107 #include <dev/ic/ncr5380var.h> 108 109 #include "sireg.h" 110 #include "sivar.h" 111 112 void si_vme_dma_setup(struct ncr5380_softc *); 113 void si_vme_dma_start(struct ncr5380_softc *); 114 void si_vme_dma_eop(struct ncr5380_softc *); 115 void si_vme_dma_stop(struct ncr5380_softc *); 116 117 void si_vme_intr_on (struct ncr5380_softc *); 118 void si_vme_intr_off(struct ncr5380_softc *); 119 120 static void si_vme_reset(struct ncr5380_softc *); 121 122 /* 123 * New-style autoconfig attachment 124 */ 125 126 static int si_vme_match(struct device *, struct cfdata *, void *); 127 static void si_vme_attach(struct device *, struct device *, void *); 128 129 CFATTACH_DECL(si_vme, sizeof(struct si_softc), 130 si_vme_match, si_vme_attach, NULL, NULL); 131 132 /* 133 * Options for disconnect/reselect, DMA, and interrupts. 134 * By default, allow disconnect/reselect on targets 4-6. 135 * Those are normally tapes that really need it enabled. 136 */ 137 int si_vme_options = 0x0f; 138 139 140 static int 141 si_vme_match(struct device *parent, struct cfdata *cf, void *aux) 142 { 143 struct confargs *ca = aux; 144 int probe_addr; 145 146 /* No default VME address. */ 147 if (ca->ca_paddr == -1) 148 return (0); 149 150 /* Make sure something is there... */ 151 probe_addr = ca->ca_paddr + 1; 152 if (bus_peek(ca->ca_bustype, probe_addr, 1) == -1) 153 return (0); 154 155 /* 156 * If this is a VME SCSI board, we have to determine whether 157 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 158 * be determined using the fact that the "sc" board occupies 159 * 4K bytes in VME space but the "si" board occupies 2K bytes. 160 */ 161 /* Note: the "si" board should NOT respond here. */ 162 probe_addr = ca->ca_paddr + 0x801; 163 if (bus_peek(ca->ca_bustype, probe_addr, 1) != -1) { 164 /* Something responded at 2K+1. Maybe an "sc" board? */ 165 #ifdef DEBUG 166 printf("si_vme_match: May be an `sc' board at pa=0x%lx\n", 167 ca->ca_paddr); 168 #endif 169 return(0); 170 } 171 172 /* Default interrupt priority. */ 173 if (ca->ca_intpri == -1) 174 ca->ca_intpri = 2; 175 176 return (1); 177 } 178 179 static void 180 si_vme_attach(struct device *parent, struct device *self, void *args) 181 { 182 struct si_softc *sc = (struct si_softc *) self; 183 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 184 struct cfdata *cf = device_cfdata(self); 185 struct confargs *ca = args; 186 187 sc->sc_bst = ca->ca_bustag; 188 sc->sc_dmat = ca->ca_dmatag; 189 190 if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct si_regs), 0, 191 &sc->sc_bsh) != 0) { 192 printf(": can't map register\n"); 193 return; 194 } 195 sc->sc_regs = bus_space_vaddr(sc->sc_bst, sc->sc_bsh); 196 197 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 198 BUS_DMA_NOWAIT, &sc->sc_dmap) != 0) { 199 printf(": can't create DMA map\n"); 200 return; 201 } 202 203 /* Get options from config flags if specified. */ 204 if (cf->cf_flags) 205 sc->sc_options = cf->cf_flags; 206 else 207 sc->sc_options = si_vme_options; 208 209 printf(": options=0x%x\n", sc->sc_options); 210 211 sc->sc_adapter_type = ca->ca_bustype; 212 sc->sc_adapter_iv_am = VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 213 214 /* 215 * MD function pointers used by the MI code. 216 */ 217 ncr_sc->sc_pio_out = ncr5380_pio_out; 218 ncr_sc->sc_pio_in = ncr5380_pio_in; 219 ncr_sc->sc_dma_alloc = si_dma_alloc; 220 ncr_sc->sc_dma_free = si_dma_free; 221 ncr_sc->sc_dma_setup = si_vme_dma_setup; 222 ncr_sc->sc_dma_start = si_vme_dma_start; 223 ncr_sc->sc_dma_poll = si_dma_poll; 224 ncr_sc->sc_dma_eop = si_vme_dma_eop; 225 ncr_sc->sc_dma_stop = si_vme_dma_stop; 226 ncr_sc->sc_intr_on = si_vme_intr_on; 227 ncr_sc->sc_intr_off = si_vme_intr_off; 228 229 /* Attach interrupt handler. */ 230 isr_add_vectored(si_intr, (void *)sc, ca->ca_intpri, ca->ca_intvec); 231 232 /* Reset the hardware. */ 233 si_vme_reset(ncr_sc); 234 235 /* Do the common attach stuff. */ 236 si_attach(sc); 237 } 238 239 static void 240 si_vme_reset(struct ncr5380_softc *ncr_sc) 241 { 242 struct si_softc *sc = (struct si_softc *)ncr_sc; 243 volatile struct si_regs *si = sc->sc_regs; 244 245 #ifdef DEBUG 246 if (si_debug) { 247 printf("si_vme_reset\n"); 248 } 249 #endif 250 251 /* 252 * The SCSI3 controller has an 8K FIFO to buffer data between the 253 * 5380 and the DMA. Make sure it starts out empty. 254 * 255 * The reset bits in the CSR are active low. 256 */ 257 si->si_csr = 0; 258 delay(10); 259 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 260 delay(10); 261 si->fifo_count = 0; 262 263 /* Make sure the DMA engine is stopped. */ 264 si->dma_addrh = 0; 265 si->dma_addrl = 0; 266 si->dma_counth = 0; 267 si->dma_countl = 0; 268 si->si_iv_am = sc->sc_adapter_iv_am; 269 si->fifo_cnt_hi = 0; 270 } 271 272 /* 273 * This is called when the bus is going idle, 274 * so we want to enable the SBC interrupts. 275 * That is controlled by the DMA enable! 276 * Who would have guessed! 277 * What a NASTY trick! 278 */ 279 void 280 si_vme_intr_on(struct ncr5380_softc *ncr_sc) 281 { 282 struct si_softc *sc = (struct si_softc *)ncr_sc; 283 volatile struct si_regs *si = sc->sc_regs; 284 285 /* receive mode should be safer */ 286 si->si_csr &= ~SI_CSR_SEND; 287 288 /* Clear the count so nothing happens. */ 289 si->dma_counth = 0; 290 si->dma_countl = 0; 291 292 /* Clear the start address too. (paranoid?) */ 293 si->dma_addrh = 0; 294 si->dma_addrl = 0; 295 296 /* Finally, enable the DMA engine. */ 297 si->si_csr |= SI_CSR_DMA_EN; 298 } 299 300 /* 301 * This is called when the bus is idle and we are 302 * about to start playing with the SBC chip. 303 */ 304 void 305 si_vme_intr_off(struct ncr5380_softc *ncr_sc) 306 { 307 struct si_softc *sc = (struct si_softc *)ncr_sc; 308 volatile struct si_regs *si = sc->sc_regs; 309 310 si->si_csr &= ~SI_CSR_DMA_EN; 311 } 312 313 /* 314 * This function is called during the COMMAND or MSG_IN phase 315 * that precedes a DATA_IN or DATA_OUT phase, in case we need 316 * to setup the DMA engine before the bus enters a DATA phase. 317 * 318 * XXX: The VME adapter appears to suppress SBC interrupts 319 * when the FIFO is not empty or the FIFO count is non-zero! 320 * 321 * On the VME version, setup the start addres, but clear the 322 * count (to make sure it stays idle) and set that later. 323 */ 324 void 325 si_vme_dma_setup(struct ncr5380_softc *ncr_sc) 326 { 327 struct si_softc *sc = (struct si_softc *)ncr_sc; 328 struct sci_req *sr = ncr_sc->sc_current; 329 struct si_dma_handle *dh = sr->sr_dma_hand; 330 volatile struct si_regs *si = sc->sc_regs; 331 long data_pa; 332 int xlen; 333 334 /* 335 * Get the DVMA mapping for this segment. 336 * XXX - Should separate allocation and mapin. 337 */ 338 data_pa = dh->dh_dmaaddr; 339 if (data_pa & 1) 340 panic("si_dma_start: bad pa=0x%lx", data_pa); 341 xlen = dh->dh_dmalen; 342 xlen &= ~1; /* XXX: necessary? */ 343 sc->sc_reqlen = xlen; /* XXX: or less? */ 344 345 #ifdef DEBUG 346 if (si_debug & 2) { 347 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 348 dh, data_pa, xlen); 349 } 350 #endif 351 352 /* Set direction (send/recv) */ 353 if (dh->dh_flags & SIDH_OUT) { 354 si->si_csr |= SI_CSR_SEND; 355 } else { 356 si->si_csr &= ~SI_CSR_SEND; 357 } 358 359 /* Reset the FIFO. */ 360 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 361 si->si_csr |= SI_CSR_FIFO_RES; 362 363 if (data_pa & 2) { 364 si->si_csr |= SI_CSR_BPCON; 365 } else { 366 si->si_csr &= ~SI_CSR_BPCON; 367 } 368 369 /* Load the start address. */ 370 si->dma_addrh = (ushort)(data_pa >> 16); 371 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 372 373 /* 374 * Keep the count zero or it may start early! 375 */ 376 si->dma_counth = 0; 377 si->dma_countl = 0; 378 379 #if 0 380 /* Clear FIFO counter. (also hits dma_count) */ 381 si->fifo_cnt_hi = 0; 382 si->fifo_count = 0; 383 #endif 384 } 385 386 387 void 388 si_vme_dma_start(struct ncr5380_softc *ncr_sc) 389 { 390 struct si_softc *sc = (struct si_softc *)ncr_sc; 391 struct sci_req *sr = ncr_sc->sc_current; 392 struct si_dma_handle *dh = sr->sr_dma_hand; 393 volatile struct si_regs *si = sc->sc_regs; 394 int s, xlen; 395 396 xlen = sc->sc_reqlen; 397 398 /* This MAY be time critical (not sure). */ 399 s = splhigh(); 400 401 si->dma_counth = (ushort)(xlen >> 16); 402 si->dma_countl = (ushort)(xlen & 0xFFFF); 403 404 /* Set it anyway, even though dma_count hits it. */ 405 si->fifo_cnt_hi = (ushort)(xlen >> 16); 406 si->fifo_count = (ushort)(xlen & 0xFFFF); 407 408 /* 409 * Acknowledge the phase change. (After DMA setup!) 410 * Put the SBIC into DMA mode, and start the transfer. 411 */ 412 if (dh->dh_flags & SIDH_OUT) { 413 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 414 SCI_CLR_INTR(ncr_sc); 415 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 416 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 417 *ncr_sc->sci_dma_send = 0; /* start it */ 418 } else { 419 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 420 SCI_CLR_INTR(ncr_sc); 421 *ncr_sc->sci_icmd = 0; 422 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 423 *ncr_sc->sci_irecv = 0; /* start it */ 424 } 425 426 /* Let'er rip! */ 427 si->si_csr |= SI_CSR_DMA_EN; 428 429 splx(s); 430 ncr_sc->sc_state |= NCR_DOINGDMA; 431 432 #ifdef DEBUG 433 if (si_debug & 2) { 434 printf("si_dma_start: started, flags=0x%x\n", 435 ncr_sc->sc_state); 436 } 437 #endif 438 } 439 440 441 void 442 si_vme_dma_eop(struct ncr5380_softc *ncr_sc) 443 { 444 445 /* Not needed - DMA was stopped prior to examining sci_csr */ 446 } 447 448 449 void 450 si_vme_dma_stop(struct ncr5380_softc *ncr_sc) 451 { 452 struct si_softc *sc = (struct si_softc *)ncr_sc; 453 struct sci_req *sr = ncr_sc->sc_current; 454 struct si_dma_handle *dh = sr->sr_dma_hand; 455 volatile struct si_regs *si = sc->sc_regs; 456 int resid, ntrans; 457 458 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 459 #ifdef DEBUG 460 printf("si_dma_stop: DMA not running\n"); 461 #endif 462 return; 463 } 464 ncr_sc->sc_state &= ~NCR_DOINGDMA; 465 466 /* First, halt the DMA engine. */ 467 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 468 469 /* Set an impossible phase to prevent data movement? */ 470 *ncr_sc->sci_tcmd = PHASE_INVALID; 471 472 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 473 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 474 sr->sr_xs->error = XS_DRIVER_STUFFUP; 475 ncr_sc->sc_state |= NCR_ABORTING; 476 si_vme_reset(ncr_sc); 477 goto out; 478 } 479 480 /* Note that timeout may have set the error flag. */ 481 if (ncr_sc->sc_state & NCR_ABORTING) 482 goto out; 483 484 /* XXX: Wait for DMA to actually finish? */ 485 486 /* 487 * Now try to figure out how much actually transferred 488 * 489 * The fifo_count does not reflect how many bytes were 490 * actually transferred for VME. 491 * 492 * SCSI-3 VME interface is a little funny on writes: 493 * if we have a disconnect, the DMA has overshot by 494 * one byte and the resid needs to be incremented. 495 * Only happens for partial transfers. 496 * (Thanks to Matt Jacob) 497 */ 498 499 resid = si->fifo_count & 0xFFFF; 500 if (dh->dh_flags & SIDH_OUT) 501 if ((resid > 0) && (resid < sc->sc_reqlen)) 502 resid++; 503 ntrans = sc->sc_reqlen - resid; 504 505 #ifdef DEBUG 506 if (si_debug & 2) { 507 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 508 resid, ntrans); 509 } 510 #endif 511 512 if (ntrans < MIN_DMA_LEN) { 513 printf("si: fifo count: 0x%x\n", resid); 514 ncr_sc->sc_state |= NCR_ABORTING; 515 goto out; 516 } 517 if (ntrans > ncr_sc->sc_datalen) 518 panic("si_dma_stop: excess transfer"); 519 520 /* Adjust data pointer */ 521 ncr_sc->sc_dataptr += ntrans; 522 ncr_sc->sc_datalen -= ntrans; 523 524 /* 525 * After a read, we may need to clean-up 526 * "Left-over bytes" (yuck!) 527 */ 528 if (((dh->dh_flags & SIDH_OUT) == 0) && 529 ((si->si_csr & SI_CSR_LOB) != 0)) 530 { 531 char *cp = ncr_sc->sc_dataptr; 532 #ifdef DEBUG 533 printf("si: Got Left-over bytes!\n"); 534 #endif 535 if (si->si_csr & SI_CSR_BPCON) { 536 /* have SI_CSR_BPCON */ 537 cp[-1] = (si->si_bprl & 0xff00) >> 8; 538 } else { 539 switch (si->si_csr & SI_CSR_LOB) { 540 case SI_CSR_LOB_THREE: 541 cp[-3] = (si->si_bprh & 0xff00) >> 8; 542 cp[-2] = (si->si_bprh & 0x00ff); 543 cp[-1] = (si->si_bprl & 0xff00) >> 8; 544 break; 545 case SI_CSR_LOB_TWO: 546 cp[-2] = (si->si_bprh & 0xff00) >> 8; 547 cp[-1] = (si->si_bprh & 0x00ff); 548 break; 549 case SI_CSR_LOB_ONE: 550 cp[-1] = (si->si_bprh & 0xff00) >> 8; 551 break; 552 } 553 } 554 } 555 556 out: 557 si->dma_addrh = 0; 558 si->dma_addrl = 0; 559 560 si->dma_counth = 0; 561 si->dma_countl = 0; 562 563 si->fifo_cnt_hi = 0; 564 si->fifo_count = 0; 565 566 /* Put SBIC back in PIO mode. */ 567 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 568 *ncr_sc->sci_icmd = 0; 569 } 570