1 /* $NetBSD: si_vme.c,v 1.2 1996/06/17 23:21:39 gwr Exp $ */ 2 3 /* 4 * Copyright (c) 1995 David Jones, Gordon W. Ross 5 * Copyright (c) 1994 Adam Glass 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the authors may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by 21 * Adam Glass, David Jones, and Gordon Ross 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * This file contains only the machine-dependent parts of the 37 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 38 * The machine-independent parts are in ncr5380sbc.c 39 * 40 * Supported hardware includes: 41 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 42 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 43 * 44 * Could be made to support the Sun3/E if someone wanted to. 45 * 46 * Note: Both supported variants of the Sun SCSI-3 adapter have 47 * some really unusual "features" for this driver to deal with, 48 * generally related to the DMA engine. The OBIO variant will 49 * ignore any attempt to write the FIFO count register while the 50 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 51 * by setting the FIFO count early in COMMAND or MSG_IN phase. 52 * 53 * The VME variant has a bit to enable or disable the DMA engine, 54 * but that bit also gates the interrupt line from the NCR5380! 55 * Therefore, in order to get any interrupt from the 5380, (i.e. 56 * for reselect) one must clear the DMA engine transfer count and 57 * then enable DMA. This has the further complication that you 58 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 59 * we have to turn DMA back off before we even look at the 5380. 60 * 61 * What wonderfully whacky hardware this is! 62 * 63 * Credits, history: 64 * 65 * David Jones wrote the initial version of this module, which 66 * included support for the VME adapter only. (no reselection). 67 * 68 * Gordon Ross added support for the OBIO adapter, and re-worked 69 * both the VME and OBIO code to support disconnect/reselect. 70 * (Required figuring out the hardware "features" noted above.) 71 * 72 * The autoconfiguration boilerplate came from Adam Glass. 73 */ 74 75 /***************************************************************** 76 * VME functions for DMA 77 ****************************************************************/ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <scsi/scsi_all.h> 90 #include <scsi/scsi_debug.h> 91 #include <scsi/scsiconf.h> 92 93 #include <machine/autoconf.h> 94 #include <machine/isr.h> 95 #include <machine/obio.h> 96 #include <machine/dvma.h> 97 98 #define DEBUG XXX 99 100 #include <dev/ic/ncr5380reg.h> 101 #include <dev/ic/ncr5380var.h> 102 103 #include "sireg.h" 104 #include "sivar.h" 105 106 /* 107 * Transfers smaller than this are done using PIO 108 * (on assumption they're not worth DMA overhead) 109 */ 110 #define MIN_DMA_LEN 128 111 112 void si_vme_dma_setup __P((struct ncr5380_softc *)); 113 void si_vme_dma_start __P((struct ncr5380_softc *)); 114 void si_vme_dma_eop __P((struct ncr5380_softc *)); 115 void si_vme_dma_stop __P((struct ncr5380_softc *)); 116 117 void si_vme_intr_on __P((struct ncr5380_softc *)); 118 void si_vme_intr_off __P((struct ncr5380_softc *)); 119 120 /* 121 * New-style autoconfig attachment 122 */ 123 124 static int si_vmes_match __P((struct device *, void *, void *)); 125 static void si_vmes_attach __P((struct device *, struct device *, void *)); 126 127 struct cfattach si_vmes_ca = { 128 sizeof(struct si_softc), si_vmes_match, si_vmes_attach 129 }; 130 131 /* Options. Interesting values are: 1,3,7 */ 132 int si_vme_options = 3; 133 #define SI_ENABLE_DMA 1 /* Use DMA (maybe polled) */ 134 #define SI_DMA_INTR 2 /* DMA completion interrupts */ 135 #define SI_DO_RESELECT 4 /* Allow disconnect/reselect */ 136 137 138 static int 139 si_vmes_match(parent, vcf, args) 140 struct device *parent; 141 void *vcf, *args; 142 { 143 struct cfdata *cf = vcf; 144 struct confargs *ca = args; 145 int x, probe_addr; 146 147 #ifdef DIAGNOSTIC 148 if (ca->ca_bustype != BUS_VME16) { 149 printf("si_vmes_match: bustype %d?\n", ca->ca_bustype); 150 return (0); 151 } 152 #endif 153 154 if ((cpu_machine_id == SUN3_MACH_50) || 155 (cpu_machine_id == SUN3_MACH_60) ) 156 { 157 /* Sun3/50 or Sun3/60 do not have VME. */ 158 return(0); 159 } 160 161 /* 162 * Other Sun3 models may have VME "si" or "sc". 163 * This driver has no default address. 164 */ 165 if (ca->ca_paddr == -1) 166 return (0); 167 168 /* Default interrupt priority always splbio==2 */ 169 if (ca->ca_intpri == -1) 170 ca->ca_intpri = 2; 171 172 /* Make sure there is something there... */ 173 x = bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1); 174 if (x == -1) 175 return (0); 176 177 /* 178 * If this is a VME SCSI board, we have to determine whether 179 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 180 * be determined using the fact that the "sc" board occupies 181 * 4K bytes in VME space but the "si" board occupies 2K bytes. 182 */ 183 /* Note: the "si" board should NOT respond here. */ 184 x = bus_peek(ca->ca_bustype, ca->ca_paddr + 0x801, 1); 185 if (x != -1) { 186 /* Something responded at 2K+1. Maybe an "sc" board? */ 187 #ifdef DEBUG 188 printf("si_vmes_match: May be an `sc' board at pa=0x%x\n", 189 ca->ca_paddr); 190 #endif 191 return(0); 192 } 193 194 return (1); 195 } 196 197 198 static void 199 si_vmes_attach(parent, self, args) 200 struct device *parent, *self; 201 void *args; 202 { 203 struct si_softc *sc = (struct si_softc *) self; 204 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)sc; 205 struct confargs *ca = args; 206 int s; 207 208 /* XXX: Get options from flags... */ 209 printf(" : options=%d\n", si_vme_options); 210 211 ncr_sc->sc_flags = 0; 212 if (si_vme_options & SI_DO_RESELECT) 213 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 214 if ((si_vme_options & SI_DMA_INTR) == 0) 215 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 216 217 sc->sc_adapter_type = ca->ca_bustype; 218 sc->sc_adapter_iv_am = 219 VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 220 221 sc->sc_regs = (struct si_regs *) 222 bus_mapin(ca->ca_bustype, ca->ca_paddr, 223 sizeof(struct si_regs)); 224 225 /* 226 * MD function pointers used by the MI code. 227 */ 228 ncr_sc->sc_pio_out = ncr5380_pio_out; 229 ncr_sc->sc_pio_in = ncr5380_pio_in; 230 231 ncr_sc->sc_dma_alloc = si_dma_alloc; 232 ncr_sc->sc_dma_free = si_dma_free; 233 ncr_sc->sc_dma_setup = si_vme_dma_setup; 234 ncr_sc->sc_dma_start = si_vme_dma_start; 235 ncr_sc->sc_dma_poll = si_dma_poll; 236 ncr_sc->sc_dma_eop = si_vme_dma_eop; 237 ncr_sc->sc_dma_stop = si_vme_dma_stop; 238 ncr_sc->sc_intr_on = si_vme_intr_on; 239 ncr_sc->sc_intr_off = si_vme_intr_off; 240 241 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 242 243 #if 1 /* XXX - Temporary */ 244 /* XXX - In case we think DMA is completely broken... */ 245 if ((si_vme_options & SI_ENABLE_DMA) == 0) { 246 /* Override this function pointer. */ 247 ncr_sc->sc_dma_alloc = NULL; 248 } 249 #endif 250 251 /* Attach interrupt handler. */ 252 isr_add_vectored(si_intr, (void *)sc, 253 ca->ca_intpri, ca->ca_intvec); 254 255 /* Do the common attach stuff. */ 256 si_attach(sc); 257 } 258 259 260 /* 261 * This is called when the bus is going idle, 262 * so we want to enable the SBC interrupts. 263 * That is controlled by the DMA enable! 264 * Who would have guessed! 265 * What a NASTY trick! 266 */ 267 void 268 si_vme_intr_on(ncr_sc) 269 struct ncr5380_softc *ncr_sc; 270 { 271 struct si_softc *sc = (struct si_softc *)ncr_sc; 272 volatile struct si_regs *si = sc->sc_regs; 273 274 /* receive mode should be safer */ 275 si->si_csr &= ~SI_CSR_SEND; 276 277 /* Clear the count so nothing happens. */ 278 si->dma_counth = 0; 279 si->dma_countl = 0; 280 281 /* Clear the start address too. (paranoid?) */ 282 si->dma_addrh = 0; 283 si->dma_addrl = 0; 284 285 /* Finally, enable the DMA engine. */ 286 si->si_csr |= SI_CSR_DMA_EN; 287 } 288 289 /* 290 * This is called when the bus is idle and we are 291 * about to start playing with the SBC chip. 292 */ 293 void 294 si_vme_intr_off(ncr_sc) 295 struct ncr5380_softc *ncr_sc; 296 { 297 struct si_softc *sc = (struct si_softc *)ncr_sc; 298 volatile struct si_regs *si = sc->sc_regs; 299 300 si->si_csr &= ~SI_CSR_DMA_EN; 301 } 302 303 /* 304 * This function is called during the COMMAND or MSG_IN phase 305 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 306 * to setup the DMA engine before the bus enters a DATA phase. 307 * 308 * XXX: The VME adapter appears to suppress SBC interrupts 309 * when the FIFO is not empty or the FIFO count is non-zero! 310 * 311 * On the VME version, setup the start addres, but clear the 312 * count (to make sure it stays idle) and set that later. 313 */ 314 void 315 si_vme_dma_setup(ncr_sc) 316 struct ncr5380_softc *ncr_sc; 317 { 318 struct si_softc *sc = (struct si_softc *)ncr_sc; 319 struct sci_req *sr = ncr_sc->sc_current; 320 struct si_dma_handle *dh = sr->sr_dma_hand; 321 volatile struct si_regs *si = sc->sc_regs; 322 long data_pa; 323 int xlen; 324 325 /* 326 * Get the DVMA mapping for this segment. 327 * XXX - Should separate allocation and mapin. 328 */ 329 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 330 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 331 if (data_pa & 1) 332 panic("si_dma_start: bad pa=0x%x", data_pa); 333 xlen = ncr_sc->sc_datalen; 334 xlen &= ~1; /* XXX: necessary? */ 335 sc->sc_reqlen = xlen; /* XXX: or less? */ 336 337 #ifdef DEBUG 338 if (si_debug & 2) { 339 printf("si_dma_setup: dh=0x%x, pa=0x%x, xlen=%d\n", 340 dh, data_pa, xlen); 341 } 342 #endif 343 344 /* Set direction (send/recv) */ 345 if (dh->dh_flags & SIDH_OUT) { 346 si->si_csr |= SI_CSR_SEND; 347 } else { 348 si->si_csr &= ~SI_CSR_SEND; 349 } 350 351 /* Reset the FIFO. */ 352 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 353 si->si_csr |= SI_CSR_FIFO_RES; 354 355 if (data_pa & 2) { 356 si->si_csr |= SI_CSR_BPCON; 357 } else { 358 si->si_csr &= ~SI_CSR_BPCON; 359 } 360 361 /* Load the start address. */ 362 si->dma_addrh = (ushort)(data_pa >> 16); 363 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 364 365 /* 366 * Keep the count zero or it may start early! 367 */ 368 si->dma_counth = 0; 369 si->dma_countl = 0; 370 371 #if 0 372 /* Clear FIFO counter. (also hits dma_count) */ 373 si->fifo_cnt_hi = 0; 374 si->fifo_count = 0; 375 #endif 376 } 377 378 379 void 380 si_vme_dma_start(ncr_sc) 381 struct ncr5380_softc *ncr_sc; 382 { 383 struct si_softc *sc = (struct si_softc *)ncr_sc; 384 struct sci_req *sr = ncr_sc->sc_current; 385 struct si_dma_handle *dh = sr->sr_dma_hand; 386 volatile struct si_regs *si = sc->sc_regs; 387 long data_pa; 388 int s, xlen; 389 390 xlen = sc->sc_reqlen; 391 392 /* This MAY be time critical (not sure). */ 393 s = splhigh(); 394 395 si->dma_counth = (ushort)(xlen >> 16); 396 si->dma_countl = (ushort)(xlen & 0xFFFF); 397 398 /* Set it anyway, even though dma_count hits it. */ 399 si->fifo_cnt_hi = (ushort)(xlen >> 16); 400 si->fifo_count = (ushort)(xlen & 0xFFFF); 401 402 /* 403 * Acknowledge the phase change. (After DMA setup!) 404 * Put the SBIC into DMA mode, and start the transfer. 405 */ 406 if (dh->dh_flags & SIDH_OUT) { 407 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 408 SCI_CLR_INTR(ncr_sc); 409 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 410 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 411 *ncr_sc->sci_dma_send = 0; /* start it */ 412 } else { 413 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 414 SCI_CLR_INTR(ncr_sc); 415 *ncr_sc->sci_icmd = 0; 416 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 417 *ncr_sc->sci_irecv = 0; /* start it */ 418 } 419 420 /* Let'er rip! */ 421 si->si_csr |= SI_CSR_DMA_EN; 422 423 splx(s); 424 ncr_sc->sc_state |= NCR_DOINGDMA; 425 426 #ifdef DEBUG 427 if (si_debug & 2) { 428 printf("si_dma_start: started, flags=0x%x\n", 429 ncr_sc->sc_state); 430 } 431 #endif 432 } 433 434 435 void 436 si_vme_dma_eop(ncr_sc) 437 struct ncr5380_softc *ncr_sc; 438 { 439 440 /* Not needed - DMA was stopped prior to examining sci_csr */ 441 } 442 443 444 void 445 si_vme_dma_stop(ncr_sc) 446 struct ncr5380_softc *ncr_sc; 447 { 448 struct si_softc *sc = (struct si_softc *)ncr_sc; 449 struct sci_req *sr = ncr_sc->sc_current; 450 struct si_dma_handle *dh = sr->sr_dma_hand; 451 volatile struct si_regs *si = sc->sc_regs; 452 int resid, ntrans; 453 454 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 455 #ifdef DEBUG 456 printf("si_dma_stop: dma not running\n"); 457 #endif 458 return; 459 } 460 ncr_sc->sc_state &= ~NCR_DOINGDMA; 461 462 /* First, halt the DMA engine. */ 463 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 464 465 /* Set an impossible phase to prevent data movement? */ 466 *ncr_sc->sci_tcmd = PHASE_INVALID; 467 468 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 469 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 470 sr->sr_xs->error = XS_DRIVER_STUFFUP; 471 ncr_sc->sc_state |= NCR_ABORTING; 472 si_reset_adapter(ncr_sc); 473 goto out; 474 } 475 476 /* Note that timeout may have set the error flag. */ 477 if (ncr_sc->sc_state & NCR_ABORTING) 478 goto out; 479 480 /* XXX: Wait for DMA to actually finish? */ 481 482 /* 483 * Now try to figure out how much actually transferred 484 * 485 * The fifo_count does not reflect how many bytes were 486 * actually transferred for VME. 487 * 488 * SCSI-3 VME interface is a little funny on writes: 489 * if we have a disconnect, the dma has overshot by 490 * one byte and the resid needs to be incremented. 491 * Only happens for partial transfers. 492 * (Thanks to Matt Jacob) 493 */ 494 495 resid = si->fifo_count & 0xFFFF; 496 if (dh->dh_flags & SIDH_OUT) 497 if ((resid > 0) && (resid < sc->sc_reqlen)) 498 resid++; 499 ntrans = sc->sc_reqlen - resid; 500 501 #ifdef DEBUG 502 if (si_debug & 2) { 503 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 504 resid, ntrans); 505 } 506 #endif 507 508 if (ntrans < MIN_DMA_LEN) { 509 printf("si: fifo count: 0x%x\n", resid); 510 ncr_sc->sc_state |= NCR_ABORTING; 511 goto out; 512 } 513 if (ntrans > ncr_sc->sc_datalen) 514 panic("si_dma_stop: excess transfer"); 515 516 /* Adjust data pointer */ 517 ncr_sc->sc_dataptr += ntrans; 518 ncr_sc->sc_datalen -= ntrans; 519 520 /* 521 * After a read, we may need to clean-up 522 * "Left-over bytes" (yuck!) 523 */ 524 if (((dh->dh_flags & SIDH_OUT) == 0) && 525 ((si->si_csr & SI_CSR_LOB) != 0)) 526 { 527 char *cp = ncr_sc->sc_dataptr; 528 #ifdef DEBUG 529 printf("si: Got Left-over bytes!\n"); 530 #endif 531 if (si->si_csr & SI_CSR_BPCON) { 532 /* have SI_CSR_BPCON */ 533 cp[-1] = (si->si_bprl & 0xff00) >> 8; 534 } else { 535 switch (si->si_csr & SI_CSR_LOB) { 536 case SI_CSR_LOB_THREE: 537 cp[-3] = (si->si_bprh & 0xff00) >> 8; 538 cp[-2] = (si->si_bprh & 0x00ff); 539 cp[-1] = (si->si_bprl & 0xff00) >> 8; 540 break; 541 case SI_CSR_LOB_TWO: 542 cp[-2] = (si->si_bprh & 0xff00) >> 8; 543 cp[-1] = (si->si_bprh & 0x00ff); 544 break; 545 case SI_CSR_LOB_ONE: 546 cp[-1] = (si->si_bprh & 0xff00) >> 8; 547 break; 548 } 549 } 550 } 551 552 out: 553 si->dma_addrh = 0; 554 si->dma_addrl = 0; 555 556 si->dma_counth = 0; 557 si->dma_countl = 0; 558 559 si->fifo_cnt_hi = 0; 560 si->fifo_count = 0; 561 562 /* Put SBIC back in PIO mode. */ 563 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 564 *ncr_sc->sci_icmd = 0; 565 } 566