1 /* $NetBSD: si_vme.c,v 1.22 2003/07/15 03:36:15 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * VME functions for DMA 81 ****************************************************************/ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: si_vme.c,v 1.22 2003/07/15 03:36:15 lukem Exp $"); 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/errno.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/device.h> 92 #include <sys/buf.h> 93 #include <sys/proc.h> 94 #include <sys/user.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsipi_debug.h> 99 #include <dev/scsipi/scsiconf.h> 100 101 #include <machine/autoconf.h> 102 #include <machine/dvma.h> 103 104 /* #define DEBUG XXX */ 105 106 #include <dev/ic/ncr5380reg.h> 107 #include <dev/ic/ncr5380var.h> 108 109 #include "sireg.h" 110 #include "sivar.h" 111 112 void si_vme_dma_setup __P((struct ncr5380_softc *)); 113 void si_vme_dma_start __P((struct ncr5380_softc *)); 114 void si_vme_dma_eop __P((struct ncr5380_softc *)); 115 void si_vme_dma_stop __P((struct ncr5380_softc *)); 116 117 void si_vme_intr_on __P((struct ncr5380_softc *)); 118 void si_vme_intr_off __P((struct ncr5380_softc *)); 119 120 static void si_vme_reset __P((struct ncr5380_softc *)); 121 122 /* 123 * New-style autoconfig attachment 124 */ 125 126 static int si_vme_match __P((struct device *, struct cfdata *, void *)); 127 static void si_vme_attach __P((struct device *, struct device *, void *)); 128 129 CFATTACH_DECL(si_vme, sizeof(struct si_softc), 130 si_vme_match, si_vme_attach, NULL, NULL); 131 132 /* 133 * Options for disconnect/reselect, DMA, and interrupts. 134 * By default, allow disconnect/reselect on targets 4-6. 135 * Those are normally tapes that really need it enabled. 136 */ 137 int si_vme_options = 0x0f; 138 139 140 static int 141 si_vme_match(parent, cf, aux) 142 struct device *parent; 143 struct cfdata *cf; 144 void *aux; 145 { 146 struct confargs *ca = aux; 147 int probe_addr; 148 149 /* No default VME address. */ 150 if (ca->ca_paddr == -1) 151 return (0); 152 153 /* Make sure something is there... */ 154 probe_addr = ca->ca_paddr + 1; 155 if (bus_peek(ca->ca_bustype, probe_addr, 1) == -1) 156 return (0); 157 158 /* 159 * If this is a VME SCSI board, we have to determine whether 160 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 161 * be determined using the fact that the "sc" board occupies 162 * 4K bytes in VME space but the "si" board occupies 2K bytes. 163 */ 164 /* Note: the "si" board should NOT respond here. */ 165 probe_addr = ca->ca_paddr + 0x801; 166 if (bus_peek(ca->ca_bustype, probe_addr, 1) != -1) { 167 /* Something responded at 2K+1. Maybe an "sc" board? */ 168 #ifdef DEBUG 169 printf("si_vme_match: May be an `sc' board at pa=0x%x\n", 170 ca->ca_paddr); 171 #endif 172 return(0); 173 } 174 175 /* Default interrupt priority. */ 176 if (ca->ca_intpri == -1) 177 ca->ca_intpri = 2; 178 179 return (1); 180 } 181 182 static void 183 si_vme_attach(parent, self, args) 184 struct device *parent, *self; 185 void *args; 186 { 187 struct si_softc *sc = (struct si_softc *) self; 188 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 189 struct cfdata *cf = self->dv_cfdata; 190 struct confargs *ca = args; 191 192 /* Get options from config flags if specified. */ 193 if (cf->cf_flags) 194 sc->sc_options = cf->cf_flags; 195 else 196 sc->sc_options = si_vme_options; 197 198 printf(": options=0x%x\n", sc->sc_options); 199 200 sc->sc_adapter_type = ca->ca_bustype; 201 sc->sc_regs = (struct si_regs *) 202 bus_mapin(ca->ca_bustype, ca->ca_paddr, 203 sizeof(struct si_regs)); 204 sc->sc_adapter_iv_am = 205 VME_SUPV_DATA_24 | (ca->ca_intvec & 0xFF); 206 207 /* 208 * MD function pointers used by the MI code. 209 */ 210 ncr_sc->sc_pio_out = ncr5380_pio_out; 211 ncr_sc->sc_pio_in = ncr5380_pio_in; 212 ncr_sc->sc_dma_alloc = si_dma_alloc; 213 ncr_sc->sc_dma_free = si_dma_free; 214 ncr_sc->sc_dma_setup = si_vme_dma_setup; 215 ncr_sc->sc_dma_start = si_vme_dma_start; 216 ncr_sc->sc_dma_poll = si_dma_poll; 217 ncr_sc->sc_dma_eop = si_vme_dma_eop; 218 ncr_sc->sc_dma_stop = si_vme_dma_stop; 219 ncr_sc->sc_intr_on = si_vme_intr_on; 220 ncr_sc->sc_intr_off = si_vme_intr_off; 221 222 /* Attach interrupt handler. */ 223 isr_add_vectored(si_intr, (void *)sc, 224 ca->ca_intpri, ca->ca_intvec); 225 226 /* Reset the hardware. */ 227 si_vme_reset(ncr_sc); 228 229 /* Do the common attach stuff. */ 230 si_attach(sc); 231 } 232 233 static void 234 si_vme_reset(struct ncr5380_softc *ncr_sc) 235 { 236 struct si_softc *sc = (struct si_softc *)ncr_sc; 237 volatile struct si_regs *si = sc->sc_regs; 238 239 #ifdef DEBUG 240 if (si_debug) { 241 printf("si_vme_reset\n"); 242 } 243 #endif 244 245 /* 246 * The SCSI3 controller has an 8K FIFO to buffer data between the 247 * 5380 and the DMA. Make sure it starts out empty. 248 * 249 * The reset bits in the CSR are active low. 250 */ 251 si->si_csr = 0; 252 delay(10); 253 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 254 delay(10); 255 si->fifo_count = 0; 256 257 /* Make sure the DMA engine is stopped. */ 258 si->dma_addrh = 0; 259 si->dma_addrl = 0; 260 si->dma_counth = 0; 261 si->dma_countl = 0; 262 si->si_iv_am = sc->sc_adapter_iv_am; 263 si->fifo_cnt_hi = 0; 264 } 265 266 /* 267 * This is called when the bus is going idle, 268 * so we want to enable the SBC interrupts. 269 * That is controlled by the DMA enable! 270 * Who would have guessed! 271 * What a NASTY trick! 272 */ 273 void 274 si_vme_intr_on(ncr_sc) 275 struct ncr5380_softc *ncr_sc; 276 { 277 struct si_softc *sc = (struct si_softc *)ncr_sc; 278 volatile struct si_regs *si = sc->sc_regs; 279 280 /* receive mode should be safer */ 281 si->si_csr &= ~SI_CSR_SEND; 282 283 /* Clear the count so nothing happens. */ 284 si->dma_counth = 0; 285 si->dma_countl = 0; 286 287 /* Clear the start address too. (paranoid?) */ 288 si->dma_addrh = 0; 289 si->dma_addrl = 0; 290 291 /* Finally, enable the DMA engine. */ 292 si->si_csr |= SI_CSR_DMA_EN; 293 } 294 295 /* 296 * This is called when the bus is idle and we are 297 * about to start playing with the SBC chip. 298 */ 299 void 300 si_vme_intr_off(ncr_sc) 301 struct ncr5380_softc *ncr_sc; 302 { 303 struct si_softc *sc = (struct si_softc *)ncr_sc; 304 volatile struct si_regs *si = sc->sc_regs; 305 306 si->si_csr &= ~SI_CSR_DMA_EN; 307 } 308 309 /* 310 * This function is called during the COMMAND or MSG_IN phase 311 * that precedes a DATA_IN or DATA_OUT phase, in case we need 312 * to setup the DMA engine before the bus enters a DATA phase. 313 * 314 * XXX: The VME adapter appears to suppress SBC interrupts 315 * when the FIFO is not empty or the FIFO count is non-zero! 316 * 317 * On the VME version, setup the start addres, but clear the 318 * count (to make sure it stays idle) and set that later. 319 */ 320 void 321 si_vme_dma_setup(ncr_sc) 322 struct ncr5380_softc *ncr_sc; 323 { 324 struct si_softc *sc = (struct si_softc *)ncr_sc; 325 struct sci_req *sr = ncr_sc->sc_current; 326 struct si_dma_handle *dh = sr->sr_dma_hand; 327 volatile struct si_regs *si = sc->sc_regs; 328 long data_pa; 329 int xlen; 330 331 /* 332 * Get the DVMA mapping for this segment. 333 * XXX - Should separate allocation and mapin. 334 */ 335 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 336 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 337 if (data_pa & 1) 338 panic("si_dma_start: bad pa=0x%lx", data_pa); 339 xlen = ncr_sc->sc_datalen; 340 xlen &= ~1; /* XXX: necessary? */ 341 sc->sc_reqlen = xlen; /* XXX: or less? */ 342 343 #ifdef DEBUG 344 if (si_debug & 2) { 345 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 346 dh, data_pa, xlen); 347 } 348 #endif 349 350 /* Set direction (send/recv) */ 351 if (dh->dh_flags & SIDH_OUT) { 352 si->si_csr |= SI_CSR_SEND; 353 } else { 354 si->si_csr &= ~SI_CSR_SEND; 355 } 356 357 /* Reset the FIFO. */ 358 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 359 si->si_csr |= SI_CSR_FIFO_RES; 360 361 if (data_pa & 2) { 362 si->si_csr |= SI_CSR_BPCON; 363 } else { 364 si->si_csr &= ~SI_CSR_BPCON; 365 } 366 367 /* Load the start address. */ 368 si->dma_addrh = (ushort)(data_pa >> 16); 369 si->dma_addrl = (ushort)(data_pa & 0xFFFF); 370 371 /* 372 * Keep the count zero or it may start early! 373 */ 374 si->dma_counth = 0; 375 si->dma_countl = 0; 376 377 #if 0 378 /* Clear FIFO counter. (also hits dma_count) */ 379 si->fifo_cnt_hi = 0; 380 si->fifo_count = 0; 381 #endif 382 } 383 384 385 void 386 si_vme_dma_start(ncr_sc) 387 struct ncr5380_softc *ncr_sc; 388 { 389 struct si_softc *sc = (struct si_softc *)ncr_sc; 390 struct sci_req *sr = ncr_sc->sc_current; 391 struct si_dma_handle *dh = sr->sr_dma_hand; 392 volatile struct si_regs *si = sc->sc_regs; 393 int s, xlen; 394 395 xlen = sc->sc_reqlen; 396 397 /* This MAY be time critical (not sure). */ 398 s = splhigh(); 399 400 si->dma_counth = (ushort)(xlen >> 16); 401 si->dma_countl = (ushort)(xlen & 0xFFFF); 402 403 /* Set it anyway, even though dma_count hits it. */ 404 si->fifo_cnt_hi = (ushort)(xlen >> 16); 405 si->fifo_count = (ushort)(xlen & 0xFFFF); 406 407 /* 408 * Acknowledge the phase change. (After DMA setup!) 409 * Put the SBIC into DMA mode, and start the transfer. 410 */ 411 if (dh->dh_flags & SIDH_OUT) { 412 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 413 SCI_CLR_INTR(ncr_sc); 414 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 415 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 416 *ncr_sc->sci_dma_send = 0; /* start it */ 417 } else { 418 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 419 SCI_CLR_INTR(ncr_sc); 420 *ncr_sc->sci_icmd = 0; 421 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 422 *ncr_sc->sci_irecv = 0; /* start it */ 423 } 424 425 /* Let'er rip! */ 426 si->si_csr |= SI_CSR_DMA_EN; 427 428 splx(s); 429 ncr_sc->sc_state |= NCR_DOINGDMA; 430 431 #ifdef DEBUG 432 if (si_debug & 2) { 433 printf("si_dma_start: started, flags=0x%x\n", 434 ncr_sc->sc_state); 435 } 436 #endif 437 } 438 439 440 void 441 si_vme_dma_eop(ncr_sc) 442 struct ncr5380_softc *ncr_sc; 443 { 444 445 /* Not needed - DMA was stopped prior to examining sci_csr */ 446 } 447 448 449 void 450 si_vme_dma_stop(ncr_sc) 451 struct ncr5380_softc *ncr_sc; 452 { 453 struct si_softc *sc = (struct si_softc *)ncr_sc; 454 struct sci_req *sr = ncr_sc->sc_current; 455 struct si_dma_handle *dh = sr->sr_dma_hand; 456 volatile struct si_regs *si = sc->sc_regs; 457 int resid, ntrans; 458 459 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 460 #ifdef DEBUG 461 printf("si_dma_stop: DMA not running\n"); 462 #endif 463 return; 464 } 465 ncr_sc->sc_state &= ~NCR_DOINGDMA; 466 467 /* First, halt the DMA engine. */ 468 si->si_csr &= ~SI_CSR_DMA_EN; /* VME only */ 469 470 /* Set an impossible phase to prevent data movement? */ 471 *ncr_sc->sci_tcmd = PHASE_INVALID; 472 473 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 474 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 475 sr->sr_xs->error = XS_DRIVER_STUFFUP; 476 ncr_sc->sc_state |= NCR_ABORTING; 477 si_vme_reset(ncr_sc); 478 goto out; 479 } 480 481 /* Note that timeout may have set the error flag. */ 482 if (ncr_sc->sc_state & NCR_ABORTING) 483 goto out; 484 485 /* XXX: Wait for DMA to actually finish? */ 486 487 /* 488 * Now try to figure out how much actually transferred 489 * 490 * The fifo_count does not reflect how many bytes were 491 * actually transferred for VME. 492 * 493 * SCSI-3 VME interface is a little funny on writes: 494 * if we have a disconnect, the DMA has overshot by 495 * one byte and the resid needs to be incremented. 496 * Only happens for partial transfers. 497 * (Thanks to Matt Jacob) 498 */ 499 500 resid = si->fifo_count & 0xFFFF; 501 if (dh->dh_flags & SIDH_OUT) 502 if ((resid > 0) && (resid < sc->sc_reqlen)) 503 resid++; 504 ntrans = sc->sc_reqlen - resid; 505 506 #ifdef DEBUG 507 if (si_debug & 2) { 508 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 509 resid, ntrans); 510 } 511 #endif 512 513 if (ntrans < MIN_DMA_LEN) { 514 printf("si: fifo count: 0x%x\n", resid); 515 ncr_sc->sc_state |= NCR_ABORTING; 516 goto out; 517 } 518 if (ntrans > ncr_sc->sc_datalen) 519 panic("si_dma_stop: excess transfer"); 520 521 /* Adjust data pointer */ 522 ncr_sc->sc_dataptr += ntrans; 523 ncr_sc->sc_datalen -= ntrans; 524 525 /* 526 * After a read, we may need to clean-up 527 * "Left-over bytes" (yuck!) 528 */ 529 if (((dh->dh_flags & SIDH_OUT) == 0) && 530 ((si->si_csr & SI_CSR_LOB) != 0)) 531 { 532 char *cp = ncr_sc->sc_dataptr; 533 #ifdef DEBUG 534 printf("si: Got Left-over bytes!\n"); 535 #endif 536 if (si->si_csr & SI_CSR_BPCON) { 537 /* have SI_CSR_BPCON */ 538 cp[-1] = (si->si_bprl & 0xff00) >> 8; 539 } else { 540 switch (si->si_csr & SI_CSR_LOB) { 541 case SI_CSR_LOB_THREE: 542 cp[-3] = (si->si_bprh & 0xff00) >> 8; 543 cp[-2] = (si->si_bprh & 0x00ff); 544 cp[-1] = (si->si_bprl & 0xff00) >> 8; 545 break; 546 case SI_CSR_LOB_TWO: 547 cp[-2] = (si->si_bprh & 0xff00) >> 8; 548 cp[-1] = (si->si_bprh & 0x00ff); 549 break; 550 case SI_CSR_LOB_ONE: 551 cp[-1] = (si->si_bprh & 0xff00) >> 8; 552 break; 553 } 554 } 555 } 556 557 out: 558 si->dma_addrh = 0; 559 si->dma_addrl = 0; 560 561 si->dma_counth = 0; 562 si->dma_countl = 0; 563 564 si->fifo_cnt_hi = 0; 565 si->fifo_count = 0; 566 567 /* Put SBIC back in PIO mode. */ 568 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 569 *ncr_sc->sci_icmd = 0; 570 } 571