xref: /netbsd-src/sys/arch/sun3/dev/si_sebuf.c (revision 4472dbe5e3bd91ef2540bada7a7ca7384627ff9b)
1 /*	$NetBSD: si_sebuf.c,v 1.12 2000/04/01 14:38:43 tsutsui Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Sun3/E SCSI driver (machine-dependent portion).
41  * The machine-independent parts are in ncr5380sbc.c
42  *
43  * XXX - Mostly from the si driver.  Merge?
44  */
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/errno.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/device.h>
52 #include <sys/buf.h>
53 #include <sys/proc.h>
54 #include <sys/user.h>
55 
56 #include <dev/scsipi/scsi_all.h>
57 #include <dev/scsipi/scsipi_all.h>
58 #include <dev/scsipi/scsipi_debug.h>
59 #include <dev/scsipi/scsiconf.h>
60 
61 #include <machine/autoconf.h>
62 
63 /* #define DEBUG XXX */
64 
65 #include <dev/ic/ncr5380reg.h>
66 #include <dev/ic/ncr5380var.h>
67 
68 #include "sereg.h"
69 #include "sevar.h"
70 
71 /*
72  * Transfers smaller than this are done using PIO
73  * (on assumption they're not worth DMA overhead)
74  */
75 #define	MIN_DMA_LEN 128
76 
77 /*
78  * Transfers lager than 65535 bytes need to be split-up.
79  * (Some of the FIFO logic has only 16 bits counters.)
80  * Make the size an integer multiple of the page size
81  * to avoid buf/cluster remap problems.  (paranoid?)
82  */
83 #define	MAX_DMA_LEN 0xE000
84 
85 /*
86  * This structure is used to keep track of mapped DMA requests.
87  */
88 struct se_dma_handle {
89 	int 		dh_flags;
90 #define	SIDH_BUSY	1		/* This DH is in use */
91 #define	SIDH_OUT	2		/* DMA does data out (write) */
92 	u_char *	dh_addr;	/* KVA of start of buffer */
93 	int 		dh_maplen;	/* Length of KVA mapping. */
94 	long		dh_dma; 	/* Offset in DMA buffer. */
95 };
96 
97 /*
98  * The first structure member has to be the ncr5380_softc
99  * so we can just cast to go back and fourth between them.
100  */
101 struct se_softc {
102 	struct ncr5380_softc	ncr_sc;
103 	volatile struct se_regs	*sc_regs;
104 	int		sc_adapter_type;
105 	int		sc_adapter_iv;		/* int. vec */
106 	int 	sc_options;			/* options for this instance */
107 	int 	sc_reqlen;  		/* requested transfer length */
108 	struct se_dma_handle *sc_dma;
109 	/* DMA command block for the OBIO controller. */
110 	void *sc_dmacmd;
111 };
112 
113 /* Options for disconnect/reselect, DMA, and interrupts. */
114 #define SE_NO_DISCONNECT    0xff
115 #define SE_NO_PARITY_CHK  0xff00
116 #define SE_FORCE_POLLING 0x10000
117 #define SE_DISABLE_DMA   0x20000
118 
119 void se_dma_alloc __P((struct ncr5380_softc *));
120 void se_dma_free __P((struct ncr5380_softc *));
121 void se_dma_poll __P((struct ncr5380_softc *));
122 
123 void se_dma_setup __P((struct ncr5380_softc *));
124 void se_dma_start __P((struct ncr5380_softc *));
125 void se_dma_eop __P((struct ncr5380_softc *));
126 void se_dma_stop __P((struct ncr5380_softc *));
127 
128 void se_intr_on  __P((struct ncr5380_softc *));
129 void se_intr_off __P((struct ncr5380_softc *));
130 
131 static int  se_intr __P((void *));
132 static void se_reset __P((struct ncr5380_softc *));
133 
134 /*
135  * New-style autoconfig attachment
136  */
137 
138 static int	se_match __P((struct device *, struct cfdata *, void *));
139 static void	se_attach __P((struct device *, struct device *, void *));
140 
141 struct cfattach si_sebuf_ca = {
142 	sizeof(struct se_softc), se_match, se_attach
143 };
144 
145 static void	se_minphys __P((struct buf *));
146 
147 /* Options for disconnect/reselect, DMA, and interrupts. */
148 int se_options = SE_DISABLE_DMA | SE_FORCE_POLLING | 0xff;
149 
150 /* How long to wait for DMA before declaring an error. */
151 int se_dma_intr_timo = 500;	/* ticks (sec. X 100) */
152 
153 int se_debug = 0;
154 #ifdef	DEBUG
155 static int se_link_flags = 0 /* | SDEV_DB2 */ ;
156 #endif
157 
158 
159 static int
160 se_match(parent, cf, args)
161 	struct device	*parent;
162 	struct cfdata *cf;
163 	void *args;
164 {
165 	struct sebuf_attach_args *aa = args;
166 
167 	/* Match by name. */
168 	if (strcmp(aa->name, "se"))
169 		return (0);
170 
171 	/* Anyting else to check? */
172 
173 	return (1);
174 }
175 
176 static void
177 se_attach(parent, self, args)
178 	struct device	*parent, *self;
179 	void		*args;
180 {
181 	struct se_softc *sc = (struct se_softc *) self;
182 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
183 	struct cfdata *cf = self->dv_cfdata;
184 	struct sebuf_attach_args *aa = args;
185 	volatile struct se_regs *regs;
186 	int i;
187 
188 	/* Get options from config flags if specified. */
189 	if (cf->cf_flags)
190 		sc->sc_options = cf->cf_flags;
191 	else
192 		sc->sc_options = se_options;
193 
194 	printf(": options=0x%x\n", sc->sc_options);
195 
196 	sc->sc_adapter_type = aa->ca.ca_bustype;
197 	sc->sc_adapter_iv = aa->ca.ca_intvec;
198 	sc->sc_regs = regs = aa->regs;
199 
200 	/*
201 	 * MD function pointers used by the MI code.
202 	 */
203 	ncr_sc->sc_pio_out = ncr5380_pio_out;
204 	ncr_sc->sc_pio_in =  ncr5380_pio_in;
205 
206 #if 0	/* XXX - not yet... */
207 	ncr_sc->sc_dma_alloc = se_dma_alloc;
208 	ncr_sc->sc_dma_free  = se_dma_free;
209 	ncr_sc->sc_dma_setup = se_dma_setup;
210 	ncr_sc->sc_dma_start = se_dma_start;
211 	ncr_sc->sc_dma_poll  = se_dma_poll;
212 	ncr_sc->sc_dma_eop   = se_dma_eop;
213 	ncr_sc->sc_dma_stop  = se_dma_stop;
214 	ncr_sc->sc_intr_on   = se_intr_on;
215 	ncr_sc->sc_intr_off  = se_intr_off;
216 #endif	/* XXX */
217 
218 	/* Attach interrupt handler. */
219 	isr_add_vectored(se_intr, (void *)sc,
220 		aa->ca.ca_intpri, aa->ca.ca_intvec);
221 
222 	/* Reset the hardware. */
223 	se_reset(ncr_sc);
224 
225 	/* Do the common attach stuff. */
226 
227 	/*
228 	 * Support the "options" (config file flags).
229 	 * Disconnect/reselect is a per-target mask.
230 	 * Interrupts and DMA are per-controller.
231 	 */
232 	ncr_sc->sc_no_disconnect =
233 		(sc->sc_options & SE_NO_DISCONNECT);
234 	ncr_sc->sc_parity_disable =
235 		(sc->sc_options & SE_NO_PARITY_CHK) >> 8;
236 	if (sc->sc_options & SE_FORCE_POLLING)
237 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
238 
239 #if 1	/* XXX - Temporary */
240 	/* XXX - In case we think DMA is completely broken... */
241 	if (sc->sc_options & SE_DISABLE_DMA) {
242 		/* Override this function pointer. */
243 		ncr_sc->sc_dma_alloc = NULL;
244 	}
245 #endif
246 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
247 
248 #ifdef	DEBUG
249 	if (se_debug)
250 		printf("se: Set TheSoftC=%p TheRegs=%p\n", sc, regs);
251 	ncr_sc->sc_link.flags |= se_link_flags;
252 #endif
253 
254 	/*
255 	 * Initialize fields used by the MI code
256 	 */
257 	ncr_sc->sci_r0 = &regs->ncrregs[0];
258 	ncr_sc->sci_r1 = &regs->ncrregs[1];
259 	ncr_sc->sci_r2 = &regs->ncrregs[2];
260 	ncr_sc->sci_r3 = &regs->ncrregs[3];
261 	ncr_sc->sci_r4 = &regs->ncrregs[4];
262 	ncr_sc->sci_r5 = &regs->ncrregs[5];
263 	ncr_sc->sci_r6 = &regs->ncrregs[6];
264 	ncr_sc->sci_r7 = &regs->ncrregs[7];
265 
266 	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
267 
268 	/*
269 	 * Allocate DMA handles.
270 	 */
271 	i = SCI_OPENINGS * sizeof(struct se_dma_handle);
272 	sc->sc_dma = (struct se_dma_handle *)
273 		malloc(i, M_DEVBUF, M_WAITOK);
274 	if (sc->sc_dma == NULL)
275 		panic("se: dma_malloc failed\n");
276 	for (i = 0; i < SCI_OPENINGS; i++)
277 		sc->sc_dma[i].dh_flags = 0;
278 
279 	ncr_sc->sc_link.scsipi_scsi.adapter_target = 7;
280 	ncr_sc->sc_adapter.scsipi_minphys = se_minphys;
281 
282 	/*
283 	 *  Initialize se board itself.
284 	 */
285 	ncr5380_attach(ncr_sc);
286 }
287 
288 static void
289 se_reset(struct ncr5380_softc *ncr_sc)
290 {
291 	struct se_softc *sc = (struct se_softc *)ncr_sc;
292 	volatile struct se_regs *se = sc->sc_regs;
293 
294 #ifdef	DEBUG
295 	if (se_debug) {
296 		printf("se_reset\n");
297 	}
298 #endif
299 
300 	/* The reset bits in the CSR are active low. */
301 	se->se_csr = 0;
302 	delay(10);
303 	se->se_csr = SE_CSR_SCSI_RES /* | SE_CSR_INTR_EN */ ;
304 	delay(10);
305 
306 	/* Make sure the DMA engine is stopped. */
307 	se->dma_addr = 0;
308 	se->dma_cntr = 0;
309 	se->se_ivec = sc->sc_adapter_iv;
310 }
311 
312 /*
313  * This is called when the bus is going idle,
314  * so we want to enable the SBC interrupts.
315  * That is controlled by the DMA enable!
316  * Who would have guessed!
317  * What a NASTY trick!
318  */
319 void
320 se_intr_on(ncr_sc)
321 	struct ncr5380_softc *ncr_sc;
322 {
323 	struct se_softc *sc = (struct se_softc *)ncr_sc;
324 	volatile struct se_regs *se = sc->sc_regs;
325 
326 	/* receive mode should be safer */
327 	se->se_csr &= ~SE_CSR_SEND;
328 
329 	/* Clear the count so nothing happens. */
330 	se->dma_cntr = 0;
331 
332 	/* Clear the start address too. (paranoid?) */
333 	se->dma_addr = 0;
334 
335 	/* Finally, enable the DMA engine. */
336 	se->se_csr |= SE_CSR_INTR_EN;
337 }
338 
339 /*
340  * This is called when the bus is idle and we are
341  * about to start playing with the SBC chip.
342  */
343 void
344 se_intr_off(ncr_sc)
345 	struct ncr5380_softc *ncr_sc;
346 {
347 	struct se_softc *sc = (struct se_softc *)ncr_sc;
348 	volatile struct se_regs *se = sc->sc_regs;
349 
350 	se->se_csr &= ~SE_CSR_INTR_EN;
351 }
352 
353 /*
354  * This function is called during the COMMAND or MSG_IN phase
355  * that preceeds a DATA_IN or DATA_OUT phase, in case we need
356  * to setup the DMA engine before the bus enters a DATA phase.
357  *
358  * On the VME version, setup the start addres, but clear the
359  * count (to make sure it stays idle) and set that later.
360  * XXX: The VME adapter appears to suppress SBC interrupts
361  * when the FIFO is not empty or the FIFO count is non-zero!
362  * XXX: Need to copy data into the DMA buffer...
363  */
364 void
365 se_dma_setup(ncr_sc)
366 	struct ncr5380_softc *ncr_sc;
367 {
368 	struct se_softc *sc = (struct se_softc *)ncr_sc;
369 	struct sci_req *sr = ncr_sc->sc_current;
370 	struct se_dma_handle *dh = sr->sr_dma_hand;
371 	volatile struct se_regs *se = sc->sc_regs;
372 	long data_pa;
373 	int xlen;
374 
375 	/*
376 	 * Get the DMA mapping for this segment.
377 	 * XXX - Should separate allocation and mapin.
378 	 */
379 	data_pa = 0; /* XXX se_dma_kvtopa(dh->dh_dma); */
380 	data_pa += (ncr_sc->sc_dataptr - dh->dh_addr);
381 	if (data_pa & 1)
382 		panic("se_dma_start: bad pa=0x%lx", data_pa);
383 	xlen = ncr_sc->sc_datalen;
384 	xlen &= ~1;				/* XXX: necessary? */
385 	sc->sc_reqlen = xlen; 	/* XXX: or less? */
386 
387 #ifdef	DEBUG
388 	if (se_debug & 2) {
389 		printf("se_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n",
390 			   dh, data_pa, xlen);
391 	}
392 #endif
393 
394 	/* Set direction (send/recv) */
395 	if (dh->dh_flags & SIDH_OUT) {
396 		se->se_csr |= SE_CSR_SEND;
397 	} else {
398 		se->se_csr &= ~SE_CSR_SEND;
399 	}
400 
401 	/* Load the start address. */
402 	se->dma_addr = (ushort)(data_pa & 0xFFFF);
403 
404 	/*
405 	 * Keep the count zero or it may start early!
406 	 */
407 	se->dma_cntr = 0;
408 }
409 
410 
411 void
412 se_dma_start(ncr_sc)
413 	struct ncr5380_softc *ncr_sc;
414 {
415 	struct se_softc *sc = (struct se_softc *)ncr_sc;
416 	struct sci_req *sr = ncr_sc->sc_current;
417 	struct se_dma_handle *dh = sr->sr_dma_hand;
418 	volatile struct se_regs *se = sc->sc_regs;
419 	int s, xlen;
420 
421 	xlen = sc->sc_reqlen;
422 
423 	/* This MAY be time critical (not sure). */
424 	s = splhigh();
425 
426 	se->dma_cntr = (ushort)(xlen & 0xFFFF);
427 
428 	/*
429 	 * Acknowledge the phase change.  (After DMA setup!)
430 	 * Put the SBIC into DMA mode, and start the transfer.
431 	 */
432 	if (dh->dh_flags & SIDH_OUT) {
433 		*ncr_sc->sci_tcmd = PHASE_DATA_OUT;
434 		SCI_CLR_INTR(ncr_sc);
435 		*ncr_sc->sci_icmd = SCI_ICMD_DATA;
436 		*ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
437 		*ncr_sc->sci_dma_send = 0;	/* start it */
438 	} else {
439 		*ncr_sc->sci_tcmd = PHASE_DATA_IN;
440 		SCI_CLR_INTR(ncr_sc);
441 		*ncr_sc->sci_icmd = 0;
442 		*ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
443 		*ncr_sc->sci_irecv = 0;	/* start it */
444 	}
445 
446 	/* Let'er rip! */
447 	se->se_csr |= SE_CSR_INTR_EN;
448 
449 	splx(s);
450 	ncr_sc->sc_state |= NCR_DOINGDMA;
451 
452 #ifdef	DEBUG
453 	if (se_debug & 2) {
454 		printf("se_dma_start: started, flags=0x%x\n",
455 			   ncr_sc->sc_state);
456 	}
457 #endif
458 }
459 
460 
461 void
462 se_dma_eop(ncr_sc)
463 	struct ncr5380_softc *ncr_sc;
464 {
465 
466 	/* Not needed - DMA was stopped prior to examining sci_csr */
467 }
468 
469 
470 void
471 se_dma_stop(ncr_sc)
472 	struct ncr5380_softc *ncr_sc;
473 {
474 	struct se_softc *sc = (struct se_softc *)ncr_sc;
475 	struct sci_req *sr = ncr_sc->sc_current;
476 	struct se_dma_handle *dh = sr->sr_dma_hand;
477 	volatile struct se_regs *se = sc->sc_regs;
478 	int resid, ntrans;
479 
480 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
481 #ifdef	DEBUG
482 		printf("se_dma_stop: dma not running\n");
483 #endif
484 		return;
485 	}
486 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
487 
488 	/* First, halt the DMA engine. */
489 	se->se_csr &= ~SE_CSR_INTR_EN;	/* VME only */
490 
491 	/* Set an impossible phase to prevent data movement? */
492 	*ncr_sc->sci_tcmd = PHASE_INVALID;
493 
494 	/* Note that timeout may have set the error flag. */
495 	if (ncr_sc->sc_state & NCR_ABORTING)
496 		goto out;
497 
498 	/* XXX: Wait for DMA to actually finish? */
499 
500 	/*
501 	 * Now try to figure out how much actually transferred
502 	 */
503 	resid = se->dma_cntr & 0xFFFF;
504 	if (dh->dh_flags & SIDH_OUT)
505 		if ((resid > 0) && (resid < sc->sc_reqlen))
506 			resid++;
507 	ntrans = sc->sc_reqlen - resid;
508 
509 #ifdef	DEBUG
510 	if (se_debug & 2) {
511 		printf("se_dma_stop: resid=0x%x ntrans=0x%x\n",
512 		       resid, ntrans);
513 	}
514 #endif
515 
516 	if (ntrans < MIN_DMA_LEN) {
517 		printf("se: fifo count: 0x%x\n", resid);
518 		ncr_sc->sc_state |= NCR_ABORTING;
519 		goto out;
520 	}
521 	if (ntrans > ncr_sc->sc_datalen)
522 		panic("se_dma_stop: excess transfer");
523 
524 	/* Adjust data pointer */
525 	ncr_sc->sc_dataptr += ntrans;
526 	ncr_sc->sc_datalen -= ntrans;
527 
528 out:
529 	se->dma_addr = 0;
530 	se->dma_cntr = 0;
531 
532 	/* Put SBIC back in PIO mode. */
533 	*ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE);
534 	*ncr_sc->sci_icmd = 0;
535 }
536 
537 /*****************************************************************/
538 
539 static void
540 se_minphys(struct buf *bp)
541 {
542 
543 	if (bp->b_bcount > MAX_DMA_LEN)
544 		bp->b_bcount = MAX_DMA_LEN;
545 
546 	return (minphys(bp));
547 }
548 
549 
550 int
551 se_intr(void *arg)
552 {
553 	struct se_softc *sc = arg;
554 	volatile struct se_regs *se = sc->sc_regs;
555 	int dma_error, claimed;
556 	u_short csr;
557 
558 	claimed = 0;
559 	dma_error = 0;
560 
561 	/* SBC interrupt? DMA interrupt? */
562 	csr = se->se_csr;
563 	NCR_TRACE("se_intr: csr=0x%x\n", csr);
564 
565 	if (csr & SE_CSR_SBC_IP) {
566 		claimed = ncr5380_intr(&sc->ncr_sc);
567 #ifdef	DEBUG
568 		if (!claimed) {
569 			printf("se_intr: spurious from SBC\n");
570 		}
571 #endif
572 		/* Yes, we DID cause this interrupt. */
573 		claimed = 1;
574 	}
575 
576 	return (claimed);
577 }
578 
579 
580 /*****************************************************************
581  * Common functions for DMA
582  ****************************************************************/
583 
584 /*
585  * Allocate a DMA handle and put it in sc->sc_dma.  Prepare
586  * for DMA transfer.  On the Sun3/E, this means we have to
587  * allocate space in the DMA buffer for this transfer.
588  */
589 void
590 se_dma_alloc(ncr_sc)
591 	struct ncr5380_softc *ncr_sc;
592 {
593 	struct se_softc *sc = (struct se_softc *)ncr_sc;
594 	struct sci_req *sr = ncr_sc->sc_current;
595 	struct scsipi_xfer *xs = sr->sr_xs;
596 	struct se_dma_handle *dh;
597 	int i, xlen;
598 	u_long addr;
599 
600 #ifdef	DIAGNOSTIC
601 	if (sr->sr_dma_hand != NULL)
602 		panic("se_dma_alloc: already have DMA handle");
603 #endif
604 
605 	addr = (u_long) ncr_sc->sc_dataptr;
606 	xlen = ncr_sc->sc_datalen;
607 
608 	/* If the DMA start addr is misaligned then do PIO */
609 	if ((addr & 1) || (xlen & 1)) {
610 		printf("se_dma_alloc: misaligned.\n");
611 		return;
612 	}
613 
614 	/* Make sure our caller checked sc_min_dma_len. */
615 	if (xlen < MIN_DMA_LEN)
616 		panic("se_dma_alloc: xlen=0x%x\n", xlen);
617 
618 	/*
619 	 * Never attempt single transfers of more than 63k, because
620 	 * our count register may be only 16 bits (an OBIO adapter).
621 	 * This should never happen since already bounded by minphys().
622 	 * XXX - Should just segment these...
623 	 */
624 	if (xlen > MAX_DMA_LEN) {
625 		printf("se_dma_alloc: excessive xlen=0x%x\n", xlen);
626 		ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
627 	}
628 
629 	/* Find free DMA handle.  Guaranteed to find one since we have
630 	   as many DMA handles as the driver has processes. */
631 	for (i = 0; i < SCI_OPENINGS; i++) {
632 		if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
633 			goto found;
634 	}
635 	panic("se: no free DMA handles.");
636 found:
637 
638 	dh = &sc->sc_dma[i];
639 	dh->dh_flags = SIDH_BUSY;
640 
641 	/* Copy the "write" flag for convenience. */
642 	if (xs->xs_control & XS_CTL_DATA_OUT)
643 		dh->dh_flags |= SIDH_OUT;
644 
645 	dh->dh_addr = (u_char*) addr;
646 	dh->dh_maplen  = xlen;
647 	dh->dh_dma = 0;	/* XXX - Allocate space in DMA buffer. */
648 	/* XXX: dh->dh_dma = alloc(xlen) */
649 	if (!dh->dh_dma) {
650 		/* Can't remap segment */
651 		printf("se_dma_alloc: can't remap %p/0x%x\n",
652 			dh->dh_addr, dh->dh_maplen);
653 		dh->dh_flags = 0;
654 		return;
655 	}
656 
657 	/* success */
658 	sr->sr_dma_hand = dh;
659 
660 	return;
661 }
662 
663 
664 void
665 se_dma_free(ncr_sc)
666 	struct ncr5380_softc *ncr_sc;
667 {
668 	struct sci_req *sr = ncr_sc->sc_current;
669 	struct se_dma_handle *dh = sr->sr_dma_hand;
670 
671 #ifdef	DIAGNOSTIC
672 	if (dh == NULL)
673 		panic("se_dma_free: no DMA handle");
674 #endif
675 
676 	if (ncr_sc->sc_state & NCR_DOINGDMA)
677 		panic("se_dma_free: free while in progress");
678 
679 	if (dh->dh_flags & SIDH_BUSY) {
680 		/* XXX: Should separate allocation and mapping. */
681 		/* XXX: Give back the DMA space. */
682 		/* XXX: free((caddr_t)dh->dh_dma, dh->dh_maplen); */
683 		dh->dh_dma = 0;
684 		dh->dh_flags = 0;
685 	}
686 	sr->sr_dma_hand = NULL;
687 }
688 
689 
690 #define	CSR_MASK SE_CSR_SBC_IP
691 #define	POLL_TIMO	50000	/* X100 = 5 sec. */
692 
693 /*
694  * Poll (spin-wait) for DMA completion.
695  * Called right after xx_dma_start(), and
696  * xx_dma_stop() will be called next.
697  * Same for either VME or OBIO.
698  */
699 void
700 se_dma_poll(ncr_sc)
701 	struct ncr5380_softc *ncr_sc;
702 {
703 	struct se_softc *sc = (struct se_softc *)ncr_sc;
704 	struct sci_req *sr = ncr_sc->sc_current;
705 	volatile struct se_regs *se = sc->sc_regs;
706 	int tmo;
707 
708 	/* Make sure DMA started successfully. */
709 	if (ncr_sc->sc_state & NCR_ABORTING)
710 		return;
711 
712 	/*
713 	 * XXX: The Sun driver waits for ~SE_CSR_DMA_ACTIVE here
714 	 * XXX: (on obio) or even worse (on vme) a 10mS. delay!
715 	 * XXX: I really doubt that is necessary...
716 	 */
717 
718 	/* Wait for any "dma complete" or error bits. */
719 	tmo = POLL_TIMO;
720 	for (;;) {
721 		if (se->se_csr & CSR_MASK)
722 			break;
723 		if (--tmo <= 0) {
724 			printf("se: DMA timeout (while polling)\n");
725 			/* Indicate timeout as MI code would. */
726 			sr->sr_flags |= SR_OVERDUE;
727 			break;
728 		}
729 		delay(100);
730 	}
731 	NCR_TRACE("se_dma_poll: waited %d\n",
732 			  POLL_TIMO - tmo);
733 
734 #ifdef	DEBUG
735 	if (se_debug & 2) {
736 		printf("se_dma_poll: done, csr=0x%x\n", se->se_csr);
737 	}
738 #endif
739 }
740 
741