1 /* $NetBSD: si_obio.c,v 1.26 2003/05/03 18:11:04 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsipi_debug.h> 96 #include <dev/scsipi/scsiconf.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/dvma.h> 100 101 /* #define DEBUG XXX */ 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 #include "am9516.h" 109 110 /* 111 * How many uS. to delay after touching the am9516 UDC. 112 */ 113 #define UDC_WAIT_USEC 5 114 115 void si_obio_dma_setup __P((struct ncr5380_softc *)); 116 void si_obio_dma_start __P((struct ncr5380_softc *)); 117 void si_obio_dma_eop __P((struct ncr5380_softc *)); 118 void si_obio_dma_stop __P((struct ncr5380_softc *)); 119 120 static void si_obio_reset __P((struct ncr5380_softc *)); 121 122 static __inline__ void si_obio_udc_write 123 __P((volatile struct si_regs *si, int regnum, int value)); 124 static __inline__ int si_obio_udc_read 125 __P((volatile struct si_regs *si, int regnum)); 126 127 128 /* 129 * New-style autoconfig attachment 130 */ 131 132 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 133 static void si_obio_attach __P((struct device *, struct device *, void *)); 134 135 CFATTACH_DECL(si_obio, sizeof(struct si_softc), 136 si_obio_match, si_obio_attach, NULL, NULL); 137 138 /* 139 * Options for disconnect/reselect, DMA, and interrupts. 140 * By default, allow disconnect/reselect on targets 4-6. 141 * Those are normally tapes that really need it enabled. 142 */ 143 int si_obio_options = 0x0f; 144 145 146 static int 147 si_obio_match(parent, cf, aux) 148 struct device *parent; 149 struct cfdata *cf; 150 void *aux; 151 { 152 struct confargs *ca = aux; 153 154 /* Make sure something is there... */ 155 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 156 return (0); 157 158 /* Default interrupt priority. */ 159 if (ca->ca_intpri == -1) 160 ca->ca_intpri = 2; 161 162 return (1); 163 } 164 165 static void 166 si_obio_attach(parent, self, args) 167 struct device *parent, *self; 168 void *args; 169 { 170 struct si_softc *sc = (struct si_softc *) self; 171 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 172 struct cfdata *cf = self->dv_cfdata; 173 struct confargs *ca = args; 174 175 /* Get options from config flags if specified. */ 176 if (cf->cf_flags) 177 sc->sc_options = cf->cf_flags; 178 else 179 sc->sc_options = si_obio_options; 180 181 printf(": options=0x%x\n", sc->sc_options); 182 183 sc->sc_adapter_type = ca->ca_bustype; 184 sc->sc_regs = bus_mapin(ca->ca_bustype, 185 ca->ca_paddr, sizeof(struct si_regs)); 186 187 /* 188 * MD function pointers used by the MI code. 189 */ 190 ncr_sc->sc_pio_out = ncr5380_pio_out; 191 ncr_sc->sc_pio_in = ncr5380_pio_in; 192 ncr_sc->sc_dma_alloc = si_dma_alloc; 193 ncr_sc->sc_dma_free = si_dma_free; 194 ncr_sc->sc_dma_setup = si_obio_dma_setup; 195 ncr_sc->sc_dma_start = si_obio_dma_start; 196 ncr_sc->sc_dma_poll = si_dma_poll; 197 ncr_sc->sc_dma_eop = si_obio_dma_eop; 198 ncr_sc->sc_dma_stop = si_obio_dma_stop; 199 ncr_sc->sc_intr_on = NULL; 200 ncr_sc->sc_intr_off = NULL; 201 202 /* Need DVMA-capable memory for the UDC command block. */ 203 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 204 205 /* Attach interrupt handler. */ 206 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 207 208 /* Reset the hardware. */ 209 si_obio_reset(ncr_sc); 210 211 /* Do the common attach stuff. */ 212 si_attach(sc); 213 } 214 215 static void 216 si_obio_reset(struct ncr5380_softc *ncr_sc) 217 { 218 struct si_softc *sc = (struct si_softc *)ncr_sc; 219 volatile struct si_regs *si = sc->sc_regs; 220 221 #ifdef DEBUG 222 if (si_debug) { 223 printf("si_obio_reset\n"); 224 } 225 #endif 226 227 /* 228 * The SCSI3 controller has an 8K FIFO to buffer data between the 229 * 5380 and the DMA. Make sure it starts out empty. 230 * 231 * The reset bits in the CSR are active low. 232 */ 233 si->si_csr = 0; 234 delay(10); 235 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 236 delay(10); 237 si->fifo_count = 0; 238 } 239 240 static __inline__ void 241 si_obio_udc_write(si, regnum, value) 242 volatile struct si_regs *si; 243 int regnum, value; 244 { 245 si->udc_addr = regnum; 246 delay(UDC_WAIT_USEC); 247 si->udc_data = value; 248 delay(UDC_WAIT_USEC); 249 } 250 251 static __inline__ int 252 si_obio_udc_read(si, regnum) 253 volatile struct si_regs *si; 254 int regnum; 255 { 256 int value; 257 258 si->udc_addr = regnum; 259 delay(UDC_WAIT_USEC); 260 value = si->udc_data; 261 delay(UDC_WAIT_USEC); 262 263 return (value); 264 } 265 266 267 /* 268 * This function is called during the COMMAND or MSG_IN phase 269 * that precedes a DATA_IN or DATA_OUT phase, in case we need 270 * to setup the DMA engine before the bus enters a DATA phase. 271 * 272 * The OBIO "si" IGNORES any attempt to set the FIFO count 273 * register after the SCSI bus goes into any DATA phase, so 274 * this function has to setup the evil FIFO logic. 275 */ 276 void 277 si_obio_dma_setup(ncr_sc) 278 struct ncr5380_softc *ncr_sc; 279 { 280 struct si_softc *sc = (struct si_softc *)ncr_sc; 281 struct sci_req *sr = ncr_sc->sc_current; 282 struct si_dma_handle *dh = sr->sr_dma_hand; 283 volatile struct si_regs *si = sc->sc_regs; 284 struct udc_table *cmd; 285 long data_pa, cmd_pa; 286 int xlen; 287 288 /* 289 * Get the DVMA mapping for this segment. 290 * XXX - Should separate allocation and mapin. 291 */ 292 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 293 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 294 if (data_pa & 1) 295 panic("si_dma_start: bad pa=0x%lx", data_pa); 296 xlen = ncr_sc->sc_datalen; 297 sc->sc_reqlen = xlen; /* XXX: or less? */ 298 299 #ifdef DEBUG 300 if (si_debug & 2) { 301 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 302 dh, data_pa, xlen); 303 } 304 #endif 305 306 /* Reset the UDC. (In case not already reset?) */ 307 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 308 309 /* Reset the FIFO */ 310 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 311 si->si_csr |= SI_CSR_FIFO_RES; 312 313 /* Set direction (send/recv) */ 314 if (dh->dh_flags & SIDH_OUT) { 315 si->si_csr |= SI_CSR_SEND; 316 } else { 317 si->si_csr &= ~SI_CSR_SEND; 318 } 319 320 /* Set the FIFO counter. */ 321 si->fifo_count = xlen; 322 323 /* Reset the UDC. */ 324 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 325 326 /* 327 * XXX: Reset the FIFO again! Comment from Sprite: 328 * Go through reset again becuase of the bug on the 3/50 329 * where bytes occasionally linger in the DMA fifo. 330 */ 331 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 332 si->si_csr |= SI_CSR_FIFO_RES; 333 334 #ifdef DEBUG 335 /* Make sure the extra FIFO reset did not hit the count. */ 336 if (si->fifo_count != xlen) { 337 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 338 si->fifo_count, xlen); 339 Debugger(); 340 } 341 #endif 342 343 /* 344 * Set up the DMA controller. The DMA controller on 345 * OBIO needs a command block in DVMA space. 346 */ 347 cmd = sc->sc_dmacmd; 348 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 349 cmd->addrl = data_pa & 0xFFFF; 350 cmd->count = xlen / 2; /* bytes -> words */ 351 cmd->cmrh = UDC_CMR_HIGH; 352 if (dh->dh_flags & SIDH_OUT) { 353 if (xlen & 1) 354 cmd->count++; 355 cmd->cmrl = UDC_CMR_LSEND; 356 cmd->rsel = UDC_RSEL_SEND; 357 } else { 358 cmd->cmrl = UDC_CMR_LRECV; 359 cmd->rsel = UDC_RSEL_RECV; 360 } 361 362 /* Tell the DMA chip where the control block is. */ 363 cmd_pa = dvma_kvtopa(cmd, BUS_OBIO); 364 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 365 (cmd_pa & 0xff0000) >> 8); 366 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 367 (cmd_pa & 0xffff)); 368 369 /* Tell the chip to be a DMA master. */ 370 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 371 372 /* Tell the chip to interrupt on error. */ 373 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 374 375 /* Will do "start chain" command in _dma_start. */ 376 } 377 378 379 void 380 si_obio_dma_start(ncr_sc) 381 struct ncr5380_softc *ncr_sc; 382 { 383 struct si_softc *sc = (struct si_softc *)ncr_sc; 384 struct sci_req *sr = ncr_sc->sc_current; 385 struct si_dma_handle *dh = sr->sr_dma_hand; 386 volatile struct si_regs *si = sc->sc_regs; 387 int s; 388 389 #ifdef DEBUG 390 if (si_debug & 2) { 391 printf("si_dma_start: sr=%p\n", sr); 392 } 393 #endif 394 395 /* This MAY be time critical (not sure). */ 396 s = splhigh(); 397 398 /* Finally, give the UDC a "start chain" command. */ 399 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 400 401 /* 402 * Acknowledge the phase change. (After DMA setup!) 403 * Put the SBIC into DMA mode, and start the transfer. 404 */ 405 if (dh->dh_flags & SIDH_OUT) { 406 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 407 SCI_CLR_INTR(ncr_sc); 408 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 409 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 410 *ncr_sc->sci_dma_send = 0; /* start it */ 411 } else { 412 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 413 SCI_CLR_INTR(ncr_sc); 414 *ncr_sc->sci_icmd = 0; 415 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 416 *ncr_sc->sci_irecv = 0; /* start it */ 417 } 418 419 splx(s); 420 ncr_sc->sc_state |= NCR_DOINGDMA; 421 422 #ifdef DEBUG 423 if (si_debug & 2) { 424 printf("si_dma_start: started, flags=0x%x\n", 425 ncr_sc->sc_state); 426 } 427 #endif 428 } 429 430 431 void 432 si_obio_dma_eop(ncr_sc) 433 struct ncr5380_softc *ncr_sc; 434 { 435 436 /* Not needed - DMA was stopped prior to examining sci_csr */ 437 } 438 439 440 void 441 si_obio_dma_stop(ncr_sc) 442 struct ncr5380_softc *ncr_sc; 443 { 444 struct si_softc *sc = (struct si_softc *)ncr_sc; 445 struct sci_req *sr = ncr_sc->sc_current; 446 struct si_dma_handle *dh = sr->sr_dma_hand; 447 volatile struct si_regs *si = sc->sc_regs; 448 int resid, ntrans, tmo, udc_cnt; 449 450 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 451 #ifdef DEBUG 452 printf("si_dma_stop: DMA not running\n"); 453 #endif 454 return; 455 } 456 ncr_sc->sc_state &= ~NCR_DOINGDMA; 457 458 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 459 460 /* OK, have either phase mis-match or end of DMA. */ 461 /* Set an impossible phase to prevent data movement? */ 462 *ncr_sc->sci_tcmd = PHASE_INVALID; 463 464 /* Check for DMA errors. */ 465 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 466 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 467 sr->sr_xs->error = XS_DRIVER_STUFFUP; 468 ncr_sc->sc_state |= NCR_ABORTING; 469 si_obio_reset(ncr_sc); 470 goto out; 471 } 472 473 /* Note that timeout may have set the error flag. */ 474 if (ncr_sc->sc_state & NCR_ABORTING) 475 goto out; 476 477 /* 478 * After a read, wait for the FIFO to empty. 479 * Note: this only works on the OBIO version. 480 */ 481 if ((dh->dh_flags & SIDH_OUT) == 0) { 482 tmo = 200000; /* X10 = 2 sec. */ 483 for (;;) { 484 if (si->si_csr & SI_CSR_FIFO_EMPTY) 485 break; 486 if (--tmo <= 0) { 487 printf("si: DMA FIFO did not empty, reset\n"); 488 ncr_sc->sc_state |= NCR_ABORTING; 489 /* si_obio_reset(ncr_sc); */ 490 goto out; 491 } 492 delay(10); 493 } 494 } 495 496 /* 497 * Now try to figure out how much actually transferred. 498 * The fifo_count might not reflect how many bytes were 499 * actually transferred. 500 */ 501 resid = si->fifo_count & 0xFFFF; 502 ntrans = sc->sc_reqlen - resid; 503 504 #ifdef DEBUG 505 if (si_debug & 2) { 506 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 507 resid, ntrans); 508 } 509 #endif 510 511 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 512 if (ntrans < MIN_DMA_LEN) { 513 printf("si: fifo count: 0x%x\n", resid); 514 ncr_sc->sc_state |= NCR_ABORTING; 515 goto out; 516 } 517 if (ntrans > ncr_sc->sc_datalen) 518 panic("si_dma_stop: excess transfer"); 519 520 /* Adjust data pointer */ 521 ncr_sc->sc_dataptr += ntrans; 522 ncr_sc->sc_datalen -= ntrans; 523 524 /* 525 * After a read, we may need to clean-up 526 * "Left-over bytes" (yuck!) 527 */ 528 if ((dh->dh_flags & SIDH_OUT) == 0) { 529 /* If odd transfer count, grab last byte by hand. */ 530 if (ntrans & 1) { 531 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 532 (int) ncr_sc->sc_dataptr - 1); 533 ncr_sc->sc_dataptr[-1] = 534 (si->fifo_data & 0xff00) >> 8; 535 goto out; 536 } 537 /* UDC might not have transfered the last word. */ 538 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 539 if (((udc_cnt * 2) - resid) == 2) { 540 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 541 (int) ncr_sc->sc_dataptr - 2); 542 ncr_sc->sc_dataptr[-2] = 543 (si->fifo_data & 0xff00) >> 8; 544 ncr_sc->sc_dataptr[-1] = 545 (si->fifo_data & 0x00ff); 546 } 547 } 548 549 out: 550 /* Reset the UDC. */ 551 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 552 si->fifo_count = 0; 553 si->si_csr &= ~SI_CSR_SEND; 554 555 /* Reset the FIFO */ 556 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 557 si->si_csr |= SI_CSR_FIFO_RES; 558 559 /* Put SBIC back in PIO mode. */ 560 /* XXX: set tcmd to PHASE_INVALID? */ 561 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 562 *ncr_sc->sci_icmd = 0; 563 } 564 565