1 /* $NetBSD: si_obio.c,v 1.11 1997/02/26 22:26:02 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <scsi/scsi_all.h> 94 #include <scsi/scsi_debug.h> 95 #include <scsi/scsiconf.h> 96 97 #include <machine/autoconf.h> 98 #include <machine/obio.h> 99 #include <machine/dvma.h> 100 101 #define DEBUG XXX 102 103 #include <dev/ic/ncr5380reg.h> 104 #include <dev/ic/ncr5380var.h> 105 106 #include "sireg.h" 107 #include "sivar.h" 108 #include "am9516.h" 109 110 /* 111 * How many uS. to delay after touching the am9516 UDC. 112 */ 113 #define UDC_WAIT_USEC 5 114 115 void si_obio_dma_setup __P((struct ncr5380_softc *)); 116 void si_obio_dma_start __P((struct ncr5380_softc *)); 117 void si_obio_dma_eop __P((struct ncr5380_softc *)); 118 void si_obio_dma_stop __P((struct ncr5380_softc *)); 119 120 static __inline__ void si_obio_udc_write 121 __P((volatile struct si_regs *si, int regnum, int value)); 122 static __inline__ int si_obio_udc_read 123 __P((volatile struct si_regs *si, int regnum)); 124 125 126 /* 127 * New-style autoconfig attachment 128 */ 129 130 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 131 static void si_obio_attach __P((struct device *, struct device *, void *)); 132 133 struct cfattach si_obio_ca = { 134 sizeof(struct si_softc), si_obio_match, si_obio_attach 135 }; 136 137 /* 138 * Options for disconnect/reselect, DMA, and interrupts. 139 * By default, allow disconnect/reselect on targets 4-6. 140 * Those are normally tapes that really need it enabled. 141 * 142 * XXX - Leave interrupts disabled for now, to avoid the 143 * not-yet-identified "everything dumps core" bug... 144 */ 145 int si_obio_options = SI_FORCE_POLLING | 0x0f; 146 147 148 static int 149 si_obio_match(parent, cf, args) 150 struct device *parent; 151 struct cfdata *cf; 152 void *args; 153 { 154 struct confargs *ca = args; 155 156 /* Make sure there is something there... */ 157 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 158 return (0); 159 160 /* Default interrupt priority. */ 161 if (ca->ca_intpri == -1) 162 ca->ca_intpri = 2; 163 164 return (1); 165 } 166 167 static void 168 si_obio_attach(parent, self, args) 169 struct device *parent, *self; 170 void *args; 171 { 172 struct si_softc *sc = (struct si_softc *) self; 173 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 174 struct cfdata *cf = self->dv_cfdata; 175 struct confargs *ca = args; 176 177 /* Get options from config flags if specified. */ 178 if (cf->cf_flags) 179 sc->sc_options = cf->cf_flags; 180 else 181 sc->sc_options = si_obio_options; 182 183 printf(": options=0x%x\n", sc->sc_options); 184 185 sc->sc_adapter_type = ca->ca_bustype; 186 sc->sc_regs = (struct si_regs *) 187 obio_alloc(ca->ca_paddr, sizeof(struct si_regs)); 188 189 /* 190 * MD function pointers used by the MI code. 191 */ 192 ncr_sc->sc_pio_out = ncr5380_pio_out; 193 ncr_sc->sc_pio_in = ncr5380_pio_in; 194 ncr_sc->sc_dma_alloc = si_dma_alloc; 195 ncr_sc->sc_dma_free = si_dma_free; 196 ncr_sc->sc_dma_setup = si_obio_dma_setup; 197 ncr_sc->sc_dma_start = si_obio_dma_start; 198 ncr_sc->sc_dma_poll = si_dma_poll; 199 ncr_sc->sc_dma_eop = si_obio_dma_eop; 200 ncr_sc->sc_dma_stop = si_obio_dma_stop; 201 ncr_sc->sc_intr_on = NULL; 202 ncr_sc->sc_intr_off = NULL; 203 204 /* Need DVMA-capable memory for the UDC command block. */ 205 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 206 207 /* Attach interrupt handler. */ 208 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 209 210 /* Do the common attach stuff. */ 211 si_attach(sc); 212 } 213 214 215 static __inline__ void 216 si_obio_udc_write(si, regnum, value) 217 volatile struct si_regs *si; 218 int regnum, value; 219 { 220 si->udc_addr = regnum; 221 delay(UDC_WAIT_USEC); 222 si->udc_data = value; 223 delay(UDC_WAIT_USEC); 224 } 225 226 static __inline__ int 227 si_obio_udc_read(si, regnum) 228 volatile struct si_regs *si; 229 int regnum; 230 { 231 int value; 232 233 si->udc_addr = regnum; 234 delay(UDC_WAIT_USEC); 235 value = si->udc_data; 236 delay(UDC_WAIT_USEC); 237 238 return (value); 239 } 240 241 242 /* 243 * This function is called during the COMMAND or MSG_IN phase 244 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 245 * to setup the DMA engine before the bus enters a DATA phase. 246 * 247 * The OBIO "si" IGNORES any attempt to set the FIFO count 248 * register after the SCSI bus goes into any DATA phase, so 249 * this function has to setup the evil FIFO logic. 250 */ 251 void 252 si_obio_dma_setup(ncr_sc) 253 struct ncr5380_softc *ncr_sc; 254 { 255 struct si_softc *sc = (struct si_softc *)ncr_sc; 256 struct sci_req *sr = ncr_sc->sc_current; 257 struct si_dma_handle *dh = sr->sr_dma_hand; 258 volatile struct si_regs *si = sc->sc_regs; 259 struct udc_table *cmd; 260 long data_pa, cmd_pa; 261 int xlen; 262 263 /* 264 * Get the DVMA mapping for this segment. 265 * XXX - Should separate allocation and mapin. 266 */ 267 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 268 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 269 if (data_pa & 1) 270 panic("si_dma_start: bad pa=0x%x", data_pa); 271 xlen = ncr_sc->sc_datalen; 272 sc->sc_reqlen = xlen; /* XXX: or less? */ 273 274 #ifdef DEBUG 275 if (si_debug & 2) { 276 printf("si_dma_setup: dh=%p, pa=0x%x, xlen=0x%x\n", 277 dh, data_pa, xlen); 278 } 279 #endif 280 281 /* Reset the UDC. (In case not already reset?) */ 282 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 283 284 /* Reset the FIFO */ 285 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 286 si->si_csr |= SI_CSR_FIFO_RES; 287 288 /* Set direction (send/recv) */ 289 if (dh->dh_flags & SIDH_OUT) { 290 si->si_csr |= SI_CSR_SEND; 291 } else { 292 si->si_csr &= ~SI_CSR_SEND; 293 } 294 295 /* Set the FIFO counter. */ 296 si->fifo_count = xlen; 297 298 /* Reset the UDC. */ 299 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 300 301 /* 302 * XXX: Reset the FIFO again! Comment from Sprite: 303 * Go through reset again becuase of the bug on the 3/50 304 * where bytes occasionally linger in the DMA fifo. 305 */ 306 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 307 si->si_csr |= SI_CSR_FIFO_RES; 308 309 #ifdef DEBUG 310 /* Make sure the extra FIFO reset did not hit the count. */ 311 if (si->fifo_count != xlen) { 312 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 313 si->fifo_count, xlen); 314 Debugger(); 315 } 316 #endif 317 318 /* 319 * Set up the DMA controller. The DMA controller on 320 * OBIO needs a command block in DVMA space. 321 */ 322 cmd = sc->sc_dmacmd; 323 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 324 cmd->addrl = data_pa & 0xFFFF; 325 cmd->count = xlen / 2; /* bytes -> words */ 326 cmd->cmrh = UDC_CMR_HIGH; 327 if (dh->dh_flags & SIDH_OUT) { 328 if (xlen & 1) 329 cmd->count++; 330 cmd->cmrl = UDC_CMR_LSEND; 331 cmd->rsel = UDC_RSEL_SEND; 332 } else { 333 cmd->cmrl = UDC_CMR_LRECV; 334 cmd->rsel = UDC_RSEL_RECV; 335 } 336 337 /* Tell the DMA chip where the control block is. */ 338 cmd_pa = dvma_kvtopa((long)cmd, BUS_OBIO); 339 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 340 (cmd_pa & 0xff0000) >> 8); 341 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 342 (cmd_pa & 0xffff)); 343 344 /* Tell the chip to be a DMA master. */ 345 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 346 347 /* Tell the chip to interrupt on error. */ 348 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 349 350 /* Will do "start chain" command in _dma_start. */ 351 } 352 353 354 void 355 si_obio_dma_start(ncr_sc) 356 struct ncr5380_softc *ncr_sc; 357 { 358 struct si_softc *sc = (struct si_softc *)ncr_sc; 359 struct sci_req *sr = ncr_sc->sc_current; 360 struct si_dma_handle *dh = sr->sr_dma_hand; 361 volatile struct si_regs *si = sc->sc_regs; 362 int s; 363 364 #ifdef DEBUG 365 if (si_debug & 2) { 366 printf("si_dma_start: sr=%p\n", sr); 367 } 368 #endif 369 370 /* This MAY be time critical (not sure). */ 371 s = splhigh(); 372 373 /* Finally, give the UDC a "start chain" command. */ 374 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 375 376 /* 377 * Acknowledge the phase change. (After DMA setup!) 378 * Put the SBIC into DMA mode, and start the transfer. 379 */ 380 if (dh->dh_flags & SIDH_OUT) { 381 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 382 SCI_CLR_INTR(ncr_sc); 383 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 384 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 385 *ncr_sc->sci_dma_send = 0; /* start it */ 386 } else { 387 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 388 SCI_CLR_INTR(ncr_sc); 389 *ncr_sc->sci_icmd = 0; 390 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 391 *ncr_sc->sci_irecv = 0; /* start it */ 392 } 393 394 splx(s); 395 ncr_sc->sc_state |= NCR_DOINGDMA; 396 397 #ifdef DEBUG 398 if (si_debug & 2) { 399 printf("si_dma_start: started, flags=0x%x\n", 400 ncr_sc->sc_state); 401 } 402 #endif 403 } 404 405 406 void 407 si_obio_dma_eop(ncr_sc) 408 struct ncr5380_softc *ncr_sc; 409 { 410 411 /* Not needed - DMA was stopped prior to examining sci_csr */ 412 } 413 414 415 void 416 si_obio_dma_stop(ncr_sc) 417 struct ncr5380_softc *ncr_sc; 418 { 419 struct si_softc *sc = (struct si_softc *)ncr_sc; 420 struct sci_req *sr = ncr_sc->sc_current; 421 struct si_dma_handle *dh = sr->sr_dma_hand; 422 volatile struct si_regs *si = sc->sc_regs; 423 int resid, ntrans, tmo, udc_cnt; 424 425 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 426 #ifdef DEBUG 427 printf("si_dma_stop: dma not running\n"); 428 #endif 429 return; 430 } 431 ncr_sc->sc_state &= ~NCR_DOINGDMA; 432 433 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 434 435 /* OK, have either phase mis-match or end of DMA. */ 436 /* Set an impossible phase to prevent data movement? */ 437 *ncr_sc->sci_tcmd = PHASE_INVALID; 438 439 /* Check for DMA errors. */ 440 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 441 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 442 sr->sr_xs->error = XS_DRIVER_STUFFUP; 443 ncr_sc->sc_state |= NCR_ABORTING; 444 si_reset_adapter(ncr_sc); 445 goto out; 446 } 447 448 /* Note that timeout may have set the error flag. */ 449 if (ncr_sc->sc_state & NCR_ABORTING) 450 goto out; 451 452 /* 453 * After a read, wait for the FIFO to empty. 454 * Note: this only works on the OBIO version. 455 */ 456 if ((dh->dh_flags & SIDH_OUT) == 0) { 457 tmo = 200000; /* X10 = 2 sec. */ 458 for (;;) { 459 if (si->si_csr & SI_CSR_FIFO_EMPTY) 460 break; 461 if (--tmo <= 0) { 462 printf("si: dma fifo did not empty, reset\n"); 463 ncr_sc->sc_state |= NCR_ABORTING; 464 /* si_reset_adapter(ncr_sc); */ 465 goto out; 466 } 467 delay(10); 468 } 469 } 470 471 /* 472 * Now try to figure out how much actually transferred 473 * The fifo_count might not reflect how many bytes were 474 * actually transferred. 475 */ 476 resid = si->fifo_count & 0xFFFF; 477 ntrans = sc->sc_reqlen - resid; 478 479 #ifdef DEBUG 480 if (si_debug & 2) { 481 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 482 resid, ntrans); 483 } 484 #endif 485 486 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 487 if (ntrans < MIN_DMA_LEN) { 488 printf("si: fifo count: 0x%x\n", resid); 489 ncr_sc->sc_state |= NCR_ABORTING; 490 goto out; 491 } 492 if (ntrans > ncr_sc->sc_datalen) 493 panic("si_dma_stop: excess transfer"); 494 495 /* Adjust data pointer */ 496 ncr_sc->sc_dataptr += ntrans; 497 ncr_sc->sc_datalen -= ntrans; 498 499 /* 500 * After a read, we may need to clean-up 501 * "Left-over bytes" (yuck!) 502 */ 503 if ((dh->dh_flags & SIDH_OUT) == 0) { 504 /* If odd transfer count, grab last byte by hand. */ 505 if (ntrans & 1) { 506 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 507 (int) ncr_sc->sc_dataptr - 1); 508 ncr_sc->sc_dataptr[-1] = 509 (si->fifo_data & 0xff00) >> 8; 510 goto out; 511 } 512 /* UDC might not have transfered the last word. */ 513 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 514 if (((udc_cnt * 2) - resid) == 2) { 515 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 516 (int) ncr_sc->sc_dataptr - 2); 517 ncr_sc->sc_dataptr[-2] = 518 (si->fifo_data & 0xff00) >> 8; 519 ncr_sc->sc_dataptr[-1] = 520 (si->fifo_data & 0x00ff); 521 } 522 } 523 524 out: 525 /* Reset the UDC. */ 526 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 527 si->fifo_count = 0; 528 si->si_csr &= ~SI_CSR_SEND; 529 530 /* Reset the FIFO */ 531 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 532 si->si_csr |= SI_CSR_FIFO_RES; 533 534 /* Put SBIC back in PIO mode. */ 535 /* XXX: set tcmd to PHASE_INVALID? */ 536 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 537 *ncr_sc->sci_icmd = 0; 538 } 539 540