1 /* $NetBSD: si_obio.c,v 1.18 1997/12/09 22:29:04 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 /***************************************************************** 80 * OBIO functions for DMA 81 ****************************************************************/ 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/errno.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/device.h> 89 #include <sys/buf.h> 90 #include <sys/proc.h> 91 #include <sys/user.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsipi_debug.h> 96 #include <dev/scsipi/scsiconf.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/obio.h> 100 #include <machine/dvma.h> 101 102 /* #define DEBUG XXX */ 103 104 #include <dev/ic/ncr5380reg.h> 105 #include <dev/ic/ncr5380var.h> 106 107 #include "sireg.h" 108 #include "sivar.h" 109 #include "am9516.h" 110 111 /* 112 * How many uS. to delay after touching the am9516 UDC. 113 */ 114 #define UDC_WAIT_USEC 5 115 116 void si_obio_dma_setup __P((struct ncr5380_softc *)); 117 void si_obio_dma_start __P((struct ncr5380_softc *)); 118 void si_obio_dma_eop __P((struct ncr5380_softc *)); 119 void si_obio_dma_stop __P((struct ncr5380_softc *)); 120 121 static void si_obio_reset __P((struct ncr5380_softc *)); 122 123 static __inline__ void si_obio_udc_write 124 __P((volatile struct si_regs *si, int regnum, int value)); 125 static __inline__ int si_obio_udc_read 126 __P((volatile struct si_regs *si, int regnum)); 127 128 129 /* 130 * New-style autoconfig attachment 131 */ 132 133 static int si_obio_match __P((struct device *, struct cfdata *, void *)); 134 static void si_obio_attach __P((struct device *, struct device *, void *)); 135 136 struct cfattach si_obio_ca = { 137 sizeof(struct si_softc), si_obio_match, si_obio_attach 138 }; 139 140 /* 141 * Options for disconnect/reselect, DMA, and interrupts. 142 * By default, allow disconnect/reselect on targets 4-6. 143 * Those are normally tapes that really need it enabled. 144 */ 145 int si_obio_options = 0x0f; 146 147 148 static int 149 si_obio_match(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct confargs *ca = aux; 155 156 /* We use obio_mapin(), so require OBIO. */ 157 if (ca->ca_bustype != BUS_OBIO) 158 return (0); 159 160 /* Make sure something is there... */ 161 if (bus_peek(ca->ca_bustype, ca->ca_paddr + 1, 1) == -1) 162 return (0); 163 164 /* Default interrupt priority. */ 165 if (ca->ca_intpri == -1) 166 ca->ca_intpri = 2; 167 168 return (1); 169 } 170 171 static void 172 si_obio_attach(parent, self, args) 173 struct device *parent, *self; 174 void *args; 175 { 176 struct si_softc *sc = (struct si_softc *) self; 177 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 178 struct cfdata *cf = self->dv_cfdata; 179 struct confargs *ca = args; 180 181 /* Get options from config flags if specified. */ 182 if (cf->cf_flags) 183 sc->sc_options = cf->cf_flags; 184 else 185 sc->sc_options = si_obio_options; 186 187 printf(": options=0x%x\n", sc->sc_options); 188 189 sc->sc_adapter_type = ca->ca_bustype; 190 sc->sc_regs = (struct si_regs *) 191 obio_mapin(ca->ca_paddr, sizeof(struct si_regs)); 192 193 /* 194 * MD function pointers used by the MI code. 195 */ 196 ncr_sc->sc_pio_out = ncr5380_pio_out; 197 ncr_sc->sc_pio_in = ncr5380_pio_in; 198 ncr_sc->sc_dma_alloc = si_dma_alloc; 199 ncr_sc->sc_dma_free = si_dma_free; 200 ncr_sc->sc_dma_setup = si_obio_dma_setup; 201 ncr_sc->sc_dma_start = si_obio_dma_start; 202 ncr_sc->sc_dma_poll = si_dma_poll; 203 ncr_sc->sc_dma_eop = si_obio_dma_eop; 204 ncr_sc->sc_dma_stop = si_obio_dma_stop; 205 ncr_sc->sc_intr_on = NULL; 206 ncr_sc->sc_intr_off = NULL; 207 208 /* Need DVMA-capable memory for the UDC command block. */ 209 sc->sc_dmacmd = dvma_malloc(sizeof (struct udc_table)); 210 211 /* Attach interrupt handler. */ 212 isr_add_autovect(si_intr, (void *)sc, ca->ca_intpri); 213 214 /* Reset the hardware. */ 215 si_obio_reset(ncr_sc); 216 217 /* Do the common attach stuff. */ 218 si_attach(sc); 219 } 220 221 static void 222 si_obio_reset(struct ncr5380_softc *ncr_sc) 223 { 224 struct si_softc *sc = (struct si_softc *)ncr_sc; 225 volatile struct si_regs *si = sc->sc_regs; 226 227 #ifdef DEBUG 228 if (si_debug) { 229 printf("si_obio_reset\n"); 230 } 231 #endif 232 233 /* 234 * The SCSI3 controller has an 8K FIFO to buffer data between the 235 * 5380 and the DMA. Make sure it starts out empty. 236 * 237 * The reset bits in the CSR are active low. 238 */ 239 si->si_csr = 0; 240 delay(10); 241 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 242 delay(10); 243 si->fifo_count = 0; 244 } 245 246 static __inline__ void 247 si_obio_udc_write(si, regnum, value) 248 volatile struct si_regs *si; 249 int regnum, value; 250 { 251 si->udc_addr = regnum; 252 delay(UDC_WAIT_USEC); 253 si->udc_data = value; 254 delay(UDC_WAIT_USEC); 255 } 256 257 static __inline__ int 258 si_obio_udc_read(si, regnum) 259 volatile struct si_regs *si; 260 int regnum; 261 { 262 int value; 263 264 si->udc_addr = regnum; 265 delay(UDC_WAIT_USEC); 266 value = si->udc_data; 267 delay(UDC_WAIT_USEC); 268 269 return (value); 270 } 271 272 273 /* 274 * This function is called during the COMMAND or MSG_IN phase 275 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 276 * to setup the DMA engine before the bus enters a DATA phase. 277 * 278 * The OBIO "si" IGNORES any attempt to set the FIFO count 279 * register after the SCSI bus goes into any DATA phase, so 280 * this function has to setup the evil FIFO logic. 281 */ 282 void 283 si_obio_dma_setup(ncr_sc) 284 struct ncr5380_softc *ncr_sc; 285 { 286 struct si_softc *sc = (struct si_softc *)ncr_sc; 287 struct sci_req *sr = ncr_sc->sc_current; 288 struct si_dma_handle *dh = sr->sr_dma_hand; 289 volatile struct si_regs *si = sc->sc_regs; 290 struct udc_table *cmd; 291 long data_pa, cmd_pa; 292 int xlen; 293 294 /* 295 * Get the DVMA mapping for this segment. 296 * XXX - Should separate allocation and mapin. 297 */ 298 data_pa = dvma_kvtopa(dh->dh_dvma, sc->sc_adapter_type); 299 data_pa += (ncr_sc->sc_dataptr - dh->dh_addr); 300 if (data_pa & 1) 301 panic("si_dma_start: bad pa=0x%lx", data_pa); 302 xlen = ncr_sc->sc_datalen; 303 sc->sc_reqlen = xlen; /* XXX: or less? */ 304 305 #ifdef DEBUG 306 if (si_debug & 2) { 307 printf("si_dma_setup: dh=%p, pa=0x%lx, xlen=0x%x\n", 308 dh, data_pa, xlen); 309 } 310 #endif 311 312 /* Reset the UDC. (In case not already reset?) */ 313 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 314 315 /* Reset the FIFO */ 316 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 317 si->si_csr |= SI_CSR_FIFO_RES; 318 319 /* Set direction (send/recv) */ 320 if (dh->dh_flags & SIDH_OUT) { 321 si->si_csr |= SI_CSR_SEND; 322 } else { 323 si->si_csr &= ~SI_CSR_SEND; 324 } 325 326 /* Set the FIFO counter. */ 327 si->fifo_count = xlen; 328 329 /* Reset the UDC. */ 330 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 331 332 /* 333 * XXX: Reset the FIFO again! Comment from Sprite: 334 * Go through reset again becuase of the bug on the 3/50 335 * where bytes occasionally linger in the DMA fifo. 336 */ 337 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 338 si->si_csr |= SI_CSR_FIFO_RES; 339 340 #ifdef DEBUG 341 /* Make sure the extra FIFO reset did not hit the count. */ 342 if (si->fifo_count != xlen) { 343 printf("si_dma_setup: fifo_count=0x%x, xlen=0x%x\n", 344 si->fifo_count, xlen); 345 Debugger(); 346 } 347 #endif 348 349 /* 350 * Set up the DMA controller. The DMA controller on 351 * OBIO needs a command block in DVMA space. 352 */ 353 cmd = sc->sc_dmacmd; 354 cmd->addrh = ((data_pa & 0xFF0000) >> 8) | UDC_ADDR_INFO; 355 cmd->addrl = data_pa & 0xFFFF; 356 cmd->count = xlen / 2; /* bytes -> words */ 357 cmd->cmrh = UDC_CMR_HIGH; 358 if (dh->dh_flags & SIDH_OUT) { 359 if (xlen & 1) 360 cmd->count++; 361 cmd->cmrl = UDC_CMR_LSEND; 362 cmd->rsel = UDC_RSEL_SEND; 363 } else { 364 cmd->cmrl = UDC_CMR_LRECV; 365 cmd->rsel = UDC_RSEL_RECV; 366 } 367 368 /* Tell the DMA chip where the control block is. */ 369 cmd_pa = dvma_kvtopa(cmd, BUS_OBIO); 370 si_obio_udc_write(si, UDC_ADR_CAR_HIGH, 371 (cmd_pa & 0xff0000) >> 8); 372 si_obio_udc_write(si, UDC_ADR_CAR_LOW, 373 (cmd_pa & 0xffff)); 374 375 /* Tell the chip to be a DMA master. */ 376 si_obio_udc_write(si, UDC_ADR_MODE, UDC_MODE); 377 378 /* Tell the chip to interrupt on error. */ 379 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_CIE); 380 381 /* Will do "start chain" command in _dma_start. */ 382 } 383 384 385 void 386 si_obio_dma_start(ncr_sc) 387 struct ncr5380_softc *ncr_sc; 388 { 389 struct si_softc *sc = (struct si_softc *)ncr_sc; 390 struct sci_req *sr = ncr_sc->sc_current; 391 struct si_dma_handle *dh = sr->sr_dma_hand; 392 volatile struct si_regs *si = sc->sc_regs; 393 int s; 394 395 #ifdef DEBUG 396 if (si_debug & 2) { 397 printf("si_dma_start: sr=%p\n", sr); 398 } 399 #endif 400 401 /* This MAY be time critical (not sure). */ 402 s = splhigh(); 403 404 /* Finally, give the UDC a "start chain" command. */ 405 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_STRT_CHN); 406 407 /* 408 * Acknowledge the phase change. (After DMA setup!) 409 * Put the SBIC into DMA mode, and start the transfer. 410 */ 411 if (dh->dh_flags & SIDH_OUT) { 412 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 413 SCI_CLR_INTR(ncr_sc); 414 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 415 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 416 *ncr_sc->sci_dma_send = 0; /* start it */ 417 } else { 418 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 419 SCI_CLR_INTR(ncr_sc); 420 *ncr_sc->sci_icmd = 0; 421 *ncr_sc->sci_mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 422 *ncr_sc->sci_irecv = 0; /* start it */ 423 } 424 425 splx(s); 426 ncr_sc->sc_state |= NCR_DOINGDMA; 427 428 #ifdef DEBUG 429 if (si_debug & 2) { 430 printf("si_dma_start: started, flags=0x%x\n", 431 ncr_sc->sc_state); 432 } 433 #endif 434 } 435 436 437 void 438 si_obio_dma_eop(ncr_sc) 439 struct ncr5380_softc *ncr_sc; 440 { 441 442 /* Not needed - DMA was stopped prior to examining sci_csr */ 443 } 444 445 446 void 447 si_obio_dma_stop(ncr_sc) 448 struct ncr5380_softc *ncr_sc; 449 { 450 struct si_softc *sc = (struct si_softc *)ncr_sc; 451 struct sci_req *sr = ncr_sc->sc_current; 452 struct si_dma_handle *dh = sr->sr_dma_hand; 453 volatile struct si_regs *si = sc->sc_regs; 454 int resid, ntrans, tmo, udc_cnt; 455 456 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 457 #ifdef DEBUG 458 printf("si_dma_stop: dma not running\n"); 459 #endif 460 return; 461 } 462 ncr_sc->sc_state &= ~NCR_DOINGDMA; 463 464 NCR_TRACE("si_dma_stop: top, csr=0x%x\n", si->si_csr); 465 466 /* OK, have either phase mis-match or end of DMA. */ 467 /* Set an impossible phase to prevent data movement? */ 468 *ncr_sc->sci_tcmd = PHASE_INVALID; 469 470 /* Check for DMA errors. */ 471 if (si->si_csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 472 printf("si: DMA error, csr=0x%x, reset\n", si->si_csr); 473 sr->sr_xs->error = XS_DRIVER_STUFFUP; 474 ncr_sc->sc_state |= NCR_ABORTING; 475 si_obio_reset(ncr_sc); 476 goto out; 477 } 478 479 /* Note that timeout may have set the error flag. */ 480 if (ncr_sc->sc_state & NCR_ABORTING) 481 goto out; 482 483 /* 484 * After a read, wait for the FIFO to empty. 485 * Note: this only works on the OBIO version. 486 */ 487 if ((dh->dh_flags & SIDH_OUT) == 0) { 488 tmo = 200000; /* X10 = 2 sec. */ 489 for (;;) { 490 if (si->si_csr & SI_CSR_FIFO_EMPTY) 491 break; 492 if (--tmo <= 0) { 493 printf("si: dma fifo did not empty, reset\n"); 494 ncr_sc->sc_state |= NCR_ABORTING; 495 /* si_obio_reset(ncr_sc); */ 496 goto out; 497 } 498 delay(10); 499 } 500 } 501 502 /* 503 * Now try to figure out how much actually transferred. 504 * The fifo_count might not reflect how many bytes were 505 * actually transferred. 506 */ 507 resid = si->fifo_count & 0xFFFF; 508 ntrans = sc->sc_reqlen - resid; 509 510 #ifdef DEBUG 511 if (si_debug & 2) { 512 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 513 resid, ntrans); 514 } 515 #endif 516 517 /* XXX: Treat (ntrans==0) as a special, non-error case? */ 518 if (ntrans < MIN_DMA_LEN) { 519 printf("si: fifo count: 0x%x\n", resid); 520 ncr_sc->sc_state |= NCR_ABORTING; 521 goto out; 522 } 523 if (ntrans > ncr_sc->sc_datalen) 524 panic("si_dma_stop: excess transfer"); 525 526 /* Adjust data pointer */ 527 ncr_sc->sc_dataptr += ntrans; 528 ncr_sc->sc_datalen -= ntrans; 529 530 /* 531 * After a read, we may need to clean-up 532 * "Left-over bytes" (yuck!) 533 */ 534 if ((dh->dh_flags & SIDH_OUT) == 0) { 535 /* If odd transfer count, grab last byte by hand. */ 536 if (ntrans & 1) { 537 NCR_TRACE("si_dma_stop: leftover 1 at 0x%x\n", 538 (int) ncr_sc->sc_dataptr - 1); 539 ncr_sc->sc_dataptr[-1] = 540 (si->fifo_data & 0xff00) >> 8; 541 goto out; 542 } 543 /* UDC might not have transfered the last word. */ 544 udc_cnt = si_obio_udc_read(si, UDC_ADR_COUNT); 545 if (((udc_cnt * 2) - resid) == 2) { 546 NCR_TRACE("si_dma_stop: leftover 2 at 0x%x\n", 547 (int) ncr_sc->sc_dataptr - 2); 548 ncr_sc->sc_dataptr[-2] = 549 (si->fifo_data & 0xff00) >> 8; 550 ncr_sc->sc_dataptr[-1] = 551 (si->fifo_data & 0x00ff); 552 } 553 } 554 555 out: 556 /* Reset the UDC. */ 557 si_obio_udc_write(si, UDC_ADR_COMMAND, UDC_CMD_RESET); 558 si->fifo_count = 0; 559 si->si_csr &= ~SI_CSR_SEND; 560 561 /* Reset the FIFO */ 562 si->si_csr &= ~SI_CSR_FIFO_RES; /* active low */ 563 si->si_csr |= SI_CSR_FIFO_RES; 564 565 /* Put SBIC back in PIO mode. */ 566 /* XXX: set tcmd to PHASE_INVALID? */ 567 *ncr_sc->sci_mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 568 *ncr_sc->sci_icmd = 0; 569 } 570 571