1 /* $NetBSD: si.c,v 1.34 1997/02/26 22:26:01 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, and Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains only the machine-dependent parts of the 41 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 42 * The machine-independent parts are in ncr5380sbc.c 43 * 44 * Supported hardware includes: 45 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 46 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 47 * 48 * Could be made to support the Sun3/E if someone wanted to. 49 * 50 * Note: Both supported variants of the Sun SCSI-3 adapter have 51 * some really unusual "features" for this driver to deal with, 52 * generally related to the DMA engine. The OBIO variant will 53 * ignore any attempt to write the FIFO count register while the 54 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 55 * by setting the FIFO count early in COMMAND or MSG_IN phase. 56 * 57 * The VME variant has a bit to enable or disable the DMA engine, 58 * but that bit also gates the interrupt line from the NCR5380! 59 * Therefore, in order to get any interrupt from the 5380, (i.e. 60 * for reselect) one must clear the DMA engine transfer count and 61 * then enable DMA. This has the further complication that you 62 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 63 * we have to turn DMA back off before we even look at the 5380. 64 * 65 * What wonderfully whacky hardware this is! 66 * 67 * Credits, history: 68 * 69 * David Jones wrote the initial version of this module, which 70 * included support for the VME adapter only. (no reselection). 71 * 72 * Gordon Ross added support for the OBIO adapter, and re-worked 73 * both the VME and OBIO code to support disconnect/reselect. 74 * (Required figuring out the hardware "features" noted above.) 75 * 76 * The autoconfiguration boilerplate came from Adam Glass. 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/malloc.h> 84 #include <sys/device.h> 85 #include <sys/buf.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 89 #include <scsi/scsi_all.h> 90 #include <scsi/scsi_debug.h> 91 #include <scsi/scsiconf.h> 92 93 #include <machine/autoconf.h> 94 #include <machine/dvma.h> 95 96 #define DEBUG XXX 97 98 #include <dev/ic/ncr5380reg.h> 99 #include <dev/ic/ncr5380var.h> 100 101 #include "sireg.h" 102 #include "sivar.h" 103 104 /* 105 * Transfers smaller than this are done using PIO 106 * (on assumption they're not worth DMA overhead) 107 */ 108 #define MIN_DMA_LEN 128 109 110 int si_debug = 0; 111 #ifdef DEBUG 112 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 113 #endif 114 115 /* How long to wait for DMA before declaring an error. */ 116 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 117 118 static void si_minphys __P((struct buf *)); 119 120 static struct scsi_adapter si_ops = { 121 ncr5380_scsi_cmd, /* scsi_cmd() */ 122 si_minphys, /* scsi_minphys() */ 123 NULL, /* open_target_lu() */ 124 NULL, /* close_target_lu() */ 125 }; 126 127 /* This is copied from julian's bt driver */ 128 /* "so we have a default dev struct for our link struct." */ 129 static struct scsi_device si_dev = { 130 NULL, /* Use default error handler. */ 131 NULL, /* Use default start handler. */ 132 NULL, /* Use default async handler. */ 133 NULL, /* Use default "done" routine. */ 134 }; 135 136 /* 137 * New-style autoconfig attachment. The cfattach 138 * structures are in si_obio.c and si_vme.c 139 */ 140 141 struct cfdriver si_cd = { 142 NULL, "si", DV_DULL 143 }; 144 145 146 void 147 si_attach(sc) 148 struct si_softc *sc; 149 { 150 struct ncr5380_softc *ncr_sc = (void *)sc; 151 volatile struct si_regs *regs = sc->sc_regs; 152 int i; 153 154 /* 155 * Support the "options" (config file flags). 156 * Disconnect/reselect is a per-target mask. 157 * Interrupts and DMA are per-controller. 158 */ 159 ncr_sc->sc_no_disconnect = 160 (sc->sc_options & SI_NO_DISCONNECT); 161 ncr_sc->sc_parity_disable = 162 (sc->sc_options & SI_NO_PARITY_CHK) >> 8; 163 if (sc->sc_options & SI_FORCE_POLLING) 164 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 165 166 #if 1 /* XXX - Temporary */ 167 /* XXX - In case we think DMA is completely broken... */ 168 if (sc->sc_options & SI_DISABLE_DMA) { 169 /* Override this function pointer. */ 170 ncr_sc->sc_dma_alloc = NULL; 171 } 172 #endif 173 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 174 175 /* 176 * Fill in the prototype scsi_link. 177 */ 178 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 179 ncr_sc->sc_link.adapter_softc = sc; 180 ncr_sc->sc_link.adapter_target = 7; 181 ncr_sc->sc_link.adapter = &si_ops; 182 ncr_sc->sc_link.device = &si_dev; 183 184 #ifdef DEBUG 185 if (si_debug) 186 printf("si: Set TheSoftC=%p TheRegs=%p\n", sc, regs); 187 ncr_sc->sc_link.flags |= si_link_flags; 188 #endif 189 190 /* 191 * Initialize fields used by the MI code 192 */ 193 ncr_sc->sci_r0 = ®s->sci.sci_r0; 194 ncr_sc->sci_r1 = ®s->sci.sci_r1; 195 ncr_sc->sci_r2 = ®s->sci.sci_r2; 196 ncr_sc->sci_r3 = ®s->sci.sci_r3; 197 ncr_sc->sci_r4 = ®s->sci.sci_r4; 198 ncr_sc->sci_r5 = ®s->sci.sci_r5; 199 ncr_sc->sci_r6 = ®s->sci.sci_r6; 200 ncr_sc->sci_r7 = ®s->sci.sci_r7; 201 202 /* 203 * Allocate DMA handles. 204 */ 205 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 206 sc->sc_dma = (struct si_dma_handle *) 207 malloc(i, M_DEVBUF, M_WAITOK); 208 if (sc->sc_dma == NULL) 209 panic("si: dvma_malloc failed\n"); 210 for (i = 0; i < SCI_OPENINGS; i++) 211 sc->sc_dma[i].dh_flags = 0; 212 213 /* 214 * Initialize si board itself. 215 */ 216 si_reset_adapter(ncr_sc); 217 ncr5380_init(ncr_sc); 218 ncr5380_reset_scsibus(ncr_sc); 219 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 220 } 221 222 static void 223 si_minphys(struct buf *bp) 224 { 225 if (bp->b_bcount > MAX_DMA_LEN) { 226 #ifdef DEBUG 227 if (si_debug) { 228 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 229 Debugger(); 230 } 231 #endif 232 bp->b_bcount = MAX_DMA_LEN; 233 } 234 return (minphys(bp)); 235 } 236 237 238 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 239 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 240 241 int 242 si_intr(void *arg) 243 { 244 struct si_softc *sc = arg; 245 volatile struct si_regs *si = sc->sc_regs; 246 int dma_error, claimed; 247 u_short csr; 248 249 claimed = 0; 250 dma_error = 0; 251 252 /* SBC interrupt? DMA interrupt? */ 253 csr = si->si_csr; 254 NCR_TRACE("si_intr: csr=0x%x\n", csr); 255 256 if (csr & SI_CSR_DMA_CONFLICT) { 257 dma_error |= SI_CSR_DMA_CONFLICT; 258 printf("si_intr: DMA conflict\n"); 259 } 260 if (csr & SI_CSR_DMA_BUS_ERR) { 261 dma_error |= SI_CSR_DMA_BUS_ERR; 262 printf("si_intr: DMA bus error\n"); 263 } 264 if (dma_error) { 265 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 266 sc->ncr_sc.sc_state |= NCR_ABORTING; 267 /* Make sure we will call the main isr. */ 268 csr |= SI_CSR_DMA_IP; 269 } 270 271 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 272 claimed = ncr5380_intr(&sc->ncr_sc); 273 #ifdef DEBUG 274 if (!claimed) { 275 printf("si_intr: spurious from SBC\n"); 276 if (si_debug & 4) { 277 Debugger(); /* XXX */ 278 } 279 } 280 #endif 281 } 282 283 return (claimed); 284 } 285 286 287 void 288 si_reset_adapter(struct ncr5380_softc *ncr_sc) 289 { 290 struct si_softc *sc = (struct si_softc *)ncr_sc; 291 volatile struct si_regs *si = sc->sc_regs; 292 293 #ifdef DEBUG 294 if (si_debug) { 295 printf("si_reset_adapter\n"); 296 } 297 #endif 298 299 /* 300 * The SCSI3 controller has an 8K FIFO to buffer data between the 301 * 5380 and the DMA. Make sure it starts out empty. 302 * 303 * The reset bits in the CSR are active low. 304 */ 305 si->si_csr = 0; 306 delay(10); 307 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 308 delay(10); 309 si->fifo_count = 0; 310 311 if (sc->sc_adapter_type == BUS_VME16) { 312 si->dma_addrh = 0; 313 si->dma_addrl = 0; 314 si->dma_counth = 0; 315 si->dma_countl = 0; 316 si->si_iv_am = sc->sc_adapter_iv_am; 317 si->fifo_cnt_hi = 0; 318 } 319 320 SCI_CLR_INTR(ncr_sc); 321 } 322 323 324 /***************************************************************** 325 * Common functions for DMA 326 ****************************************************************/ 327 328 /* 329 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 330 * for DMA transfer. On the Sun3, this means mapping the buffer 331 * into DVMA space. dvma_mapin() flushes the cache for us. 332 */ 333 void 334 si_dma_alloc(ncr_sc) 335 struct ncr5380_softc *ncr_sc; 336 { 337 struct si_softc *sc = (struct si_softc *)ncr_sc; 338 struct sci_req *sr = ncr_sc->sc_current; 339 struct scsi_xfer *xs = sr->sr_xs; 340 struct si_dma_handle *dh; 341 int i, xlen; 342 u_long addr; 343 344 #ifdef DIAGNOSTIC 345 if (sr->sr_dma_hand != NULL) 346 panic("si_dma_alloc: already have DMA handle"); 347 #endif 348 349 addr = (u_long) ncr_sc->sc_dataptr; 350 xlen = ncr_sc->sc_datalen; 351 352 /* If the DMA start addr is misaligned then do PIO */ 353 if ((addr & 1) || (xlen & 1)) { 354 printf("si_dma_alloc: misaligned.\n"); 355 return; 356 } 357 358 /* Make sure our caller checked sc_min_dma_len. */ 359 if (xlen < MIN_DMA_LEN) 360 panic("si_dma_alloc: xlen=0x%x\n", xlen); 361 362 /* 363 * Never attempt single transfers of more than 63k, because 364 * our count register may be only 16 bits (an OBIO adapter). 365 * This should never happen since already bounded by minphys(). 366 * XXX - Should just segment these... 367 */ 368 if (xlen > MAX_DMA_LEN) { 369 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 370 Debugger(); 371 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 372 } 373 374 /* Find free DMA handle. Guaranteed to find one since we have 375 as many DMA handles as the driver has processes. */ 376 for (i = 0; i < SCI_OPENINGS; i++) { 377 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 378 goto found; 379 } 380 panic("si: no free DMA handles."); 381 found: 382 383 dh = &sc->sc_dma[i]; 384 dh->dh_flags = SIDH_BUSY; 385 dh->dh_addr = (u_char*) addr; 386 dh->dh_maplen = xlen; 387 dh->dh_dvma = 0; 388 389 /* Copy the "write" flag for convenience. */ 390 if (xs->flags & SCSI_DATA_OUT) 391 dh->dh_flags |= SIDH_OUT; 392 393 #if 0 394 /* 395 * Some machines might not need to remap B_PHYS buffers. 396 * The sun3 does not map B_PHYS buffers into DVMA space, 397 * (they are mapped into normal KV space) so on the sun3 398 * we must always remap to a DVMA address here. Re-map is 399 * cheap anyway, because it's done by segments, not pages. 400 */ 401 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 402 dh->dh_flags |= SIDH_PHYS; 403 #endif 404 405 dh->dh_dvma = (u_long) dvma_mapin((char *)addr, xlen); 406 if (!dh->dh_dvma) { 407 /* Can't remap segment */ 408 printf("si_dma_alloc: can't remap %p/0x%x\n", 409 dh->dh_addr, dh->dh_maplen); 410 dh->dh_flags = 0; 411 return; 412 } 413 414 /* success */ 415 sr->sr_dma_hand = dh; 416 417 return; 418 } 419 420 421 void 422 si_dma_free(ncr_sc) 423 struct ncr5380_softc *ncr_sc; 424 { 425 struct sci_req *sr = ncr_sc->sc_current; 426 struct si_dma_handle *dh = sr->sr_dma_hand; 427 428 #ifdef DIAGNOSTIC 429 if (dh == NULL) 430 panic("si_dma_free: no DMA handle"); 431 #endif 432 433 if (ncr_sc->sc_state & NCR_DOINGDMA) 434 panic("si_dma_free: free while in progress"); 435 436 if (dh->dh_flags & SIDH_BUSY) { 437 /* XXX - Should separate allocation and mapping. */ 438 /* Give back the DVMA space. */ 439 dvma_mapout((caddr_t)dh->dh_dvma, dh->dh_maplen); 440 dh->dh_dvma = 0; 441 dh->dh_flags = 0; 442 } 443 sr->sr_dma_hand = NULL; 444 } 445 446 447 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 448 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 449 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 450 451 /* 452 * Poll (spin-wait) for DMA completion. 453 * Called right after xx_dma_start(), and 454 * xx_dma_stop() will be called next. 455 * Same for either VME or OBIO. 456 */ 457 void 458 si_dma_poll(ncr_sc) 459 struct ncr5380_softc *ncr_sc; 460 { 461 struct si_softc *sc = (struct si_softc *)ncr_sc; 462 struct sci_req *sr = ncr_sc->sc_current; 463 volatile struct si_regs *si = sc->sc_regs; 464 int tmo; 465 466 /* Make sure DMA started successfully. */ 467 if (ncr_sc->sc_state & NCR_ABORTING) 468 return; 469 470 /* 471 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 472 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 473 * XXX: I really doubt that is necessary... 474 */ 475 476 /* Wait for any "dma complete" or error bits. */ 477 tmo = POLL_TIMO; 478 for (;;) { 479 if (si->si_csr & CSR_MASK) 480 break; 481 if (--tmo <= 0) { 482 printf("si: DMA timeout (while polling)\n"); 483 /* Indicate timeout as MI code would. */ 484 sr->sr_flags |= SR_OVERDUE; 485 break; 486 } 487 delay(100); 488 } 489 NCR_TRACE("si_dma_poll: waited %d\n", 490 POLL_TIMO - tmo); 491 492 #ifdef DEBUG 493 if (si_debug & 2) { 494 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 495 } 496 #endif 497 } 498 499