1 /* $NetBSD: si.c,v 1.30 1996/10/30 00:24:38 gwr Exp $ */ 2 3 /* 4 * Copyright (c) 1995 David Jones, Gordon W. Ross 5 * Copyright (c) 1994 Adam Glass 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the authors may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by 21 * Adam Glass, David Jones, and Gordon Ross 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * This file contains only the machine-dependent parts of the 37 * Sun3 SCSI driver. (Autoconfig stuff and DMA functions.) 38 * The machine-independent parts are in ncr5380sbc.c 39 * 40 * Supported hardware includes: 41 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60) 42 * Sun SCSI-3 on VME (Sun3/160,Sun3/260) 43 * 44 * Could be made to support the Sun3/E if someone wanted to. 45 * 46 * Note: Both supported variants of the Sun SCSI-3 adapter have 47 * some really unusual "features" for this driver to deal with, 48 * generally related to the DMA engine. The OBIO variant will 49 * ignore any attempt to write the FIFO count register while the 50 * SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with 51 * by setting the FIFO count early in COMMAND or MSG_IN phase. 52 * 53 * The VME variant has a bit to enable or disable the DMA engine, 54 * but that bit also gates the interrupt line from the NCR5380! 55 * Therefore, in order to get any interrupt from the 5380, (i.e. 56 * for reselect) one must clear the DMA engine transfer count and 57 * then enable DMA. This has the further complication that you 58 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 59 * we have to turn DMA back off before we even look at the 5380. 60 * 61 * What wonderfully whacky hardware this is! 62 * 63 * Credits, history: 64 * 65 * David Jones wrote the initial version of this module, which 66 * included support for the VME adapter only. (no reselection). 67 * 68 * Gordon Ross added support for the OBIO adapter, and re-worked 69 * both the VME and OBIO code to support disconnect/reselect. 70 * (Required figuring out the hardware "features" noted above.) 71 * 72 * The autoconfiguration boilerplate came from Adam Glass. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/errno.h> 78 #include <sys/kernel.h> 79 #include <sys/malloc.h> 80 #include <sys/device.h> 81 #include <sys/buf.h> 82 #include <sys/proc.h> 83 #include <sys/user.h> 84 85 #include <scsi/scsi_all.h> 86 #include <scsi/scsi_debug.h> 87 #include <scsi/scsiconf.h> 88 89 #include <machine/autoconf.h> 90 #include <machine/isr.h> 91 #include <machine/obio.h> 92 #include <machine/dvma.h> 93 94 #define DEBUG XXX 95 96 #include <dev/ic/ncr5380reg.h> 97 #include <dev/ic/ncr5380var.h> 98 99 #include "sireg.h" 100 #include "sivar.h" 101 102 /* 103 * Transfers smaller than this are done using PIO 104 * (on assumption they're not worth DMA overhead) 105 */ 106 #define MIN_DMA_LEN 128 107 108 int si_debug = 0; 109 #ifdef DEBUG 110 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 111 #endif 112 113 /* How long to wait for DMA before declaring an error. */ 114 int si_dma_intr_timo = 500; /* ticks (sec. X 100) */ 115 116 static void si_minphys __P((struct buf *)); 117 118 static struct scsi_adapter si_ops = { 119 ncr5380_scsi_cmd, /* scsi_cmd() */ 120 si_minphys, /* scsi_minphys() */ 121 NULL, /* open_target_lu() */ 122 NULL, /* close_target_lu() */ 123 }; 124 125 /* This is copied from julian's bt driver */ 126 /* "so we have a default dev struct for our link struct." */ 127 static struct scsi_device si_dev = { 128 NULL, /* Use default error handler. */ 129 NULL, /* Use default start handler. */ 130 NULL, /* Use default async handler. */ 131 NULL, /* Use default "done" routine. */ 132 }; 133 134 /* 135 * New-style autoconfig attachment. The cfattach 136 * structures are in si_obio.c and si_vme.c 137 */ 138 139 struct cfdriver si_cd = { 140 NULL, "si", DV_DULL 141 }; 142 143 144 void 145 si_attach(sc) 146 struct si_softc *sc; 147 { 148 struct ncr5380_softc *ncr_sc = (void *)sc; 149 volatile struct si_regs *regs = sc->sc_regs; 150 int i; 151 152 /* 153 * Support the "options" (config file flags). 154 */ 155 if ((sc->sc_options & SI_DO_RESELECT) != 0) 156 ncr_sc->sc_flags |= NCR5380_PERMIT_RESELECT; 157 if ((sc->sc_options & SI_DMA_INTR) == 0) 158 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 159 #if 1 /* XXX - Temporary */ 160 /* XXX - In case we think DMA is completely broken... */ 161 if ((sc->sc_options & SI_ENABLE_DMA) == 0) { 162 /* Override this function pointer. */ 163 ncr_sc->sc_dma_alloc = NULL; 164 } 165 #endif 166 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 167 168 /* 169 * Fill in the prototype scsi_link. 170 */ 171 ncr_sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 172 ncr_sc->sc_link.adapter_softc = sc; 173 ncr_sc->sc_link.adapter_target = 7; 174 ncr_sc->sc_link.adapter = &si_ops; 175 ncr_sc->sc_link.device = &si_dev; 176 177 #ifdef DEBUG 178 if (si_debug) 179 printf("si: Set TheSoftC=%x TheRegs=%x\n", sc, regs); 180 ncr_sc->sc_link.flags |= si_link_flags; 181 #endif 182 183 /* 184 * Initialize fields used by the MI code 185 */ 186 ncr_sc->sci_r0 = ®s->sci.sci_r0; 187 ncr_sc->sci_r1 = ®s->sci.sci_r1; 188 ncr_sc->sci_r2 = ®s->sci.sci_r2; 189 ncr_sc->sci_r3 = ®s->sci.sci_r3; 190 ncr_sc->sci_r4 = ®s->sci.sci_r4; 191 ncr_sc->sci_r5 = ®s->sci.sci_r5; 192 ncr_sc->sci_r6 = ®s->sci.sci_r6; 193 ncr_sc->sci_r7 = ®s->sci.sci_r7; 194 195 /* 196 * Allocate DMA handles. 197 */ 198 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 199 sc->sc_dma = (struct si_dma_handle *) 200 malloc(i, M_DEVBUF, M_WAITOK); 201 if (sc->sc_dma == NULL) 202 panic("si: dvma_malloc failed\n"); 203 for (i = 0; i < SCI_OPENINGS; i++) 204 sc->sc_dma[i].dh_flags = 0; 205 206 /* 207 * Initialize si board itself. 208 */ 209 si_reset_adapter(ncr_sc); 210 ncr5380_init(ncr_sc); 211 ncr5380_reset_scsibus(ncr_sc); 212 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 213 } 214 215 static void 216 si_minphys(struct buf *bp) 217 { 218 if (bp->b_bcount > MAX_DMA_LEN) { 219 #ifdef DEBUG 220 if (si_debug) { 221 printf("si_minphys len = 0x%x.\n", bp->b_bcount); 222 Debugger(); 223 } 224 #endif 225 bp->b_bcount = MAX_DMA_LEN; 226 } 227 return (minphys(bp)); 228 } 229 230 231 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 232 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 233 234 int 235 si_intr(void *arg) 236 { 237 struct si_softc *sc = arg; 238 volatile struct si_regs *si = sc->sc_regs; 239 int dma_error, claimed; 240 u_short csr; 241 242 claimed = 0; 243 dma_error = 0; 244 245 /* SBC interrupt? DMA interrupt? */ 246 csr = si->si_csr; 247 NCR_TRACE("si_intr: csr=0x%x\n", csr); 248 249 if (csr & SI_CSR_DMA_CONFLICT) { 250 dma_error |= SI_CSR_DMA_CONFLICT; 251 printf("si_intr: DMA conflict\n"); 252 } 253 if (csr & SI_CSR_DMA_BUS_ERR) { 254 dma_error |= SI_CSR_DMA_BUS_ERR; 255 printf("si_intr: DMA bus error\n"); 256 } 257 if (dma_error) { 258 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 259 sc->ncr_sc.sc_state |= NCR_ABORTING; 260 /* Make sure we will call the main isr. */ 261 csr |= SI_CSR_DMA_IP; 262 } 263 264 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 265 claimed = ncr5380_intr(&sc->ncr_sc); 266 #ifdef DEBUG 267 if (!claimed) { 268 printf("si_intr: spurious from SBC\n"); 269 if (si_debug & 4) { 270 Debugger(); /* XXX */ 271 } 272 } 273 #endif 274 } 275 276 return (claimed); 277 } 278 279 280 void 281 si_reset_adapter(struct ncr5380_softc *ncr_sc) 282 { 283 struct si_softc *sc = (struct si_softc *)ncr_sc; 284 volatile struct si_regs *si = sc->sc_regs; 285 286 #ifdef DEBUG 287 if (si_debug) { 288 printf("si_reset_adapter\n"); 289 } 290 #endif 291 292 /* 293 * The SCSI3 controller has an 8K FIFO to buffer data between the 294 * 5380 and the DMA. Make sure it starts out empty. 295 * 296 * The reset bits in the CSR are active low. 297 */ 298 si->si_csr = 0; 299 delay(10); 300 si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN; 301 delay(10); 302 si->fifo_count = 0; 303 304 if (sc->sc_adapter_type == BUS_VME16) { 305 si->dma_addrh = 0; 306 si->dma_addrl = 0; 307 si->dma_counth = 0; 308 si->dma_countl = 0; 309 si->si_iv_am = sc->sc_adapter_iv_am; 310 si->fifo_cnt_hi = 0; 311 } 312 313 SCI_CLR_INTR(ncr_sc); 314 } 315 316 317 /***************************************************************** 318 * Common functions for DMA 319 ****************************************************************/ 320 321 /* 322 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 323 * for DMA transfer. On the Sun3, this means mapping the buffer 324 * into DVMA space. dvma_mapin() flushes the cache for us. 325 */ 326 void 327 si_dma_alloc(ncr_sc) 328 struct ncr5380_softc *ncr_sc; 329 { 330 struct si_softc *sc = (struct si_softc *)ncr_sc; 331 struct sci_req *sr = ncr_sc->sc_current; 332 struct scsi_xfer *xs = sr->sr_xs; 333 struct si_dma_handle *dh; 334 int i, xlen; 335 u_long addr; 336 337 #ifdef DIAGNOSTIC 338 if (sr->sr_dma_hand != NULL) 339 panic("si_dma_alloc: already have DMA handle"); 340 #endif 341 342 addr = (u_long) ncr_sc->sc_dataptr; 343 xlen = ncr_sc->sc_datalen; 344 345 /* If the DMA start addr is misaligned then do PIO */ 346 if ((addr & 1) || (xlen & 1)) { 347 printf("si_dma_alloc: misaligned.\n"); 348 return; 349 } 350 351 /* Make sure our caller checked sc_min_dma_len. */ 352 if (xlen < MIN_DMA_LEN) 353 panic("si_dma_alloc: xlen=0x%x\n", xlen); 354 355 /* 356 * Never attempt single transfers of more than 63k, because 357 * our count register may be only 16 bits (an OBIO adapter). 358 * This should never happen since already bounded by minphys(). 359 * XXX - Should just segment these... 360 */ 361 if (xlen > MAX_DMA_LEN) { 362 printf("si_dma_alloc: excessive xlen=0x%x\n", xlen); 363 Debugger(); 364 ncr_sc->sc_datalen = xlen = MAX_DMA_LEN; 365 } 366 367 /* Find free DMA handle. Guaranteed to find one since we have 368 as many DMA handles as the driver has processes. */ 369 for (i = 0; i < SCI_OPENINGS; i++) { 370 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 371 goto found; 372 } 373 panic("si: no free DMA handles."); 374 found: 375 376 dh = &sc->sc_dma[i]; 377 dh->dh_flags = SIDH_BUSY; 378 dh->dh_addr = (u_char*) addr; 379 dh->dh_maplen = xlen; 380 dh->dh_dvma = 0; 381 382 /* Copy the "write" flag for convenience. */ 383 if (xs->flags & SCSI_DATA_OUT) 384 dh->dh_flags |= SIDH_OUT; 385 386 #if 0 387 /* 388 * Some machines might not need to remap B_PHYS buffers. 389 * The sun3 does not map B_PHYS buffers into DVMA space, 390 * (they are mapped into normal KV space) so on the sun3 391 * we must always remap to a DVMA address here. Re-map is 392 * cheap anyway, because it's done by segments, not pages. 393 */ 394 if (xs->bp && (xs->bp->b_flags & B_PHYS)) 395 dh->dh_flags |= SIDH_PHYS; 396 #endif 397 398 dh->dh_dvma = (u_long) dvma_mapin((char *)addr, xlen); 399 if (!dh->dh_dvma) { 400 /* Can't remap segment */ 401 printf("si_dma_alloc: can't remap %x/%x\n", 402 dh->dh_addr, dh->dh_maplen); 403 dh->dh_flags = 0; 404 return; 405 } 406 407 /* success */ 408 sr->sr_dma_hand = dh; 409 410 return; 411 } 412 413 414 void 415 si_dma_free(ncr_sc) 416 struct ncr5380_softc *ncr_sc; 417 { 418 struct sci_req *sr = ncr_sc->sc_current; 419 struct si_dma_handle *dh = sr->sr_dma_hand; 420 421 #ifdef DIAGNOSTIC 422 if (dh == NULL) 423 panic("si_dma_free: no DMA handle"); 424 #endif 425 426 if (ncr_sc->sc_state & NCR_DOINGDMA) 427 panic("si_dma_free: free while in progress"); 428 429 if (dh->dh_flags & SIDH_BUSY) { 430 /* XXX - Should separate allocation and mapping. */ 431 /* Give back the DVMA space. */ 432 dvma_mapout((caddr_t)dh->dh_dvma, dh->dh_maplen); 433 dh->dh_dvma = 0; 434 dh->dh_flags = 0; 435 } 436 sr->sr_dma_hand = NULL; 437 } 438 439 440 #define CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 441 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR) 442 #define POLL_TIMO 50000 /* X100 = 5 sec. */ 443 444 /* 445 * Poll (spin-wait) for DMA completion. 446 * Called right after xx_dma_start(), and 447 * xx_dma_stop() will be called next. 448 * Same for either VME or OBIO. 449 */ 450 void 451 si_dma_poll(ncr_sc) 452 struct ncr5380_softc *ncr_sc; 453 { 454 struct si_softc *sc = (struct si_softc *)ncr_sc; 455 struct sci_req *sr = ncr_sc->sc_current; 456 struct si_dma_handle *dh = sr->sr_dma_hand; 457 volatile struct si_regs *si = sc->sc_regs; 458 int tmo; 459 460 /* Make sure DMA started successfully. */ 461 if (ncr_sc->sc_state & NCR_ABORTING) 462 return; 463 464 /* 465 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here 466 * XXX: (on obio) or even worse (on vme) a 10mS. delay! 467 * XXX: I really doubt that is necessary... 468 */ 469 470 /* Wait for any "dma complete" or error bits. */ 471 tmo = POLL_TIMO; 472 for (;;) { 473 if (si->si_csr & CSR_MASK) 474 break; 475 if (--tmo <= 0) { 476 printf("si: DMA timeout (while polling)\n"); 477 /* Indicate timeout as MI code would. */ 478 sr->sr_flags |= SR_OVERDUE; 479 break; 480 } 481 delay(100); 482 } 483 NCR_TRACE("si_dma_poll: waited %d\n", 484 POLL_TIMO - tmo); 485 486 #ifdef DEBUG 487 if (si_debug & 2) { 488 printf("si_dma_poll: done, csr=0x%x\n", si->si_csr); 489 } 490 #endif 491 } 492 493