1 /* $NetBSD: dma.c,v 1.10 1999/04/08 04:46:41 gwr Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Paul Kranenburg. All rights reserved. 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Peter Galbavy. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/dvma.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <dev/ic/ncr53c9xreg.h> 49 #include <dev/ic/ncr53c9xvar.h> 50 51 #include <sun3/dev/dmareg.h> 52 #include <sun3/dev/dmavar.h> 53 54 #define MAX_DMA_SZ 0x01000000 /* 16MB */ 55 56 static int dmamatch __P((struct device *, struct cfdata *, void *)); 57 static void dmaattach __P((struct device *, struct device *, void *)); 58 59 struct cfattach dma_ca = { 60 sizeof(struct dma_softc), dmamatch, dmaattach 61 }; 62 63 extern struct cfdriver dma_cd; 64 65 static int 66 dmamatch(parent, cf, aux) 67 struct device *parent; 68 struct cfdata *cf; 69 void *aux; 70 { 71 struct confargs *ca = aux; 72 73 /* 74 * Check for the DMA registers. 75 */ 76 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 4) == -1) 77 return (0); 78 79 /* If default ipl, fill it in. */ 80 if (ca->ca_intpri == -1) 81 ca->ca_intpri = 2; 82 83 return (1); 84 } 85 86 static void 87 dmaattach(parent, self, aux) 88 struct device *parent, *self; 89 void *aux; 90 { 91 struct confargs *ca = aux; 92 struct dma_softc *sc = (void *)self; 93 int id; 94 95 #if 0 96 /* indirect functions */ 97 sc->intr = espdmaintr; 98 sc->setup = dma_setup; 99 sc->reset = dma_reset; 100 #endif 101 102 /* 103 * Map in the registers. 104 */ 105 sc->sc_regs = bus_mapin(ca->ca_bustype, ca->ca_paddr, 106 sizeof(struct dma_regs)); 107 sc->sc_rev = DMACSR(sc) & D_DEV_ID; 108 id = (sc->sc_rev >> 28) & 0xf; 109 printf(": rev %d\n", id); 110 111 /* 112 * Make sure the DMA chip is supported revision. 113 * The Sun3/80 used only the old rev zero chip, 114 * so the initialization has been simplified. 115 */ 116 switch (sc->sc_rev) { 117 case DMAREV_0: 118 case DMAREV_1: 119 break; 120 default: 121 panic("unsupported dma rev"); 122 } 123 } 124 125 /* 126 * This is called by espattach to get our softc. 127 */ 128 struct dma_softc * 129 espdmafind(int unit) 130 { 131 if (unit < 0 || unit >= dma_cd.cd_ndevs || 132 dma_cd.cd_devs[unit] == NULL) 133 panic("no dma"); 134 return (dma_cd.cd_devs[unit]); 135 } 136 137 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 138 int count = 100000; \ 139 while ((COND) && --count > 0) DELAY(5); \ 140 if (count == 0) { \ 141 printf("%s: line %d: CSR = 0x%x\n", \ 142 __FILE__, __LINE__, DMACSR(SC)); \ 143 if (DONTPANIC) \ 144 printf(MSG); \ 145 else \ 146 panic(MSG); \ 147 } \ 148 } while (0) 149 150 #define DMA_DRAIN(sc, dontpanic) do { \ 151 /* \ 152 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 153 * and "drain" bits while it is still thinking about a \ 154 * request. \ 155 * other revs: D_R_PEND bit reads as 0 \ 156 */ \ 157 DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 158 /* \ 159 * Select drain bit (always rev 0,1) \ 160 * also clears errors and D_TC flag \ 161 */ \ 162 DMACSR(sc) |= D_DRAIN; \ 163 /* \ 164 * Wait for draining to finish \ 165 */ \ 166 DMAWAIT(sc, DMACSR(sc) & D_PACKCNT, "DRAINING", dontpanic); \ 167 } while(0) 168 169 #define DMA_FLUSH(sc, dontpanic) do { \ 170 /* \ 171 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 172 * and "drain" bits while it is still thinking about a \ 173 * request. \ 174 * other revs: D_R_PEND bit reads as 0 \ 175 */ \ 176 DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 177 DMACSR(sc) &= ~(D_WRITE|D_EN_DMA); \ 178 DMACSR(sc) |= D_FLUSH; \ 179 } while(0) 180 181 void 182 dma_reset(sc) 183 struct dma_softc *sc; 184 { 185 186 DMA_FLUSH(sc, 1); 187 DMACSR(sc) |= D_RESET; /* reset DMA */ 188 DELAY(200); /* what should this be ? */ 189 /*DMAWAIT1(sc); why was this here? */ 190 DMACSR(sc) &= ~D_RESET; /* de-assert reset line */ 191 DELAY(5); /* allow a few ticks to settle */ 192 193 /* 194 * Get transfer burst size from (?) and plug it into the 195 * controller registers. This is needed on the Sun4m... 196 * Do we need it too? Apparently not, because the 3/80 197 * always has the old, REV zero DMA chip. 198 */ 199 DMACSR(sc) |= D_INT_EN; /* enable interrupts */ 200 201 sc->sc_active = 0; 202 } 203 204 205 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 206 207 /* 208 * setup a dma transfer 209 */ 210 int 211 dma_setup(sc, addr, len, datain, dmasize) 212 struct dma_softc *sc; 213 caddr_t *addr; 214 size_t *len; 215 int datain; 216 size_t *dmasize; /* IN-OUT */ 217 { 218 u_int32_t csr; 219 220 DMA_FLUSH(sc, 0); 221 222 #if 0 223 DMACSR(sc) &= ~D_INT_EN; 224 #endif 225 sc->sc_dmaaddr = addr; 226 sc->sc_dmalen = len; 227 228 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 229 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 230 231 /* 232 * the rules say we cannot transfer more than the limit 233 * of this DMA chip (64k for old and 16Mb for new), 234 * and we cannot cross a 16Mb boundary. 235 */ 236 *dmasize = sc->sc_dmasize = 237 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 238 239 NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 240 241 /* Program the DMA address */ 242 if (sc->sc_dmasize) { 243 /* 244 * Use dvma mapin routines to map the buffer into DVMA space. 245 */ 246 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 247 sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr, 248 sc->sc_dmasize, 0); 249 if (sc->sc_dvmakaddr == NULL) 250 panic("dma: cannot allocate DVMA address"); 251 sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO); 252 DMADDR(sc) = sc->sc_dmasaddr; 253 } else { 254 /* XXX: What is this about? -gwr */ 255 DMADDR(sc) = (u_int32_t) *sc->sc_dmaaddr; 256 } 257 258 /* We never have DMAREV_ESC. */ 259 260 /* Setup DMA control register */ 261 csr = DMACSR(sc); 262 if (datain) 263 csr |= D_WRITE; 264 else 265 csr &= ~D_WRITE; 266 csr |= D_INT_EN; 267 DMACSR(sc) = csr; 268 269 return 0; 270 } 271 272 /* 273 * Pseudo (chained) interrupt from the esp driver to kick the 274 * current running DMA transfer. I am relying on espintr() to 275 * pickup and clean errors for now 276 * 277 * return 1 if it was a DMA continue. 278 */ 279 int 280 espdmaintr(sc) 281 struct dma_softc *sc; 282 { 283 struct ncr53c9x_softc *nsc = sc->sc_esp; 284 char bits[64]; 285 int trans, resid; 286 u_int32_t csr; 287 288 csr = DMACSR(sc); 289 290 NCR_DMA(("%s: intr: addr 0x%x, csr %s\n", 291 sc->sc_dev.dv_xname, DMADDR(sc), 292 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)))); 293 294 if (csr & D_ERR_PEND) { 295 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 296 DMACSR(sc) |= D_FLUSH; 297 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 298 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 299 return (-1); 300 } 301 302 /* This is an "assertion" :) */ 303 if (sc->sc_active == 0) 304 panic("dmaintr: DMA wasn't active"); 305 306 DMA_DRAIN(sc, 0); 307 308 /* DMA has stopped */ 309 DMACSR(sc) &= ~D_EN_DMA; 310 sc->sc_active = 0; 311 312 if (sc->sc_dmasize == 0) { 313 /* A "Transfer Pad" operation completed */ 314 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 315 NCR_READ_REG(nsc, NCR_TCL) | 316 (NCR_READ_REG(nsc, NCR_TCM) << 8), 317 NCR_READ_REG(nsc, NCR_TCL), 318 NCR_READ_REG(nsc, NCR_TCM))); 319 return 0; 320 } 321 322 resid = 0; 323 /* 324 * If a transfer onto the SCSI bus gets interrupted by the device 325 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 326 * as residual since the ESP counter registers get decremented as 327 * bytes are clocked into the FIFO. 328 */ 329 if (!(csr & D_WRITE) && 330 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 331 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 332 } 333 334 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 335 /* 336 * `Terminal count' is off, so read the residue 337 * out of the ESP counter registers. 338 */ 339 resid += (NCR_READ_REG(nsc, NCR_TCL) | 340 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 341 ((nsc->sc_cfg2 & NCRCFG2_FE) 342 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 343 : 0)); 344 345 if (resid == 0 && sc->sc_dmasize == 65536 && 346 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 347 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 348 resid = 65536; 349 } 350 351 trans = sc->sc_dmasize - resid; 352 if (trans < 0) { /* transferred < 0 ? */ 353 #if 0 354 /* 355 * This situation can happen in perfectly normal operation 356 * if the ESP is reselected while using DMA to select 357 * another target. As such, don't print the warning. 358 */ 359 printf("%s: xfer (%d) > req (%d)\n", 360 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 361 #endif 362 trans = sc->sc_dmasize; 363 } 364 365 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 366 NCR_READ_REG(nsc, NCR_TCL), 367 NCR_READ_REG(nsc, NCR_TCM), 368 (nsc->sc_cfg2 & NCRCFG2_FE) 369 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 370 trans, resid)); 371 372 #ifdef SUN3X_470_EVENTUALLY 373 if (csr & D_WRITE) 374 cache_flush(*sc->sc_dmaaddr, trans); 375 #endif 376 377 if (sc->sc_dvmakaddr) 378 dvma_mapout(sc->sc_dvmakaddr, sc->sc_dmasize); 379 380 *sc->sc_dmalen -= trans; 381 *sc->sc_dmaaddr += trans; 382 383 #if 0 /* this is not normal operation just yet */ 384 if (*sc->sc_dmalen == 0 || 385 nsc->sc_phase != nsc->sc_prevphase) 386 return 0; 387 388 /* and again */ 389 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 390 return 1; 391 #endif 392 return 0; 393 } 394