1 /* $NetBSD: zs.c,v 1.16 2007/12/04 15:12:07 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.16 2007/12/04 15:12:07 tsutsui Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/conf.h> 56 #include <sys/device.h> 57 #include <sys/file.h> 58 #include <sys/ioctl.h> 59 #include <sys/kernel.h> 60 #include <sys/proc.h> 61 #include <sys/tty.h> 62 #include <sys/time.h> 63 #include <sys/syslog.h> 64 #include <sys/intr.h> 65 66 #include <machine/autoconf.h> 67 #include <machine/promlib.h> 68 #include <machine/cpu.h> 69 #include <machine/eeprom.h> 70 #include <machine/psl.h> 71 #include <machine/z8530var.h> 72 73 #include <dev/cons.h> 74 #include <dev/ic/z8530reg.h> 75 #include <dev/sun/kbd_ms_ttyvar.h> 76 #include <ddb/db_output.h> 77 78 #include <sun2/dev/cons.h> 79 80 #include "kbd.h" /* NKBD */ 81 #include "ms.h" /* NMS */ 82 83 /* 84 * Some warts needed by z8530tty.c - 85 * The default parity REALLY needs to be the same as the PROM uses, 86 * or you can not see messages done with printf during boot-up... 87 */ 88 int zs_def_cflag = (CREAD | CS8 | HUPCL); 89 90 /* ZS channel used as the console device (if any) */ 91 void *zs_conschan_get, *zs_conschan_put; 92 93 static u_char zs_init_reg[16] = { 94 0, /* 0: CMD (reset, etc.) */ 95 0, /* 1: No interrupts yet. */ 96 #ifdef ZS_INIT_IVECT 97 ZS_INIT_IVECT, /* 2: IVECT */ 98 #else 99 0, /* 2: IVECT */ 100 #endif 101 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 102 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 103 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 104 0, /* 6: TXSYNC/SYNCLO */ 105 0, /* 7: RXSYNC/SYNCHI */ 106 0, /* 8: alias for data port */ 107 #ifdef ZS_INIT_IVECT 108 ZSWR9_MASTER_IE, 109 #else 110 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 111 #endif 112 0, /*10: Misc. TX/RX control bits */ 113 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 114 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 115 0, /*13: BAUDHI (default=9600) */ 116 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 117 ZSWR15_BREAK_IE, 118 }; 119 120 /* Console ops */ 121 static int zscngetc(dev_t); 122 static void zscnputc(dev_t, int); 123 static void zscnpollc(dev_t, int); 124 125 struct consdev zs_consdev = { 126 NULL, 127 NULL, 128 zscngetc, 129 zscnputc, 130 zscnpollc, 131 NULL, 132 }; 133 134 135 /**************************************************************** 136 * Autoconfig 137 ****************************************************************/ 138 139 static int zs_print(void *, const char *name); 140 141 extern struct cfdriver zs_cd; 142 143 /* Interrupt handlers. */ 144 int zscheckintr(void *); 145 static int zshard(void *); 146 static void zssoft(void *); 147 148 static int zs_get_speed(struct zs_chanstate *); 149 150 /* 151 * Attach a found zs. 152 * 153 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 154 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 155 */ 156 void 157 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 158 { 159 struct zsc_attach_args zsc_args; 160 struct zs_chanstate *cs; 161 int s, channel; 162 163 if (zsd == NULL) { 164 printf("configuration incomplete\n"); 165 return; 166 } 167 168 #if 0 169 /* we should use ipl2si(softpri) but it isn't exported */ 170 printf(" softpri %d\n", _IPL_SOFT_LEVEL3); 171 #else 172 printf("\n"); 173 #endif 174 175 /* 176 * Initialize software state for each channel. 177 */ 178 for (channel = 0; channel < 2; channel++) { 179 struct zschan *zc; 180 struct device *child; 181 182 zsc_args.channel = channel; 183 cs = &zsc->zsc_cs_store[channel]; 184 zsc->zsc_cs[channel] = cs; 185 186 zs_lock_init(cs); 187 cs->cs_channel = channel; 188 cs->cs_private = NULL; 189 cs->cs_ops = &zsops_null; 190 cs->cs_brg_clk = PCLK / 16; 191 192 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 193 194 zsc_args.consdev = NULL; 195 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 196 zsc->zsc_node, 197 channel); 198 199 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 200 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 201 zsc_args.consdev = &zs_consdev; 202 } 203 204 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 205 zs_conschan_get = zc; 206 } 207 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 208 zs_conschan_put = zc; 209 } 210 211 /* Children need to set cn_dev, etc */ 212 cs->cs_reg_csr = &zc->zc_csr; 213 cs->cs_reg_data = &zc->zc_data; 214 215 memcpy(cs->cs_creg, zs_init_reg, 16); 216 memcpy(cs->cs_preg, zs_init_reg, 16); 217 218 /* XXX: Consult PROM properties for this?! */ 219 cs->cs_defspeed = zs_get_speed(cs); 220 cs->cs_defcflag = zs_def_cflag; 221 222 /* Make these correspond to cs_defcflag (-crtscts) */ 223 cs->cs_rr0_dcd = ZSRR0_DCD; 224 cs->cs_rr0_cts = 0; 225 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 226 cs->cs_wr5_rts = 0; 227 228 /* 229 * Clear the master interrupt enable. 230 * The INTENA is common to both channels, 231 * so just do it on the A channel. 232 */ 233 if (channel == 0) { 234 zs_write_reg(cs, 9, 0); 235 } 236 237 /* 238 * Look for a child driver for this channel. 239 * The child attach will setup the hardware. 240 */ 241 if (!(child = 242 config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) { 243 /* No sub-driver. Just reset it. */ 244 u_char reset = (channel == 0) ? 245 ZSWR9_A_RESET : ZSWR9_B_RESET; 246 s = splzs(); 247 zs_write_reg(cs, 9, reset); 248 splx(s); 249 } 250 #if (NKBD > 0) || (NMS > 0) 251 /* 252 * If this was a zstty it has a keyboard 253 * property on it we need to attach the 254 * sunkbd and sunms line disciplines. 255 */ 256 if (child 257 && device_is_a(child, "zstty")) { 258 struct kbd_ms_tty_attach_args kma; 259 struct zstty_softc { 260 /* The following are the only fields we need here */ 261 struct device zst_dev; 262 struct tty *zst_tty; 263 struct zs_chanstate *zst_cs; 264 } *zst = (struct zstty_softc *)child; 265 struct tty *tp; 266 267 kma.kmta_tp = tp = zst->zst_tty; 268 if (tp != NULL) { 269 kma.kmta_dev = tp->t_dev; 270 kma.kmta_consdev = zsc_args.consdev; 271 272 /* Attach 'em if we got 'em. */ 273 switch(zs_peripheral_type(zsc->zsc_promunit, 274 zsc->zsc_node, 275 channel)) { 276 case ZS_PERIPHERAL_SUNKBD: 277 #if (NKBD > 0) 278 kma.kmta_name = "keyboard"; 279 config_found(child, (void *)&kma, NULL); 280 #endif 281 break; 282 case ZS_PERIPHERAL_SUNMS: 283 #if (NMS > 0) 284 kma.kmta_name = "mouse"; 285 config_found(child, (void *)&kma, NULL); 286 #endif 287 break; 288 default: 289 break; 290 } 291 } 292 } 293 #endif 294 } 295 296 /* 297 * Now safe to install interrupt handlers. 298 */ 299 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 300 if (!(zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL, 301 zssoft, zsc))) 302 panic("zsattach: could not establish soft interrupt"); 303 304 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 305 zsc->zsc_dev.dv_xname, "intr"); 306 307 308 /* 309 * Set the master interrupt enable and interrupt vector. 310 * (common to both channels, do it on A) 311 */ 312 cs = zsc->zsc_cs[0]; 313 s = splhigh(); 314 /* interrupt vector */ 315 zs_write_reg(cs, 2, zs_init_reg[2]); 316 /* master interrupt control (enable) */ 317 zs_write_reg(cs, 9, zs_init_reg[9]); 318 splx(s); 319 320 } 321 322 static int 323 zs_print(void *aux, const char *name) 324 { 325 struct zsc_attach_args *args = aux; 326 327 if (name != NULL) 328 aprint_normal("%s: ", name); 329 330 if (args->channel != -1) 331 aprint_normal(" channel %d", args->channel); 332 333 return (UNCONF); 334 } 335 336 static int 337 zshard(void *arg) 338 { 339 struct zsc_softc *zsc = (struct zsc_softc *)arg; 340 int rr3, rval; 341 342 rval = 0; 343 while ((rr3 = zsc_intr_hard(zsc))) { 344 /* Count up the interrupts. */ 345 rval |= rr3; 346 zsc->zsc_intrcnt.ev_count++; 347 } 348 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 349 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 350 zsc->zsc_softintr) { 351 softint_schedule(zsc->zsc_softintr); 352 } 353 return (rval); 354 } 355 356 int 357 zscheckintr(void *arg) 358 { 359 struct zsc_softc *zsc; 360 int unit, rval; 361 362 rval = 0; 363 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 364 365 zsc = zs_cd.cd_devs[unit]; 366 if (zsc == NULL) 367 continue; 368 rval = (zshard((void *)zsc) || rval); 369 } 370 return (rval); 371 } 372 373 374 /* 375 * We need this only for TTY_DEBUG purposes. 376 */ 377 static void 378 zssoft(void *arg) 379 { 380 struct zsc_softc *zsc = (struct zsc_softc *)arg; 381 int s; 382 383 /* Make sure we call the tty layer at spltty. */ 384 s = spltty(); 385 (void)zsc_intr_soft(zsc); 386 #ifdef TTY_DEBUG 387 { 388 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 389 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 390 if (zst0->zst_overflows || zst1->zst_overflows ) { 391 struct trapframe *frame = (struct trapframe *)arg; 392 393 printf("zs silo overflow from %p\n", 394 (long)frame->tf_pc); 395 } 396 } 397 #endif 398 splx(s); 399 } 400 401 402 /* 403 * Compute the current baud rate given a ZS channel. 404 */ 405 static int 406 zs_get_speed(struct zs_chanstate *cs) 407 { 408 int tconst; 409 410 tconst = zs_read_reg(cs, 12); 411 tconst |= zs_read_reg(cs, 13) << 8; 412 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 413 } 414 415 /* 416 * MD functions for setting the baud rate and control modes. 417 */ 418 int 419 zs_set_speed(struct zs_chanstate *cs, int bps) 420 { 421 int tconst, real_bps; 422 423 if (bps == 0) 424 return (0); 425 426 #ifdef DIAGNOSTIC 427 if (cs->cs_brg_clk == 0) 428 panic("zs_set_speed"); 429 #endif 430 431 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 432 if (tconst < 0) 433 return (EINVAL); 434 435 /* Convert back to make sure we can do it. */ 436 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 437 438 /* XXX - Allow some tolerance here? */ 439 if (real_bps != bps) 440 return (EINVAL); 441 442 cs->cs_preg[12] = tconst; 443 cs->cs_preg[13] = tconst >> 8; 444 445 /* Caller will stuff the pending registers. */ 446 return (0); 447 } 448 449 int 450 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */) 451 { 452 int s; 453 454 /* 455 * Output hardware flow control on the chip is horrendous: 456 * if carrier detect drops, the receiver is disabled, and if 457 * CTS drops, the transmitter is stoped IN MID CHARACTER! 458 * Therefore, NEVER set the HFC bit, and instead use the 459 * status interrupt to detect CTS changes. 460 */ 461 s = splzs(); 462 cs->cs_rr0_pps = 0; 463 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 464 cs->cs_rr0_dcd = 0; 465 if ((cflag & MDMBUF) == 0) 466 cs->cs_rr0_pps = ZSRR0_DCD; 467 } else 468 cs->cs_rr0_dcd = ZSRR0_DCD; 469 if ((cflag & CRTSCTS) != 0) { 470 cs->cs_wr5_dtr = ZSWR5_DTR; 471 cs->cs_wr5_rts = ZSWR5_RTS; 472 cs->cs_rr0_cts = ZSRR0_CTS; 473 } else if ((cflag & CDTRCTS) != 0) { 474 cs->cs_wr5_dtr = 0; 475 cs->cs_wr5_rts = ZSWR5_DTR; 476 cs->cs_rr0_cts = ZSRR0_CTS; 477 } else if ((cflag & MDMBUF) != 0) { 478 cs->cs_wr5_dtr = 0; 479 cs->cs_wr5_rts = ZSWR5_DTR; 480 cs->cs_rr0_cts = ZSRR0_DCD; 481 } else { 482 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 483 cs->cs_wr5_rts = 0; 484 cs->cs_rr0_cts = 0; 485 } 486 splx(s); 487 488 /* Caller will stuff the pending registers. */ 489 return (0); 490 } 491 492 493 /* 494 * Read or write the chip with suitable delays. 495 */ 496 497 u_char 498 zs_read_reg(struct zs_chanstate *cs, u_char reg) 499 { 500 u_char val; 501 502 *cs->cs_reg_csr = reg; 503 ZS_DELAY(); 504 val = *cs->cs_reg_csr; 505 ZS_DELAY(); 506 return (val); 507 } 508 509 void 510 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 511 { 512 *cs->cs_reg_csr = reg; 513 ZS_DELAY(); 514 *cs->cs_reg_csr = val; 515 ZS_DELAY(); 516 } 517 518 u_char 519 zs_read_csr(struct zs_chanstate *cs) 520 { 521 u_char val; 522 523 val = *cs->cs_reg_csr; 524 ZS_DELAY(); 525 return (val); 526 } 527 528 void 529 zs_write_csr(struct zs_chanstate *cs, u_char val) 530 { 531 *cs->cs_reg_csr = val; 532 ZS_DELAY(); 533 } 534 535 u_char 536 zs_read_data(struct zs_chanstate *cs) 537 { 538 u_char val; 539 540 val = *cs->cs_reg_data; 541 ZS_DELAY(); 542 return (val); 543 } 544 545 void 546 zs_write_data(struct zs_chanstate *cs, u_char val) 547 { 548 *cs->cs_reg_data = val; 549 ZS_DELAY(); 550 } 551 552 /**************************************************************** 553 * Console support functions (Sun specific!) 554 * Note: this code is allowed to know about the layout of 555 * the chip registers, and uses that to keep things simple. 556 * XXX - I think I like the mvme167 code better. -gwr 557 ****************************************************************/ 558 559 extern void Debugger(void); 560 561 /* 562 * Handle user request to enter kernel debugger. 563 */ 564 void 565 zs_abort(struct zs_chanstate *cs) 566 { 567 volatile struct zschan *zc = zs_conschan_get; 568 int rr0; 569 570 /* Wait for end of break to avoid PROM abort. */ 571 /* XXX - Limit the wait? */ 572 do { 573 rr0 = zc->zc_csr; 574 ZS_DELAY(); 575 } while (rr0 & ZSRR0_BREAK); 576 577 #if defined(KGDB) 578 zskgdb(cs); 579 #elif defined(DDB) 580 { 581 extern int db_active; 582 583 if (!db_active) 584 Debugger(); 585 else 586 /* Debugger is probably hozed */ 587 callrom(); 588 } 589 #else 590 printf("stopping on keyboard abort\n"); 591 callrom(); 592 #endif 593 } 594 595 596 /* 597 * Polled input char. 598 */ 599 int 600 zs_getc(void *arg) 601 { 602 volatile struct zschan *zc = arg; 603 int s, c, rr0; 604 605 s = splhigh(); 606 /* Wait for a character to arrive. */ 607 do { 608 rr0 = zc->zc_csr; 609 ZS_DELAY(); 610 } while ((rr0 & ZSRR0_RX_READY) == 0); 611 612 c = zc->zc_data; 613 ZS_DELAY(); 614 splx(s); 615 616 /* 617 * This is used by the kd driver to read scan codes, 618 * so don't translate '\r' ==> '\n' here... 619 */ 620 return (c); 621 } 622 623 /* 624 * Polled output char. 625 */ 626 void 627 zs_putc(void *arg, int c) 628 { 629 volatile struct zschan *zc = arg; 630 int s, rr0; 631 632 s = splhigh(); 633 634 /* Wait for transmitter to become ready. */ 635 do { 636 rr0 = zc->zc_csr; 637 ZS_DELAY(); 638 } while ((rr0 & ZSRR0_TX_READY) == 0); 639 640 /* 641 * Send the next character. 642 * Now you'd think that this could be followed by a ZS_DELAY() 643 * just like all the other chip accesses, but it turns out that 644 * the `transmit-ready' interrupt isn't de-asserted until 645 * some period of time after the register write completes 646 * (more than a couple instructions). So to avoid stray 647 * interrupts we put in the 2us delay regardless of CPU model. 648 */ 649 zc->zc_data = c; 650 delay(2); 651 652 splx(s); 653 } 654 655 /*****************************************************************/ 656 657 658 659 660 /* 661 * Polled console input putchar. 662 */ 663 static int 664 zscngetc(dev_t dev) 665 { 666 return (zs_getc(zs_conschan_get)); 667 } 668 669 /* 670 * Polled console output putchar. 671 */ 672 static void 673 zscnputc(dev_t dev, int c) 674 { 675 zs_putc(zs_conschan_put, c); 676 } 677 678 int swallow_zsintrs; 679 680 static void 681 zscnpollc(dev_t dev, int on) 682 { 683 /* 684 * Need to tell zs driver to acknowledge all interrupts or we get 685 * annoying spurious interrupt messages. This is because mucking 686 * with spl() levels during polling does not prevent interrupts from 687 * being generated. 688 */ 689 690 if (on) swallow_zsintrs++; 691 else swallow_zsintrs--; 692 } 693 694