1 /* $NetBSD: zs.c,v 1.17 2008/03/29 19:15:35 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.17 2008/03/29 19:15:35 tsutsui Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/conf.h> 56 #include <sys/device.h> 57 #include <sys/file.h> 58 #include <sys/ioctl.h> 59 #include <sys/kernel.h> 60 #include <sys/proc.h> 61 #include <sys/tty.h> 62 #include <sys/time.h> 63 #include <sys/syslog.h> 64 #include <sys/intr.h> 65 66 #include <machine/autoconf.h> 67 #include <machine/promlib.h> 68 #include <machine/cpu.h> 69 #include <machine/eeprom.h> 70 #include <machine/psl.h> 71 #include <machine/z8530var.h> 72 73 #include <dev/cons.h> 74 #include <dev/ic/z8530reg.h> 75 #include <dev/sun/kbd_ms_ttyvar.h> 76 #include <ddb/db_output.h> 77 78 #include <sun2/dev/cons.h> 79 80 #include "ioconf.h" 81 #include "kbd.h" /* NKBD */ 82 #include "ms.h" /* NMS */ 83 84 /* 85 * Some warts needed by z8530tty.c - 86 * The default parity REALLY needs to be the same as the PROM uses, 87 * or you can not see messages done with printf during boot-up... 88 */ 89 int zs_def_cflag = (CREAD | CS8 | HUPCL); 90 91 /* ZS channel used as the console device (if any) */ 92 void *zs_conschan_get, *zs_conschan_put; 93 94 static uint8_t zs_init_reg[16] = { 95 0, /* 0: CMD (reset, etc.) */ 96 0, /* 1: No interrupts yet. */ 97 #ifdef ZS_INIT_IVECT 98 ZS_INIT_IVECT, /* 2: IVECT */ 99 #else 100 0, /* 2: IVECT */ 101 #endif 102 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 103 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 104 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 105 0, /* 6: TXSYNC/SYNCLO */ 106 0, /* 7: RXSYNC/SYNCHI */ 107 0, /* 8: alias for data port */ 108 #ifdef ZS_INIT_IVECT 109 ZSWR9_MASTER_IE, 110 #else 111 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 112 #endif 113 0, /*10: Misc. TX/RX control bits */ 114 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 116 0, /*13: BAUDHI (default=9600) */ 117 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 118 ZSWR15_BREAK_IE, 119 }; 120 121 /* Console ops */ 122 static int zscngetc(dev_t); 123 static void zscnputc(dev_t, int); 124 static void zscnpollc(dev_t, int); 125 126 struct consdev zs_consdev = { 127 NULL, 128 NULL, 129 zscngetc, 130 zscnputc, 131 zscnpollc, 132 NULL, 133 }; 134 135 136 /**************************************************************** 137 * Autoconfig 138 ****************************************************************/ 139 140 static int zs_print(void *, const char *name); 141 142 /* Interrupt handlers. */ 143 int zscheckintr(void *); 144 static int zshard(void *); 145 static void zssoft(void *); 146 147 static int zs_get_speed(struct zs_chanstate *); 148 149 /* 150 * Attach a found zs. 151 * 152 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 153 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 154 */ 155 void 156 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 157 { 158 struct zsc_attach_args zsc_args; 159 struct zs_chanstate *cs; 160 int s, channel; 161 162 if (zsd == NULL) { 163 aprint_error(": configuration incomplete\n"); 164 return; 165 } 166 167 #if 0 168 /* we should use ipl2si(softpri) but it isn't exported */ 169 aprint_normal(" softpri %d\n", _IPL_SOFT_LEVEL3); 170 #else 171 aprint_normal("\n"); 172 #endif 173 174 /* 175 * Initialize software state for each channel. 176 */ 177 for (channel = 0; channel < 2; channel++) { 178 struct zschan *zc; 179 struct device *child; 180 181 zsc_args.channel = channel; 182 cs = &zsc->zsc_cs_store[channel]; 183 zsc->zsc_cs[channel] = cs; 184 185 zs_lock_init(cs); 186 cs->cs_channel = channel; 187 cs->cs_private = NULL; 188 cs->cs_ops = &zsops_null; 189 cs->cs_brg_clk = PCLK / 16; 190 191 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 192 193 zsc_args.consdev = NULL; 194 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 195 zsc->zsc_node, 196 channel); 197 198 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 199 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 200 zsc_args.consdev = &zs_consdev; 201 } 202 203 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 204 zs_conschan_get = zc; 205 } 206 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 207 zs_conschan_put = zc; 208 } 209 210 /* Children need to set cn_dev, etc */ 211 cs->cs_reg_csr = &zc->zc_csr; 212 cs->cs_reg_data = &zc->zc_data; 213 214 memcpy(cs->cs_creg, zs_init_reg, 16); 215 memcpy(cs->cs_preg, zs_init_reg, 16); 216 217 /* XXX: Consult PROM properties for this?! */ 218 cs->cs_defspeed = zs_get_speed(cs); 219 cs->cs_defcflag = zs_def_cflag; 220 221 /* Make these correspond to cs_defcflag (-crtscts) */ 222 cs->cs_rr0_dcd = ZSRR0_DCD; 223 cs->cs_rr0_cts = 0; 224 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 225 cs->cs_wr5_rts = 0; 226 227 /* 228 * Clear the master interrupt enable. 229 * The INTENA is common to both channels, 230 * so just do it on the A channel. 231 */ 232 if (channel == 0) { 233 zs_write_reg(cs, 9, 0); 234 } 235 236 /* 237 * Look for a child driver for this channel. 238 * The child attach will setup the hardware. 239 */ 240 if ((child = config_found(zsc->zsc_dev, (void *)&zsc_args, 241 zs_print)) == NULL) { 242 /* No sub-driver. Just reset it. */ 243 uint8_t reset = (channel == 0) ? 244 ZSWR9_A_RESET : ZSWR9_B_RESET; 245 s = splzs(); 246 zs_write_reg(cs, 9, reset); 247 splx(s); 248 } 249 #if (NKBD > 0) || (NMS > 0) 250 /* 251 * If this was a zstty it has a keyboard 252 * property on it we need to attach the 253 * sunkbd and sunms line disciplines. 254 */ 255 if (child 256 && device_is_a(child, "zstty")) { 257 struct kbd_ms_tty_attach_args kma; 258 struct zstty_softc { 259 /* 260 * The following are the only fields 261 * we need here 262 */ 263 device_t zst_dev; 264 struct tty *zst_tty; 265 struct zs_chanstate *zst_cs; 266 } *zst = device_private(child); 267 struct tty *tp; 268 269 kma.kmta_tp = tp = zst->zst_tty; 270 if (tp != NULL) { 271 kma.kmta_dev = tp->t_dev; 272 kma.kmta_consdev = zsc_args.consdev; 273 274 /* Attach 'em if we got 'em. */ 275 switch(zs_peripheral_type(zsc->zsc_promunit, 276 zsc->zsc_node, 277 channel)) { 278 case ZS_PERIPHERAL_SUNKBD: 279 #if (NKBD > 0) 280 kma.kmta_name = "keyboard"; 281 config_found(child, (void *)&kma, NULL); 282 #endif 283 break; 284 case ZS_PERIPHERAL_SUNMS: 285 #if (NMS > 0) 286 kma.kmta_name = "mouse"; 287 config_found(child, (void *)&kma, NULL); 288 #endif 289 break; 290 default: 291 break; 292 } 293 } 294 } 295 #endif 296 } 297 298 /* 299 * Now safe to install interrupt handlers. 300 */ 301 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 302 if ((zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL, 303 zssoft, zsc)) == NULL) 304 panic("%s: could not establish soft interrupt", __func__); 305 306 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 307 device_xname(zsc->zsc_dev), "intr"); 308 309 310 /* 311 * Set the master interrupt enable and interrupt vector. 312 * (common to both channels, do it on A) 313 */ 314 cs = zsc->zsc_cs[0]; 315 s = splhigh(); 316 /* interrupt vector */ 317 zs_write_reg(cs, 2, zs_init_reg[2]); 318 /* master interrupt control (enable) */ 319 zs_write_reg(cs, 9, zs_init_reg[9]); 320 splx(s); 321 322 } 323 324 static int 325 zs_print(void *aux, const char *name) 326 { 327 struct zsc_attach_args *args = aux; 328 329 if (name != NULL) 330 aprint_normal("%s: ", name); 331 332 if (args->channel != -1) 333 aprint_normal(" channel %d", args->channel); 334 335 return (UNCONF); 336 } 337 338 static int 339 zshard(void *arg) 340 { 341 struct zsc_softc *zsc = arg; 342 int rval; 343 uint8_t rr3; 344 345 rval = 0; 346 while ((rr3 = zsc_intr_hard(zsc))) { 347 /* Count up the interrupts. */ 348 rval |= rr3; 349 zsc->zsc_intrcnt.ev_count++; 350 } 351 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 352 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 353 zsc->zsc_softintr) { 354 softint_schedule(zsc->zsc_softintr); 355 } 356 return (rval); 357 } 358 359 int 360 zscheckintr(void *arg) 361 { 362 struct zsc_softc *zsc; 363 int unit, rval; 364 365 rval = 0; 366 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 367 368 zsc = device_private(zs_cd.cd_devs[unit]); 369 if (zsc == NULL) 370 continue; 371 rval = (zshard((void *)zsc) || rval); 372 } 373 return (rval); 374 } 375 376 377 /* 378 * We need this only for TTY_DEBUG purposes. 379 */ 380 static void 381 zssoft(void *arg) 382 { 383 struct zsc_softc *zsc = arg; 384 int s; 385 386 /* Make sure we call the tty layer at spltty. */ 387 s = spltty(); 388 (void)zsc_intr_soft(zsc); 389 #ifdef TTY_DEBUG 390 { 391 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 392 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 393 if (zst0->zst_overflows || zst1->zst_overflows ) { 394 struct trapframe *frame = arg; /* XXX */ 395 396 printf("zs silo overflow from %p\n", 397 (long)frame->tf_pc); 398 } 399 } 400 #endif 401 splx(s); 402 } 403 404 405 /* 406 * Compute the current baud rate given a ZS channel. 407 */ 408 static int 409 zs_get_speed(struct zs_chanstate *cs) 410 { 411 int tconst; 412 413 tconst = zs_read_reg(cs, 12); 414 tconst |= zs_read_reg(cs, 13) << 8; 415 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 416 } 417 418 /* 419 * MD functions for setting the baud rate and control modes. 420 */ 421 int 422 zs_set_speed(struct zs_chanstate *cs, int bps) 423 { 424 int tconst, real_bps; 425 426 if (bps == 0) 427 return (0); 428 429 #ifdef DIAGNOSTIC 430 if (cs->cs_brg_clk == 0) 431 panic("zs_set_speed"); 432 #endif 433 434 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 435 if (tconst < 0) 436 return (EINVAL); 437 438 /* Convert back to make sure we can do it. */ 439 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 440 441 /* XXX - Allow some tolerance here? */ 442 if (real_bps != bps) 443 return (EINVAL); 444 445 cs->cs_preg[12] = tconst; 446 cs->cs_preg[13] = tconst >> 8; 447 448 /* Caller will stuff the pending registers. */ 449 return (0); 450 } 451 452 int 453 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */) 454 { 455 int s; 456 457 /* 458 * Output hardware flow control on the chip is horrendous: 459 * if carrier detect drops, the receiver is disabled, and if 460 * CTS drops, the transmitter is stoped IN MID CHARACTER! 461 * Therefore, NEVER set the HFC bit, and instead use the 462 * status interrupt to detect CTS changes. 463 */ 464 s = splzs(); 465 cs->cs_rr0_pps = 0; 466 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 467 cs->cs_rr0_dcd = 0; 468 if ((cflag & MDMBUF) == 0) 469 cs->cs_rr0_pps = ZSRR0_DCD; 470 } else 471 cs->cs_rr0_dcd = ZSRR0_DCD; 472 if ((cflag & CRTSCTS) != 0) { 473 cs->cs_wr5_dtr = ZSWR5_DTR; 474 cs->cs_wr5_rts = ZSWR5_RTS; 475 cs->cs_rr0_cts = ZSRR0_CTS; 476 } else if ((cflag & CDTRCTS) != 0) { 477 cs->cs_wr5_dtr = 0; 478 cs->cs_wr5_rts = ZSWR5_DTR; 479 cs->cs_rr0_cts = ZSRR0_CTS; 480 } else if ((cflag & MDMBUF) != 0) { 481 cs->cs_wr5_dtr = 0; 482 cs->cs_wr5_rts = ZSWR5_DTR; 483 cs->cs_rr0_cts = ZSRR0_DCD; 484 } else { 485 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 486 cs->cs_wr5_rts = 0; 487 cs->cs_rr0_cts = 0; 488 } 489 splx(s); 490 491 /* Caller will stuff the pending registers. */ 492 return (0); 493 } 494 495 496 /* 497 * Read or write the chip with suitable delays. 498 */ 499 500 uint8_t 501 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 502 { 503 uint8_t val; 504 505 *cs->cs_reg_csr = reg; 506 ZS_DELAY(); 507 val = *cs->cs_reg_csr; 508 ZS_DELAY(); 509 return (val); 510 } 511 512 void 513 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 514 { 515 *cs->cs_reg_csr = reg; 516 ZS_DELAY(); 517 *cs->cs_reg_csr = val; 518 ZS_DELAY(); 519 } 520 521 uint8_t 522 zs_read_csr(struct zs_chanstate *cs) 523 { 524 uint8_t val; 525 526 val = *cs->cs_reg_csr; 527 ZS_DELAY(); 528 return (val); 529 } 530 531 void 532 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 533 { 534 *cs->cs_reg_csr = val; 535 ZS_DELAY(); 536 } 537 538 uint8_t 539 zs_read_data(struct zs_chanstate *cs) 540 { 541 uint8_t val; 542 543 val = *cs->cs_reg_data; 544 ZS_DELAY(); 545 return (val); 546 } 547 548 void 549 zs_write_data(struct zs_chanstate *cs, uint8_t val) 550 { 551 *cs->cs_reg_data = val; 552 ZS_DELAY(); 553 } 554 555 /**************************************************************** 556 * Console support functions (Sun specific!) 557 * Note: this code is allowed to know about the layout of 558 * the chip registers, and uses that to keep things simple. 559 * XXX - I think I like the mvme167 code better. -gwr 560 ****************************************************************/ 561 562 extern void Debugger(void); 563 564 /* 565 * Handle user request to enter kernel debugger. 566 */ 567 void 568 zs_abort(struct zs_chanstate *cs) 569 { 570 volatile struct zschan *zc = zs_conschan_get; 571 int rr0; 572 573 /* Wait for end of break to avoid PROM abort. */ 574 /* XXX - Limit the wait? */ 575 do { 576 rr0 = zc->zc_csr; 577 ZS_DELAY(); 578 } while (rr0 & ZSRR0_BREAK); 579 580 #if defined(KGDB) 581 zskgdb(cs); 582 #elif defined(DDB) 583 { 584 extern int db_active; 585 586 if (!db_active) 587 Debugger(); 588 else 589 /* Debugger is probably hozed */ 590 callrom(); 591 } 592 #else 593 printf("stopping on keyboard abort\n"); 594 callrom(); 595 #endif 596 } 597 598 599 /* 600 * Polled input char. 601 */ 602 int 603 zs_getc(void *arg) 604 { 605 volatile struct zschan *zc = arg; 606 int s, c, rr0; 607 608 s = splhigh(); 609 /* Wait for a character to arrive. */ 610 do { 611 rr0 = zc->zc_csr; 612 ZS_DELAY(); 613 } while ((rr0 & ZSRR0_RX_READY) == 0); 614 615 c = zc->zc_data; 616 ZS_DELAY(); 617 splx(s); 618 619 /* 620 * This is used by the kd driver to read scan codes, 621 * so don't translate '\r' ==> '\n' here... 622 */ 623 return (c); 624 } 625 626 /* 627 * Polled output char. 628 */ 629 void 630 zs_putc(void *arg, int c) 631 { 632 volatile struct zschan *zc = arg; 633 int s, rr0; 634 635 s = splhigh(); 636 637 /* Wait for transmitter to become ready. */ 638 do { 639 rr0 = zc->zc_csr; 640 ZS_DELAY(); 641 } while ((rr0 & ZSRR0_TX_READY) == 0); 642 643 /* 644 * Send the next character. 645 * Now you'd think that this could be followed by a ZS_DELAY() 646 * just like all the other chip accesses, but it turns out that 647 * the `transmit-ready' interrupt isn't de-asserted until 648 * some period of time after the register write completes 649 * (more than a couple instructions). So to avoid stray 650 * interrupts we put in the 2us delay regardless of CPU model. 651 */ 652 zc->zc_data = c; 653 delay(2); 654 655 splx(s); 656 } 657 658 /*****************************************************************/ 659 660 661 662 663 /* 664 * Polled console input putchar. 665 */ 666 static int 667 zscngetc(dev_t dev) 668 { 669 return (zs_getc(zs_conschan_get)); 670 } 671 672 /* 673 * Polled console output putchar. 674 */ 675 static void 676 zscnputc(dev_t dev, int c) 677 { 678 zs_putc(zs_conschan_put, c); 679 } 680 681 int swallow_zsintrs; 682 683 static void 684 zscnpollc(dev_t dev, int on) 685 { 686 /* 687 * Need to tell zs driver to acknowledge all interrupts or we get 688 * annoying spurious interrupt messages. This is because mucking 689 * with spl() levels during polling does not prevent interrupts from 690 * being generated. 691 */ 692 693 if (on) swallow_zsintrs++; 694 else swallow_zsintrs--; 695 } 696 697