xref: /netbsd-src/sys/arch/sun2/dev/zs.c (revision 181254a7b1bdde6873432bffef2d2decc4b5c22f) 
1 /*	$NetBSD: zs.c,v 1.21 2012/10/13 06:28:54 tsutsui Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Zilog Z8530 Dual UART driver (machine-dependent part)
34  *
35  * Runs two serial lines per chip using slave drivers.
36  * Plain tty/async lines use the zs_async slave.
37  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
38  */
39 
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.21 2012/10/13 06:28:54 tsutsui Exp $");
42 
43 #include "opt_ddb.h"
44 #include "opt_kgdb.h"
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/conf.h>
49 #include <sys/device.h>
50 #include <sys/file.h>
51 #include <sys/ioctl.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h>
54 #include <sys/tty.h>
55 #include <sys/time.h>
56 #include <sys/syslog.h>
57 #include <sys/intr.h>
58 
59 #include <machine/autoconf.h>
60 #include <machine/promlib.h>
61 #include <machine/cpu.h>
62 #include <machine/eeprom.h>
63 #include <machine/psl.h>
64 #include <machine/z8530var.h>
65 
66 #include <dev/cons.h>
67 #include <dev/ic/z8530reg.h>
68 #include <dev/sun/kbd_ms_ttyvar.h>
69 #include <ddb/db_output.h>
70 
71 #include <sun2/dev/cons.h>
72 
73 #include "ioconf.h"
74 #include "kbd.h"	/* NKBD */
75 #include "ms.h"		/* NMS */
76 
77 /*
78  * Some warts needed by z8530tty.c -
79  * The default parity REALLY needs to be the same as the PROM uses,
80  * or you can not see messages done with printf during boot-up...
81  */
82 int zs_def_cflag = (CREAD | CS8 | HUPCL);
83 
84 /* ZS channel used as the console device (if any) */
85 void *zs_conschan_get, *zs_conschan_put;
86 
87 static uint8_t zs_init_reg[16] = {
88 	0,	/* 0: CMD (reset, etc.) */
89 	0,	/* 1: No interrupts yet. */
90 #ifdef  ZS_INIT_IVECT
91 	ZS_INIT_IVECT,	/* 2: IVECT */
92 #else
93 	0,	/* 2: IVECT */
94 #endif
95 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
96 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
97 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
98 	0,	/* 6: TXSYNC/SYNCLO */
99 	0,	/* 7: RXSYNC/SYNCHI */
100 	0,	/* 8: alias for data port */
101 #ifdef  ZS_INIT_IVECT
102 	ZSWR9_MASTER_IE,
103 #else
104 	ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
105 #endif
106 	0,	/*10: Misc. TX/RX control bits */
107 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
108 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
109 	0,			/*13: BAUDHI (default=9600) */
110 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
111 	ZSWR15_BREAK_IE,
112 };
113 
114 /* Console ops */
115 static int  zscngetc(dev_t);
116 static void zscnputc(dev_t, int);
117 static void zscnpollc(dev_t, int);
118 
119 struct consdev zs_consdev = {
120 	NULL,
121 	NULL,
122 	zscngetc,
123 	zscnputc,
124 	zscnpollc,
125 	NULL,
126 };
127 
128 
129 /****************************************************************
130  * Autoconfig
131  ****************************************************************/
132 
133 static int  zs_print(void *, const char *name);
134 
135 /* Interrupt handlers. */
136 int zscheckintr(void *);
137 static int zshard(void *);
138 static void zssoft(void *);
139 
140 static int zs_get_speed(struct zs_chanstate *);
141 
142 /*
143  * Attach a found zs.
144  *
145  * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
146  * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
147  */
148 void
149 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri)
150 {
151 	struct zsc_attach_args zsc_args;
152 	struct zs_chanstate *cs;
153 	int channel;
154 
155 	memset(&zsc_args, 0, sizeof zsc_args);
156 	if (zsd == NULL) {
157 		aprint_error(": configuration incomplete\n");
158 		return;
159 	}
160 
161 #if 0
162 	/* we should use ipl2si(softpri) but it isn't exported */
163 	aprint_normal(" softpri %d\n", _IPL_SOFT_LEVEL3);
164 #else
165 	aprint_normal("\n");
166 #endif
167 
168 	/*
169 	 * Initialize software state for each channel.
170 	 */
171 	for (channel = 0; channel < 2; channel++) {
172 		struct zschan *zc;
173 		device_t child;
174 
175 		zsc_args.channel = channel;
176 		zsc_args.hwflags = 0;
177 		cs = &zsc->zsc_cs_store[channel];
178 		zsc->zsc_cs[channel] = cs;
179 
180 		zs_lock_init(cs);
181 		cs->cs_channel = channel;
182 		cs->cs_private = NULL;
183 		cs->cs_ops = &zsops_null;
184 		cs->cs_brg_clk = PCLK / 16;
185 
186 		zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
187 
188 		zsc_args.consdev = NULL;
189 		zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit,
190 						    zsc->zsc_node,
191 						    channel);
192 
193 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
194 			zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV;
195 			zsc_args.consdev = &zs_consdev;
196 		}
197 
198 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
199 			zs_conschan_get = zc;
200 		}
201 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
202 			zs_conschan_put = zc;
203 		}
204 
205 		/* Children need to set cn_dev, etc */
206 		cs->cs_reg_csr  = &zc->zc_csr;
207 		cs->cs_reg_data = &zc->zc_data;
208 
209 		memcpy(cs->cs_creg, zs_init_reg, 16);
210 		memcpy(cs->cs_preg, zs_init_reg, 16);
211 
212 		/* XXX: Consult PROM properties for this?! */
213 		cs->cs_defspeed = zs_get_speed(cs);
214 		cs->cs_defcflag = zs_def_cflag;
215 
216 		/* Make these correspond to cs_defcflag (-crtscts) */
217 		cs->cs_rr0_dcd = ZSRR0_DCD;
218 		cs->cs_rr0_cts = 0;
219 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
220 		cs->cs_wr5_rts = 0;
221 
222 		/*
223 		 * Clear the master interrupt enable.
224 		 * The INTENA is common to both channels,
225 		 * so just do it on the A channel.
226 		 */
227 		if (channel == 0) {
228 			zs_write_reg(cs, 9, 0);
229 		}
230 
231 		/*
232 		 * Look for a child driver for this channel.
233 		 * The child attach will setup the hardware.
234 		 */
235 		if ((child = config_found(zsc->zsc_dev, (void *)&zsc_args,
236 		    zs_print)) == NULL) {
237 			/* No sub-driver.  Just reset it. */
238 			uint8_t reset = (channel == 0) ?
239 				ZSWR9_A_RESET : ZSWR9_B_RESET;
240 			zs_lock_chan(cs);
241 			zs_write_reg(cs,  9, reset);
242 			zs_unlock_chan(cs);
243 		}
244 #if (NKBD > 0) || (NMS > 0)
245 		/*
246 		 * If this was a zstty it has a keyboard
247 		 * property on it we need to attach the
248 		 * sunkbd and sunms line disciplines.
249 		 */
250 		if (child
251 		    && device_is_a(child, "zstty")) {
252 			struct kbd_ms_tty_attach_args kma;
253 			struct zstty_softc {
254 				/*
255 				 * The following are the only fields
256 				 * we need here
257 				 */
258 				device_t zst_dev;
259 				struct  tty *zst_tty;
260 				struct	zs_chanstate *zst_cs;
261 			} *zst = device_private(child);
262 			struct tty *tp;
263 
264 			kma.kmta_tp = tp = zst->zst_tty;
265 			if (tp != NULL) {
266 				kma.kmta_dev = tp->t_dev;
267 				kma.kmta_consdev = zsc_args.consdev;
268 
269 				/* Attach 'em if we got 'em. */
270 				switch(zs_peripheral_type(zsc->zsc_promunit,
271 						 	  zsc->zsc_node,
272 						  	  channel)) {
273 				case ZS_PERIPHERAL_SUNKBD:
274 #if (NKBD > 0)
275 					kma.kmta_name = "keyboard";
276 					config_found(child, (void *)&kma, NULL);
277 #endif
278 					break;
279 				case ZS_PERIPHERAL_SUNMS:
280 #if (NMS > 0)
281 					kma.kmta_name = "mouse";
282 					config_found(child, (void *)&kma, NULL);
283 #endif
284 					break;
285 				default:
286 					break;
287 				}
288 			}
289 		}
290 #endif
291 	}
292 
293 	/*
294 	 * Now safe to install interrupt handlers.
295 	 */
296 	bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc);
297 	if ((zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL,
298 	    zssoft, zsc)) == NULL)
299 		panic("%s: could not establish soft interrupt", __func__);
300 
301 	evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
302 	    device_xname(zsc->zsc_dev), "intr");
303 
304 
305 	/*
306 	 * Set the master interrupt enable and interrupt vector.
307 	 * (common to both channels, do it on A)
308 	 */
309 	cs = zsc->zsc_cs[0];
310 	zs_lock_chan(cs);
311 	/* interrupt vector */
312 	zs_write_reg(cs, 2, zs_init_reg[2]);
313 	/* master interrupt control (enable) */
314 	zs_write_reg(cs, 9, zs_init_reg[9]);
315 	zs_unlock_chan(cs);
316 
317 }
318 
319 static int
320 zs_print(void *aux, const char *name)
321 {
322 	struct zsc_attach_args *args = aux;
323 
324 	if (name != NULL)
325 		aprint_normal("%s: ", name);
326 
327 	if (args->channel != -1)
328 		aprint_normal(" channel %d", args->channel);
329 
330 	return (UNCONF);
331 }
332 
333 static int
334 zshard(void *arg)
335 {
336 	struct zsc_softc *zsc = arg;
337 	int rval;
338 	uint8_t rr3;
339 
340 	rval = 0;
341 	while ((rr3 = zsc_intr_hard(zsc))) {
342 		/* Count up the interrupts. */
343 		rval |= rr3;
344 		zsc->zsc_intrcnt.ev_count++;
345 	}
346 	if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) ||
347 	     (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) &&
348 	    zsc->zsc_softintr) {
349 		softint_schedule(zsc->zsc_softintr);
350 	}
351 	return (rval);
352 }
353 
354 int
355 zscheckintr(void *arg)
356 {
357 	struct zsc_softc *zsc;
358 	int unit, rval;
359 
360 	rval = 0;
361 	for (unit = 0; unit < zs_cd.cd_ndevs; unit++) {
362 
363 		zsc = device_lookup_private(&zs_cd, unit);
364 		if (zsc == NULL)
365 			continue;
366 		rval = (zshard((void *)zsc) || rval);
367 	}
368 	return (rval);
369 }
370 
371 
372 /*
373  * We need this only for TTY_DEBUG purposes.
374  */
375 static void
376 zssoft(void *arg)
377 {
378 	struct zsc_softc *zsc = arg;
379 	int s;
380 
381 	/* Make sure we call the tty layer at spltty. */
382 	s = spltty();
383 	(void)zsc_intr_soft(zsc);
384 #ifdef TTY_DEBUG
385 	{
386 		struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private;
387 		struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private;
388 		if (zst0->zst_overflows || zst1->zst_overflows ) {
389 			struct trapframe *frame = arg;	/* XXX */
390 
391 			printf("zs silo overflow from %p\n",
392 			    (long)frame->tf_pc);
393 		}
394 	}
395 #endif
396 	splx(s);
397 }
398 
399 
400 /*
401  * Compute the current baud rate given a ZS channel.
402  */
403 static int
404 zs_get_speed(struct zs_chanstate *cs)
405 {
406 	int tconst;
407 
408 	tconst = zs_read_reg(cs, 12);
409 	tconst |= zs_read_reg(cs, 13) << 8;
410 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
411 }
412 
413 /*
414  * MD functions for setting the baud rate and control modes.
415  */
416 int
417 zs_set_speed(struct zs_chanstate *cs, int bps)
418 {
419 	int tconst, real_bps;
420 
421 	if (bps == 0)
422 		return (0);
423 
424 #ifdef	DIAGNOSTIC
425 	if (cs->cs_brg_clk == 0)
426 		panic("zs_set_speed");
427 #endif
428 
429 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
430 	if (tconst < 0)
431 		return (EINVAL);
432 
433 	/* Convert back to make sure we can do it. */
434 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
435 
436 	/* XXX - Allow some tolerance here? */
437 	if (real_bps != bps)
438 		return (EINVAL);
439 
440 	cs->cs_preg[12] = tconst;
441 	cs->cs_preg[13] = tconst >> 8;
442 
443 	/* Caller will stuff the pending registers. */
444 	return (0);
445 }
446 
447 int
448 zs_set_modes(struct zs_chanstate *cs, int cflag	/* bits per second */)
449 {
450 
451 	/*
452 	 * Output hardware flow control on the chip is horrendous:
453 	 * if carrier detect drops, the receiver is disabled, and if
454 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
455 	 * Therefore, NEVER set the HFC bit, and instead use the
456 	 * status interrupt to detect CTS changes.
457 	 */
458 	zs_lock_chan(cs);
459 	cs->cs_rr0_pps = 0;
460 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
461 		cs->cs_rr0_dcd = 0;
462 		if ((cflag & MDMBUF) == 0)
463 			cs->cs_rr0_pps = ZSRR0_DCD;
464 	} else
465 		cs->cs_rr0_dcd = ZSRR0_DCD;
466 	if ((cflag & CRTSCTS) != 0) {
467 		cs->cs_wr5_dtr = ZSWR5_DTR;
468 		cs->cs_wr5_rts = ZSWR5_RTS;
469 		cs->cs_rr0_cts = ZSRR0_CTS;
470 	} else if ((cflag & CDTRCTS) != 0) {
471 		cs->cs_wr5_dtr = 0;
472 		cs->cs_wr5_rts = ZSWR5_DTR;
473 		cs->cs_rr0_cts = ZSRR0_CTS;
474 	} else if ((cflag & MDMBUF) != 0) {
475 		cs->cs_wr5_dtr = 0;
476 		cs->cs_wr5_rts = ZSWR5_DTR;
477 		cs->cs_rr0_cts = ZSRR0_DCD;
478 	} else {
479 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
480 		cs->cs_wr5_rts = 0;
481 		cs->cs_rr0_cts = 0;
482 	}
483 	zs_unlock_chan(cs);
484 
485 	/* Caller will stuff the pending registers. */
486 	return (0);
487 }
488 
489 
490 /*
491  * Read or write the chip with suitable delays.
492  */
493 
494 uint8_t
495 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
496 {
497 	uint8_t val;
498 
499 	*cs->cs_reg_csr = reg;
500 	ZS_DELAY();
501 	val = *cs->cs_reg_csr;
502 	ZS_DELAY();
503 	return (val);
504 }
505 
506 void
507 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
508 {
509 	*cs->cs_reg_csr = reg;
510 	ZS_DELAY();
511 	*cs->cs_reg_csr = val;
512 	ZS_DELAY();
513 }
514 
515 uint8_t
516 zs_read_csr(struct zs_chanstate *cs)
517 {
518 	uint8_t val;
519 
520 	val = *cs->cs_reg_csr;
521 	ZS_DELAY();
522 	return (val);
523 }
524 
525 void
526 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
527 {
528 	*cs->cs_reg_csr = val;
529 	ZS_DELAY();
530 }
531 
532 uint8_t
533 zs_read_data(struct zs_chanstate *cs)
534 {
535 	uint8_t val;
536 
537 	val = *cs->cs_reg_data;
538 	ZS_DELAY();
539 	return (val);
540 }
541 
542 void
543 zs_write_data(struct zs_chanstate *cs, uint8_t val)
544 {
545 	*cs->cs_reg_data = val;
546 	ZS_DELAY();
547 }
548 
549 /****************************************************************
550  * Console support functions (Sun specific!)
551  * Note: this code is allowed to know about the layout of
552  * the chip registers, and uses that to keep things simple.
553  * XXX - I think I like the mvme167 code better. -gwr
554  ****************************************************************/
555 
556 extern void Debugger(void);
557 
558 /*
559  * Handle user request to enter kernel debugger.
560  */
561 void
562 zs_abort(struct zs_chanstate *cs)
563 {
564 	volatile struct zschan *zc = zs_conschan_get;
565 	int rr0;
566 
567 	/* Wait for end of break to avoid PROM abort. */
568 	/* XXX - Limit the wait? */
569 	do {
570 		rr0 = zc->zc_csr;
571 		ZS_DELAY();
572 	} while (rr0 & ZSRR0_BREAK);
573 
574 #if defined(KGDB)
575 	zskgdb(cs);
576 #elif defined(DDB)
577 	{
578 		extern int db_active;
579 
580 		if (!db_active)
581 			Debugger();
582 		else
583 			/* Debugger is probably hozed */
584 			callrom();
585 	}
586 #else
587 	printf("stopping on keyboard abort\n");
588 	callrom();
589 #endif
590 }
591 
592 
593 /*
594  * Polled input char.
595  */
596 int
597 zs_getc(void *arg)
598 {
599 	volatile struct zschan *zc = arg;
600 	int s, c, rr0;
601 
602 	s = splhigh();
603 	/* Wait for a character to arrive. */
604 	do {
605 		rr0 = zc->zc_csr;
606 		ZS_DELAY();
607 	} while ((rr0 & ZSRR0_RX_READY) == 0);
608 
609 	c = zc->zc_data;
610 	ZS_DELAY();
611 	splx(s);
612 
613 	/*
614 	 * This is used by the kd driver to read scan codes,
615 	 * so don't translate '\r' ==> '\n' here...
616 	 */
617 	return (c);
618 }
619 
620 /*
621  * Polled output char.
622  */
623 void
624 zs_putc(void *arg, int c)
625 {
626 	volatile struct zschan *zc = arg;
627 	int s, rr0;
628 
629 	s = splhigh();
630 
631 	/* Wait for transmitter to become ready. */
632 	do {
633 		rr0 = zc->zc_csr;
634 		ZS_DELAY();
635 	} while ((rr0 & ZSRR0_TX_READY) == 0);
636 
637 	/*
638 	 * Send the next character.
639 	 * Now you'd think that this could be followed by a ZS_DELAY()
640 	 * just like all the other chip accesses, but it turns out that
641 	 * the `transmit-ready' interrupt isn't de-asserted until
642 	 * some period of time after the register write completes
643 	 * (more than a couple instructions).  So to avoid stray
644 	 * interrupts we put in the 2us delay regardless of CPU model.
645 	 */
646 	zc->zc_data = c;
647 	delay(2);
648 
649 	splx(s);
650 }
651 
652 /*****************************************************************/
653 
654 
655 
656 
657 /*
658  * Polled console input putchar.
659  */
660 static int
661 zscngetc(dev_t dev)
662 {
663 	return (zs_getc(zs_conschan_get));
664 }
665 
666 /*
667  * Polled console output putchar.
668  */
669 static void
670 zscnputc(dev_t dev, int c)
671 {
672 	zs_putc(zs_conschan_put, c);
673 }
674 
675 int swallow_zsintrs;
676 
677 static void
678 zscnpollc(dev_t dev, int on)
679 {
680 	/*
681 	 * Need to tell zs driver to acknowledge all interrupts or we get
682 	 * annoying spurious interrupt messages.  This is because mucking
683 	 * with spl() levels during polling does not prevent interrupts from
684 	 * being generated.
685 	 */
686 
687 	if (on) swallow_zsintrs++;
688 	else swallow_zsintrs--;
689 }
690 
691