1 /* $NetBSD: if_ie_mbmem.c,v 1.9 2005/12/11 12:19:16 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1995 Charles D. Cranor 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles D. Cranor. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Converted to SUN ie driver by Charles D. Cranor, 35 * October 1994, January 1995. 36 */ 37 38 /* 39 * The i82586 is a very painful chip, found in sun2's, sun3's, sun-4/100's 40 * sun-4/200's, and VME based suns. The byte order is all wrong for a 41 * SUN, making life difficult. Programming this chip is mostly the same, 42 * but certain details differ from system to system. This driver is 43 * written so that different "ie" interfaces can be controled by the same 44 * driver. 45 */ 46 47 /* 48 * programming notes: 49 * 50 * the ie chip operates in a 24 bit address space. 51 * 52 * most ie interfaces appear to be divided into two parts: 53 * - generic 586 stuff 54 * - board specific 55 * 56 * generic: 57 * the generic stuff of the ie chip is all done with data structures 58 * that live in the chip's memory address space. the chip expects 59 * its main data structure (the sys conf ptr -- SCP) to be at a fixed 60 * address in its 24 bit space: 0xfffff4 61 * 62 * the SCP points to another structure called the ISCP. 63 * the ISCP points to another structure called the SCB. 64 * the SCB has a status field, a linked list of "commands", and 65 * a linked list of "receive buffers". these are data structures that 66 * live in memory, not registers. 67 * 68 * board: 69 * to get the chip to do anything, you first put a command in the 70 * command data structure list. then you have to signal "attention" 71 * to the chip to get it to look at the command. how you 72 * signal attention depends on what board you have... on PC's 73 * there is an i/o port number to do this, on sun's there is a 74 * register bit you toggle. 75 * 76 * to get data from the chip you program it to interrupt... 77 * 78 * 79 * sun issues: 80 * 81 * there are 3 kinds of sun "ie" interfaces: 82 * 1 - a VME/multibus card 83 * 2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's) 84 * 3 - another VME board called the 3E 85 * 86 * the VME boards lives in vme16 space. only 16 and 8 bit accesses 87 * are allowed, so functions that copy data must be aware of this. 88 * 89 * the chip is an intel chip. this means that the byte order 90 * on all the "short"s in the chip's data structures is wrong. 91 * so, constants described in the intel docs are swapped for the sun. 92 * that means that any buffer pointers you give the chip must be 93 * swapped to intel format. yuck. 94 * 95 * VME/multibus interface: 96 * for the multibus interface the board ignores the top 4 bits 97 * of the chip address. the multibus interface has its own 98 * MMU like page map (without protections or valid bits, etc). 99 * there are 256 pages of physical memory on the board (each page 100 * is 1024 bytes). There are 1024 slots in the page map. so, 101 * a 1024 byte page takes up 10 bits of address for the offset, 102 * and if there are 1024 slots in the page that is another 10 bits 103 * of the address. That makes a 20 bit address, and as stated 104 * earlier the board ignores the top 4 bits, so that accounts 105 * for all 24 bits of address. 106 * 107 * Note that the last entry of the page map maps the top of the 108 * 24 bit address space and that the SCP is supposed to be at 109 * 0xfffff4 (taking into account allignment). so, 110 * for multibus, that entry in the page map has to be used for the SCP. 111 * 112 * The page map effects BOTH how the ie chip sees the 113 * memory, and how the host sees it. 114 * 115 * The page map is part of the "register" area of the board 116 * 117 * The page map to control where ram appears in the address space. 118 * We choose to have RAM start at 0 in the 24 bit address space. 119 * 120 * to get the phyiscal address of the board's RAM you must take the 121 * top 12 bits of the physical address of the register address and 122 * or in the 4 bits from the status word as bits 17-20 (remember that 123 * the board ignores the chip's top 4 address lines). For example: 124 * if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000. 125 * to get the 4 bits from the status word just do status & IEMBMEM_HADDR. 126 * suppose the value is "4". Then just shift it left 16 bits to get 127 * it into bits 17-20 (e.g. 0x40000). Then or it to get the 128 * address of RAM (in our example: 0xffe40000). see the attach routine! 129 * 130 * 131 * on-board interface: 132 * 133 * on the onboard ie interface the 24 bit address space is hardwired 134 * to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase 135 * will be 0xff000000. sc_maddr will be where ever we allocate RAM 136 * in KVA. note that since the SCP is at a fixed address it means 137 * that we have to allocate a fixed KVA for the SCP. 138 * <fill in useful info later> 139 * 140 * 141 * VME3E interface: 142 * 143 * <fill in useful info later> 144 * 145 */ 146 147 #include <sys/cdefs.h> 148 __KERNEL_RCSID(0, "$NetBSD: if_ie_mbmem.c,v 1.9 2005/12/11 12:19:16 christos Exp $"); 149 150 #include <sys/param.h> 151 #include <sys/systm.h> 152 #include <sys/errno.h> 153 #include <sys/device.h> 154 #include <sys/protosw.h> 155 #include <sys/socket.h> 156 157 #include <net/if.h> 158 #include <net/if_types.h> 159 #include <net/if_dl.h> 160 #include <net/if_media.h> 161 #include <net/if_ether.h> 162 163 #include <machine/autoconf.h> 164 #include <machine/idprom.h> 165 #include <machine/bus.h> 166 #include <machine/intr.h> 167 #include <machine/cpu.h> 168 169 #include <dev/ic/i82586reg.h> 170 #include <dev/ic/i82586var.h> 171 172 #include "locators.h" 173 174 /* 175 * VME/multibus definitions 176 */ 177 #define IEMBMEM_PAGESIZE 1024 /* bytes */ 178 #define IEMBMEM_PAGSHIFT 10 /* bits */ 179 #define IEMBMEM_NPAGES 256 /* number of pages on chip */ 180 #define IEMBMEM_MAPSZ 1024 /* number of entries in the map */ 181 182 /* 183 * PTE for the page map 184 */ 185 #define IEMBMEM_SBORDR 0x8000 /* sun byte order */ 186 #define IEMBMEM_IBORDR 0x0000 /* intel byte ordr */ 187 188 #define IEMBMEM_P2MEM 0x2000 /* memory is on P2 */ 189 #define IEMBMEM_OBMEM 0x0000 /* memory is on board */ 190 191 #define IEMBMEM_PGMASK 0x0fff /* gives the physical page frame number */ 192 193 struct iembmem { 194 uint16_t pgmap[IEMBMEM_MAPSZ]; 195 uint16_t xxx[32]; /* prom */ 196 uint16_t status; /* see below for bits */ 197 uint16_t xxx2; /* filler */ 198 uint16_t pectrl; /* parity control (see below) */ 199 uint16_t peaddr; /* low 16 bits of address */ 200 }; 201 202 /* 203 * status bits 204 */ 205 #define IEMBMEM_RESET 0x8000 /* reset board */ 206 #define IEMBMEM_ONAIR 0x4000 /* go out of loopback 'on-air' */ 207 #define IEMBMEM_ATTEN 0x2000 /* attention */ 208 #define IEMBMEM_IENAB 0x1000 /* interrupt enable */ 209 #define IEMBMEM_PEINT 0x0800 /* parity error interrupt enable */ 210 #define IEMBMEM_PERR 0x0200 /* parity error flag */ 211 #define IEMBMEM_INT 0x0100 /* interrupt flag */ 212 #define IEMBMEM_P2EN 0x0020 /* enable p2 bus */ 213 #define IEMBMEM_256K 0x0010 /* 256kb rams */ 214 #define IEMBMEM_HADDR 0x000f /* mask for bits 17-20 of address */ 215 216 /* 217 * parity control 218 */ 219 #define IEMBMEM_PARACK 0x0100 /* parity error ack */ 220 #define IEMBMEM_PARSRC 0x0080 /* parity error source */ 221 #define IEMBMEM_PAREND 0x0040 /* which end of the data got the error */ 222 #define IEMBMEM_PARADR 0x000f /* mask to get bits 17-20 of parity address */ 223 224 /* Supported media */ 225 static int media[] = { 226 IFM_ETHER | IFM_10_2, 227 }; 228 #define NMEDIA (sizeof(media) / sizeof(media[0])) 229 230 /* 231 * the 3E board not supported (yet?) 232 */ 233 234 235 static void ie_mbmemreset(struct ie_softc *, int); 236 static void ie_mbmemattend(struct ie_softc *, int); 237 static void ie_mbmemrun(struct ie_softc *); 238 static int ie_mbmemintr(struct ie_softc *, int); 239 240 int ie_mbmem_match(struct device *, struct cfdata *, void *); 241 void ie_mbmem_attach(struct device *, struct device *, void *); 242 243 struct ie_mbmem_softc { 244 struct ie_softc ie; 245 bus_space_tag_t ievt; 246 bus_space_handle_t ievh; 247 }; 248 249 CFATTACH_DECL(ie_mbmem, sizeof(struct ie_mbmem_softc), 250 ie_mbmem_match, ie_mbmem_attach, NULL, NULL); 251 252 #define read_iev(sc, reg) \ 253 bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg)) 254 #define write_iev(sc, reg, val) \ 255 bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg), val) 256 257 /* 258 * MULTIBUS support routines 259 */ 260 void 261 ie_mbmemreset(struct ie_softc *sc, int what) 262 { 263 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 264 write_iev(vsc, status, IEMBMEM_RESET); 265 delay(100); /* XXX could be shorter? */ 266 write_iev(vsc, status, 0); 267 } 268 269 void 270 ie_mbmemattend(struct ie_softc *sc, int why) 271 { 272 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 273 274 /* flag! */ 275 write_iev(vsc, status, read_iev(vsc, status) | IEMBMEM_ATTEN); 276 /* down. */ 277 write_iev(vsc, status, read_iev(vsc, status) & ~IEMBMEM_ATTEN); 278 } 279 280 void 281 ie_mbmemrun(struct ie_softc *sc) 282 { 283 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 284 285 write_iev(vsc, status, read_iev(vsc, status) 286 | IEMBMEM_ONAIR | IEMBMEM_IENAB | IEMBMEM_PEINT); 287 } 288 289 int 290 ie_mbmemintr(struct ie_softc *sc, int where) 291 { 292 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc; 293 294 if (where != INTR_ENTER) 295 return (0); 296 297 /* 298 * check for parity error 299 */ 300 if (read_iev(vsc, status) & IEMBMEM_PERR) { 301 printf("%s: parity error (ctrl 0x%x @ 0x%02x%04x)\n", 302 sc->sc_dev.dv_xname, read_iev(vsc, pectrl), 303 read_iev(vsc, pectrl) & IEMBMEM_HADDR, 304 read_iev(vsc, peaddr)); 305 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK); 306 } 307 return (0); 308 } 309 310 void ie_mbmemcopyin(struct ie_softc *, void *, int, size_t); 311 void ie_mbmemcopyout(struct ie_softc *, const void *, int, size_t); 312 313 /* 314 * Copy board memory to kernel. 315 */ 316 void 317 ie_mbmemcopyin(struct ie_softc *sc, void *p, int offset, size_t size) 318 { 319 bus_space_copyin(sc->bt, sc->bh, offset, p, size); 320 } 321 322 /* 323 * Copy from kernel space to board memory. 324 */ 325 void 326 ie_mbmemcopyout(struct ie_softc *sc, const void *p, int offset, size_t size) 327 { 328 bus_space_copyout(sc->bt, sc->bh, offset, p, size); 329 } 330 331 /* read a 16-bit value at BH offset */ 332 uint16_t ie_mbmem_read16(struct ie_softc *, int offset); 333 /* write a 16-bit value at BH offset */ 334 void ie_mbmem_write16(struct ie_softc *, int offset, uint16_t value); 335 void ie_mbmem_write24(struct ie_softc *, int offset, int addr); 336 337 uint16_t 338 ie_mbmem_read16(struct ie_softc *sc, int offset) 339 { 340 uint16_t v; 341 342 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_READ); 343 v = bus_space_read_2(sc->bt, sc->bh, offset); 344 return (((v&0xff)<<8) | ((v>>8)&0xff)); 345 } 346 347 void 348 ie_mbmem_write16(struct ie_softc *sc, int offset, uint16_t v) 349 { 350 int v0 = ((((v)&0xff)<<8) | (((v)>>8)&0xff)); 351 352 bus_space_write_2(sc->bt, sc->bh, offset, v0); 353 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_WRITE); 354 } 355 356 void 357 ie_mbmem_write24(struct ie_softc *sc, int offset, int addr) 358 { 359 u_char *f = (u_char *)&addr; 360 uint16_t v0, v1; 361 u_char *t; 362 363 t = (u_char *)&v0; 364 t[0] = f[3]; t[1] = f[2]; 365 bus_space_write_2(sc->bt, sc->bh, offset, v0); 366 367 t = (u_char *)&v1; 368 t[0] = f[1]; t[1] = 0; 369 bus_space_write_2(sc->bt, sc->bh, offset+2, v1); 370 371 bus_space_barrier(sc->bt, sc->bh, offset, 4, BUS_SPACE_BARRIER_WRITE); 372 } 373 374 int 375 ie_mbmem_match(struct device *parent, struct cfdata *cf, void *aux) 376 { 377 struct mbmem_attach_args *mbma = aux; 378 bus_space_handle_t bh; 379 int matched; 380 381 /* No default Multibus address. */ 382 if (mbma->mbma_paddr == -1) 383 return(0); 384 385 /* Make sure there is something there... */ 386 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem), 387 0, &bh)) 388 return (0); 389 matched = (bus_space_peek_2(mbma->mbma_bustag, bh, 0, NULL) == 0); 390 bus_space_unmap(mbma->mbma_bustag, bh, sizeof(struct iembmem)); 391 if (!matched) 392 return (0); 393 394 /* Default interrupt priority. */ 395 if (mbma->mbma_pri == -1) 396 mbma->mbma_pri = 3; 397 398 return (1); 399 } 400 401 void 402 ie_mbmem_attach(struct device *parent, struct device *self, void *aux) 403 { 404 uint8_t myaddr[ETHER_ADDR_LEN]; 405 struct ie_mbmem_softc *vsc = (void *) self; 406 struct mbmem_attach_args *mbma = aux; 407 struct ie_softc *sc; 408 bus_size_t memsize; 409 bus_addr_t rampaddr; 410 int lcv; 411 412 sc = &vsc->ie; 413 414 sc->hwreset = ie_mbmemreset; 415 sc->hwinit = ie_mbmemrun; 416 sc->chan_attn = ie_mbmemattend; 417 sc->intrhook = ie_mbmemintr; 418 sc->memcopyout = ie_mbmemcopyout; 419 sc->memcopyin = ie_mbmemcopyin; 420 421 sc->ie_bus_barrier = NULL; 422 sc->ie_bus_read16 = ie_mbmem_read16; 423 sc->ie_bus_write16 = ie_mbmem_write16; 424 sc->ie_bus_write24 = ie_mbmem_write24; 425 426 /* 427 * There is 64K of memory on the Multibus board. 428 * (determined by hardware - NOT configurable!) 429 */ 430 memsize = 0x10000; /* MEMSIZE 64K */ 431 432 /* Map in the board control regs. */ 433 vsc->ievt = mbma->mbma_bustag; 434 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem), 435 0, &vsc->ievh)) 436 panic("ie_mbmem_attach: can't map regs"); 437 438 /* 439 * Find and map in the board memory. 440 */ 441 /* top 12 bits */ 442 rampaddr = mbma->mbma_paddr & 0xfff00000; 443 /* 4 more */ 444 rampaddr = rampaddr | ((read_iev(vsc, status) & IEMBMEM_HADDR) << 16); 445 sc->bt = mbma->mbma_bustag; 446 if (bus_space_map(mbma->mbma_bustag, rampaddr, memsize, 0, &sc->bh)) 447 panic("ie_mbmem_attach: can't map mem"); 448 449 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK); 450 451 /* 452 * Set up mappings, direct map except for last page 453 * which is mapped at zero and at high address (for scp) 454 */ 455 for (lcv = 0; lcv < IEMBMEM_MAPSZ - 1; lcv++) 456 write_iev(vsc, pgmap[lcv], IEMBMEM_SBORDR | IEMBMEM_OBMEM | lcv); 457 write_iev(vsc, pgmap[IEMBMEM_MAPSZ - 1], IEMBMEM_SBORDR | IEMBMEM_OBMEM | 0); 458 459 /* Clear all ram */ 460 bus_space_set_region_2(sc->bt, sc->bh, 0, 0, memsize/2); 461 462 /* 463 * We use the first page to set up SCP, ICSP and SCB data 464 * structures. The remaining pages become the buffer area 465 * (managed in i82586.c). 466 * SCP is in double-mapped page, so the 586 can see it at 467 * the mandatory magic address (IE_SCP_ADDR). 468 */ 469 sc->scp = (IE_SCP_ADDR & (IEMBMEM_PAGESIZE - 1)); 470 471 /* iscp at location zero */ 472 sc->iscp = 0; 473 474 /* scb follows iscp */ 475 sc->scb = IE_ISCP_SZ; 476 477 ie_mbmem_write16(sc, IE_ISCP_SCB((long)sc->iscp), sc->scb); 478 ie_mbmem_write16(sc, IE_ISCP_BASE((u_long)sc->iscp), 0); 479 ie_mbmem_write24(sc, IE_SCP_ISCP((u_long)sc->scp), 0); 480 481 if (i82586_proberam(sc) == 0) { 482 printf(": memory probe failed\n"); 483 return; 484 } 485 486 /* 487 * Rest of first page is unused; rest of ram for buffers. 488 */ 489 sc->buf_area = IEMBMEM_PAGESIZE; 490 sc->buf_area_sz = memsize - IEMBMEM_PAGESIZE; 491 492 sc->do_xmitnopchain = 0; 493 494 printf("\n%s:", self->dv_xname); 495 496 /* Set the ethernet address. */ 497 idprom_etheraddr(myaddr); 498 499 i82586_attach(sc, "multibus", myaddr, media, NMEDIA, media[0]); 500 501 bus_intr_establish(mbma->mbma_bustag, mbma->mbma_pri, IPL_NET, 0, 502 i82586_intr, sc); 503 } 504