1 /* $NetBSD: cpu.c,v 1.75 2008/04/14 16:19:18 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. All advertising materials mentioning features or use of this software 29 * must display the following acknowledgement: 30 * This product includes software developed by Aaron Brown and 31 * Harvard University. 32 * This product includes software developed by the University of 33 * California, Berkeley and its contributors. 34 * 4. Neither the name of the University nor the names of its contributors 35 * may be used to endorse or promote products derived from this software 36 * without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 48 * SUCH DAMAGE. 49 * 50 * @(#)cpu.c 8.5 (Berkeley) 11/23/93 51 * 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.75 2008/04/14 16:19:18 nakayama Exp $"); 56 57 #include "opt_multiprocessor.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/device.h> 62 #include <sys/kernel.h> 63 64 #include <uvm/uvm_extern.h> 65 66 #include <machine/autoconf.h> 67 #include <machine/cpu.h> 68 #include <machine/reg.h> 69 #include <machine/trap.h> 70 #include <machine/pmap.h> 71 #include <machine/sparc64.h> 72 #include <machine/openfirm.h> 73 74 #include <sparc64/sparc64/cache.h> 75 76 int ecache_min_line_size; 77 78 /* Linked list of all CPUs in system. */ 79 int sparc_ncpus = 0; 80 struct cpu_info *cpus = NULL; 81 82 volatile sparc64_cpuset_t cpus_active;/* set of active cpus */ 83 struct cpu_bootargs *cpu_args; /* allocated very early in pmap_bootstrap. */ 84 85 static struct cpu_info *alloc_cpuinfo(u_int); 86 87 /* The following are used externally (sysctl_hw). */ 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 char cpu_model[100]; /* machine model (primary CPU) */ 91 extern char machine_model[]; 92 93 #ifdef MULTIPROCESSOR 94 static const char *ipi_evcnt_names[IPI_EVCNT_NUM] = IPI_EVCNT_NAMES; 95 #endif 96 97 static void cpu_reset_fpustate(void); 98 99 /* The CPU configuration driver. */ 100 void cpu_attach(struct device *, struct device *, void *); 101 int cpu_match(struct device *, struct cfdata *, void *); 102 103 CFATTACH_DECL(cpu, sizeof(struct device), 104 cpu_match, cpu_attach, NULL, NULL); 105 106 struct cpu_info * 107 alloc_cpuinfo(u_int cpu_node) 108 { 109 paddr_t pa0, pa; 110 vaddr_t va, va0; 111 vsize_t sz = 8 * PAGE_SIZE; 112 int portid; 113 struct cpu_info *cpi, *ci; 114 extern paddr_t cpu0paddr; 115 116 /* 117 * Check for UPAID in the cpus list. 118 */ 119 if (OF_getprop(cpu_node, "upa-portid", &portid, sizeof(portid)) <= 0) 120 panic("alloc_cpuinfo: upa-portid"); 121 122 for (cpi = cpus; cpi != NULL; cpi = cpi->ci_next) 123 if (cpi->ci_cpuid == portid) 124 return cpi; 125 126 /* Allocate the aligned VA and determine the size. */ 127 va = uvm_km_alloc(kernel_map, sz, 8 * PAGE_SIZE, UVM_KMF_VAONLY); 128 if (!va) 129 panic("alloc_cpuinfo: no virtual space"); 130 va0 = va; 131 132 pa0 = cpu0paddr; 133 cpu0paddr += sz; 134 135 for (pa = pa0; pa < cpu0paddr; pa += PAGE_SIZE, va += PAGE_SIZE) 136 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 137 138 pmap_update(pmap_kernel()); 139 140 cpi = (struct cpu_info *)(va0 + CPUINFO_VA - INTSTACK); 141 142 memset((void *)va0, 0, sz); 143 144 /* 145 * Initialize cpuinfo structure. 146 * 147 * Arrange pcb, idle stack and interrupt stack in the same 148 * way as is done for the boot CPU in pmap.c. 149 */ 150 cpi->ci_next = NULL; 151 cpi->ci_curlwp = NULL; 152 cpi->ci_cpuid = portid; 153 cpi->ci_fplwp = NULL; 154 cpi->ci_spinup = NULL; 155 cpi->ci_paddr = pa0; 156 cpi->ci_self = cpi; 157 cpi->ci_node = cpu_node; 158 cpi->ci_idepth = -1; 159 memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending)); 160 161 /* 162 * Finally, add itself to the list of active cpus. 163 */ 164 for (ci = cpus; ci->ci_next != NULL; ci = ci->ci_next) 165 ; 166 #ifdef MULTIPROCESSOR 167 ci->ci_next = cpi; 168 #endif 169 return (cpi); 170 } 171 172 int 173 cpu_match(struct device *parent, struct cfdata *cf, void *aux) 174 { 175 struct mainbus_attach_args *ma = aux; 176 177 return (strcmp(cf->cf_name, ma->ma_name) == 0); 178 } 179 180 static void 181 cpu_reset_fpustate(void) 182 { 183 struct fpstate64 *fpstate; 184 struct fpstate64 fps[2]; 185 186 /* This needs to be 64-bit aligned */ 187 fpstate = ALIGNFPSTATE(&fps[1]); 188 189 /* 190 * Get the FSR and clear any exceptions. If we do not unload 191 * the queue here and it is left over from a previous crash, we 192 * will panic in the first loadfpstate(), due to a sequence error, 193 * so we need to dump the whole state anyway. 194 */ 195 fpstate->fs_fsr = 7 << FSR_VER_SHIFT; /* 7 is reserved for "none" */ 196 savefpstate(fpstate); 197 } 198 199 /* 200 * Attach the CPU. 201 * Discover interesting goop about the virtual address cache 202 * (slightly funny place to do it, but this is where it is to be found). 203 */ 204 void 205 cpu_attach(struct device *parent, struct device *dev, void *aux) 206 { 207 int node; 208 long clk; 209 struct mainbus_attach_args *ma = aux; 210 struct cpu_info *ci; 211 const char *sep; 212 register int i, l; 213 int bigcache, cachesize; 214 char buf[100]; 215 int totalsize = 0; 216 int linesize; 217 static bool passed = false; 218 219 /* tell them what we have */ 220 node = ma->ma_node; 221 222 /* 223 * Allocate cpu_info structure if needed. 224 */ 225 ci = alloc_cpuinfo((u_int)node); 226 227 /* 228 * Only do this on the boot cpu. Other cpu's call 229 * cpu_reset_fpustate() from cpu_hatch() before they 230 * call into the idle loop. 231 * For other cpus, we need to call mi_cpu_attach() 232 * and complete setting up cpcb. 233 */ 234 if (!passed) { 235 passed = true; 236 cpu_reset_fpustate(); 237 } 238 #ifdef MULTIPROCESSOR 239 else { 240 mi_cpu_attach(ci); 241 ci->ci_cpcb = (struct pcb *)ci->ci_data.cpu_idlelwp->l_addr; 242 } 243 for (i = 0; i < IPI_EVCNT_NUM; ++i) 244 evcnt_attach_dynamic(&ci->ci_ipi_evcnt[i], EVCNT_TYPE_INTR, 245 NULL, device_xname(dev), ipi_evcnt_names[i]); 246 #endif 247 evcnt_attach_dynamic(&ci->ci_tick_evcnt, EVCNT_TYPE_INTR, NULL, 248 device_xname(dev), "timer"); 249 250 clk = prom_getpropint(node, "clock-frequency", 0); 251 if (clk == 0) { 252 /* 253 * Try to find it in the OpenPROM root... 254 */ 255 clk = prom_getpropint(findroot(), "clock-frequency", 0); 256 } 257 if (clk) { 258 /* Tell OS what frequency we run on */ 259 ci->ci_cpu_clockrate[0] = clk; 260 ci->ci_cpu_clockrate[1] = clk / 1000000; 261 } 262 263 snprintf(buf, sizeof buf, "%s @ %s MHz", 264 prom_getpropstring(node, "name"), clockfreq(clk)); 265 snprintf(cpu_model, sizeof cpu_model, "%s (%s)", machine_model, buf); 266 267 printf(": %s, UPA id %d\n", buf, ci->ci_cpuid); 268 printf("%s:", device_xname(dev)); 269 270 bigcache = 0; 271 272 linesize = l = 273 prom_getpropint(node, "icache-line-size", 0); 274 for (i = 0; (1 << i) < l && l; i++) 275 /* void */; 276 if ((1 << i) != l && l) 277 panic("bad icache line size %d", l); 278 totalsize = 279 prom_getpropint(node, "icache-size", 0) * 280 prom_getpropint(node, "icache-associativity", 1); 281 if (totalsize == 0) 282 totalsize = l * 283 prom_getpropint(node, "icache-nlines", 64) * 284 prom_getpropint(node, "icache-associativity", 1); 285 286 cachesize = totalsize / 287 prom_getpropint(node, "icache-associativity", 1); 288 bigcache = cachesize; 289 290 sep = " "; 291 if (totalsize > 0) { 292 printf("%s%ldK instruction (%ld b/l)", sep, 293 (long)totalsize/1024, 294 (long)linesize); 295 sep = ", "; 296 } 297 298 linesize = l = 299 prom_getpropint(node, "dcache-line-size",0); 300 for (i = 0; (1 << i) < l && l; i++) 301 /* void */; 302 if ((1 << i) != l && l) 303 panic("bad dcache line size %d", l); 304 totalsize = 305 prom_getpropint(node, "dcache-size", 0) * 306 prom_getpropint(node, "dcache-associativity", 1); 307 if (totalsize == 0) 308 totalsize = l * 309 prom_getpropint(node, "dcache-nlines", 128) * 310 prom_getpropint(node, "dcache-associativity", 1); 311 312 cachesize = totalsize / 313 prom_getpropint(node, "dcache-associativity", 1); 314 if (cachesize > bigcache) 315 bigcache = cachesize; 316 317 if (totalsize > 0) { 318 printf("%s%ldK data (%ld b/l)", sep, 319 (long)totalsize/1024, 320 (long)linesize); 321 sep = ", "; 322 } 323 324 linesize = l = 325 prom_getpropint(node, "ecache-line-size", 0); 326 for (i = 0; (1 << i) < l && l; i++) 327 /* void */; 328 if ((1 << i) != l && l) 329 panic("bad ecache line size %d", l); 330 totalsize = 331 prom_getpropint(node, "ecache-size", 0) * 332 prom_getpropint(node, "ecache-associativity", 1); 333 if (totalsize == 0) 334 totalsize = l * 335 prom_getpropint(node, "ecache-nlines", 32768) * 336 prom_getpropint(node, "ecache-associativity", 1); 337 338 cachesize = totalsize / 339 prom_getpropint(node, "ecache-associativity", 1); 340 if (cachesize > bigcache) 341 bigcache = cachesize; 342 343 if (totalsize > 0) { 344 printf("%s%ldK external (%ld b/l)", sep, 345 (long)totalsize/1024, 346 (long)linesize); 347 } 348 printf("\n"); 349 350 if (ecache_min_line_size == 0 || 351 linesize < ecache_min_line_size) 352 ecache_min_line_size = linesize; 353 354 /* 355 * Now that we know the size of the largest cache on this CPU, 356 * re-color our pages. 357 */ 358 uvm_page_recolor(atop(bigcache)); /* XXX */ 359 360 } 361 362 #if defined(MULTIPROCESSOR) 363 vaddr_t cpu_spinup_trampoline; 364 365 /* 366 * Start secondary processors in motion. 367 */ 368 void 369 cpu_boot_secondary_processors() 370 { 371 int i, pstate; 372 struct cpu_info *ci; 373 374 sparc64_ipi_init(); 375 376 for (ci = cpus; ci != NULL; ci = ci->ci_next) { 377 if (ci->ci_cpuid == CPU_UPAID) 378 continue; 379 380 cpu_pmap_prepare(ci, false); 381 cpu_args->cb_node = ci->ci_node; 382 cpu_args->cb_cpuinfo = ci->ci_paddr; 383 membar_sync(); 384 385 /* Disable interrupts and start another CPU. */ 386 pstate = getpstate(); 387 setpstate(PSTATE_KERN); 388 389 prom_startcpu(ci->ci_node, (void *)cpu_spinup_trampoline, 0); 390 391 for (i = 0; i < 2000; i++) { 392 membar_sync(); 393 if (CPUSET_HAS(cpus_active, ci->ci_index)) 394 break; 395 delay(10000); 396 } 397 setpstate(pstate); 398 399 if (!CPUSET_HAS(cpus_active, ci->ci_index)) 400 printf("cpu%d: startup failed\n", ci->ci_cpuid); 401 } 402 } 403 404 void 405 cpu_hatch() 406 { 407 char *v = (char*)CPUINFO_VA; 408 int i; 409 410 for (i = 0; i < 4*PAGE_SIZE; i += sizeof(long)) 411 flush(v + i); 412 413 cpu_pmap_init(curcpu()); 414 CPUSET_ADD(cpus_active, cpu_number()); 415 cpu_reset_fpustate(); 416 curlwp = curcpu()->ci_data.cpu_idlelwp; 417 membar_sync(); 418 tickintr_establish(PIL_CLOCK, tickintr); 419 spl0(); 420 } 421 #endif /* MULTIPROCESSOR */ 422