1 /* $NetBSD: cpu.c,v 1.103 2012/11/08 00:34:38 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. All advertising materials mentioning features or use of this software 29 * must display the following acknowledgement: 30 * This product includes software developed by Aaron Brown and 31 * Harvard University. 32 * This product includes software developed by the University of 33 * California, Berkeley and its contributors. 34 * 4. Neither the name of the University nor the names of its contributors 35 * may be used to endorse or promote products derived from this software 36 * without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 48 * SUCH DAMAGE. 49 * 50 * @(#)cpu.c 8.5 (Berkeley) 11/23/93 51 * 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.103 2012/11/08 00:34:38 macallan Exp $"); 56 57 #include "opt_multiprocessor.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/device.h> 62 #include <sys/kernel.h> 63 #include <sys/reboot.h> 64 65 #include <uvm/uvm.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/cpu.h> 69 #include <machine/reg.h> 70 #include <machine/trap.h> 71 #include <machine/pmap.h> 72 #include <machine/sparc64.h> 73 #include <machine/openfirm.h> 74 75 #include <sparc64/sparc64/cache.h> 76 77 int ecache_min_line_size; 78 79 /* Linked list of all CPUs in system. */ 80 #if defined(MULTIPROCESSOR) 81 int sparc_ncpus = 0; 82 #endif 83 struct cpu_info *cpus = NULL; 84 85 volatile sparc64_cpuset_t cpus_active;/* set of active cpus */ 86 struct cpu_bootargs *cpu_args; /* allocated very early in pmap_bootstrap. */ 87 struct pool_cache *fpstate_cache; 88 89 static struct cpu_info *alloc_cpuinfo(u_int); 90 91 /* The following are used externally (sysctl_hw). */ 92 char machine[] = MACHINE; /* from <machine/param.h> */ 93 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 94 char cpu_model[100]; /* machine model (primary CPU) */ 95 extern char machine_model[]; 96 97 /* These are used in locore.s, and are maximums */ 98 int dcache_line_size; 99 int dcache_size; 100 int icache_line_size; 101 int icache_size; 102 103 #ifdef MULTIPROCESSOR 104 static const char *ipi_evcnt_names[IPI_EVCNT_NUM] = IPI_EVCNT_NAMES; 105 #endif 106 107 static void cpu_reset_fpustate(void); 108 109 volatile int sync_tick = 0; 110 111 /* The CPU configuration driver. */ 112 void cpu_attach(device_t, device_t, void *); 113 int cpu_match(device_t, cfdata_t, void *); 114 115 CFATTACH_DECL_NEW(cpu, 0, cpu_match, cpu_attach, NULL, NULL); 116 117 static int 118 upaid_from_node(u_int cpu_node) 119 { 120 int portid; 121 122 if (OF_getprop(cpu_node, "upa-portid", &portid, sizeof(portid)) <= 0 && 123 OF_getprop(cpu_node, "portid", &portid, sizeof(portid)) <= 0) 124 panic("cpu node w/o upa-portid"); 125 126 return portid; 127 } 128 129 struct cpu_info * 130 alloc_cpuinfo(u_int cpu_node) 131 { 132 paddr_t pa0, pa; 133 vaddr_t va, va0; 134 vsize_t sz = 8 * PAGE_SIZE; 135 int portid; 136 struct cpu_info *cpi, *ci; 137 extern paddr_t cpu0paddr; 138 139 /* 140 * Check for UPAID in the cpus list. 141 */ 142 portid = upaid_from_node(cpu_node); 143 144 for (cpi = cpus; cpi != NULL; cpi = cpi->ci_next) 145 if (cpi->ci_cpuid == portid) 146 return cpi; 147 148 /* Allocate the aligned VA and determine the size. */ 149 va = uvm_km_alloc(kernel_map, sz, 8 * PAGE_SIZE, UVM_KMF_VAONLY); 150 if (!va) 151 panic("alloc_cpuinfo: no virtual space"); 152 va0 = va; 153 154 pa0 = cpu0paddr; 155 cpu0paddr += sz; 156 157 for (pa = pa0; pa < cpu0paddr; pa += PAGE_SIZE, va += PAGE_SIZE) 158 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0); 159 160 pmap_update(pmap_kernel()); 161 162 cpi = (struct cpu_info *)(va0 + CPUINFO_VA - INTSTACK); 163 164 memset((void *)va0, 0, sz); 165 166 /* 167 * Initialize cpuinfo structure. 168 * 169 * Arrange pcb, idle stack and interrupt stack in the same 170 * way as is done for the boot CPU in pmap.c. 171 */ 172 cpi->ci_next = NULL; 173 cpi->ci_curlwp = NULL; 174 cpi->ci_cpuid = portid; 175 cpi->ci_fplwp = NULL; 176 cpi->ci_eintstack = NULL; 177 cpi->ci_spinup = NULL; 178 cpi->ci_paddr = pa0; 179 cpi->ci_self = cpi; 180 cpi->ci_node = cpu_node; 181 cpi->ci_idepth = -1; 182 memset(cpi->ci_intrpending, -1, sizeof(cpi->ci_intrpending)); 183 184 /* 185 * Finally, add itself to the list of active cpus. 186 */ 187 for (ci = cpus; ci->ci_next != NULL; ci = ci->ci_next) 188 ; 189 #ifdef MULTIPROCESSOR 190 ci->ci_next = cpi; 191 #endif 192 return (cpi); 193 } 194 195 int 196 cpu_match(device_t parent, cfdata_t cf, void *aux) 197 { 198 struct mainbus_attach_args *ma = aux; 199 200 if (strcmp(cf->cf_name, ma->ma_name) != 0) 201 return 0; 202 203 /* 204 * If we are going to only attach a single cpu, make sure 205 * to pick the one we are running on right now. 206 */ 207 if (upaid_from_node(ma->ma_node) != CPU_UPAID) { 208 #ifdef MULTIPROCESSOR 209 if (boothowto & RB_MD1) 210 #endif 211 return 0; 212 } 213 214 return 1; 215 } 216 217 static void 218 cpu_reset_fpustate(void) 219 { 220 struct fpstate64 *fpstate; 221 struct fpstate64 fps[2]; 222 223 /* This needs to be 64-byte aligned */ 224 fpstate = ALIGNFPSTATE(&fps[1]); 225 226 /* 227 * Get the FSR and clear any exceptions. If we do not unload 228 * the queue here and it is left over from a previous crash, we 229 * will panic in the first loadfpstate(), due to a sequence error, 230 * so we need to dump the whole state anyway. 231 */ 232 fpstate->fs_fsr = 7 << FSR_VER_SHIFT; /* 7 is reserved for "none" */ 233 savefpstate(fpstate); 234 } 235 236 /* 237 * Attach the CPU. 238 * Discover interesting goop about the virtual address cache 239 * (slightly funny place to do it, but this is where it is to be found). 240 */ 241 void 242 cpu_attach(device_t parent, device_t dev, void *aux) 243 { 244 int node; 245 long clk, sclk = 0; 246 struct mainbus_attach_args *ma = aux; 247 struct cpu_info *ci; 248 const char *sep; 249 register int i, l; 250 int bigcache, cachesize; 251 char buf[100]; 252 int totalsize = 0; 253 int linesize, dcachesize, icachesize; 254 255 /* tell them what we have */ 256 node = ma->ma_node; 257 258 /* 259 * Allocate cpu_info structure if needed. 260 */ 261 ci = alloc_cpuinfo((u_int)node); 262 263 /* 264 * Only do this on the boot cpu. Other cpu's call 265 * cpu_reset_fpustate() from cpu_hatch() before they 266 * call into the idle loop. 267 * For other cpus, we need to call mi_cpu_attach() 268 * and complete setting up cpcb. 269 */ 270 if (ci->ci_flags & CPUF_PRIMARY) { 271 fpstate_cache = pool_cache_init(sizeof(struct fpstate64), 272 SPARC64_BLOCK_SIZE, 0, 0, "fpstate", 273 NULL, IPL_NONE, NULL, NULL, NULL); 274 cpu_reset_fpustate(); 275 } 276 #ifdef MULTIPROCESSOR 277 else { 278 mi_cpu_attach(ci); 279 ci->ci_cpcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 280 } 281 for (i = 0; i < IPI_EVCNT_NUM; ++i) 282 evcnt_attach_dynamic(&ci->ci_ipi_evcnt[i], EVCNT_TYPE_INTR, 283 NULL, device_xname(dev), ipi_evcnt_names[i]); 284 #endif 285 evcnt_attach_dynamic(&ci->ci_tick_evcnt, EVCNT_TYPE_INTR, NULL, 286 device_xname(dev), "timer"); 287 mutex_init(&ci->ci_ctx_lock, MUTEX_SPIN, IPL_VM); 288 289 clk = prom_getpropint(node, "clock-frequency", 0); 290 if (clk == 0) { 291 /* 292 * Try to find it in the OpenPROM root... 293 */ 294 clk = prom_getpropint(findroot(), "clock-frequency", 0); 295 } 296 if (clk) { 297 /* Tell OS what frequency we run on */ 298 ci->ci_cpu_clockrate[0] = clk; 299 ci->ci_cpu_clockrate[1] = clk / 1000000; 300 } 301 302 if (!CPU_IS_HUMMINGBIRD()) { 303 sclk = prom_getpropint(findroot(), "stick-frequency", 0); 304 } 305 ci->ci_system_clockrate[0] = sclk; 306 ci->ci_system_clockrate[1] = sclk / 1000000; 307 308 snprintf(buf, sizeof buf, "%s @ %s MHz", 309 prom_getpropstring(node, "name"), clockfreq(clk)); 310 snprintf(cpu_model, sizeof cpu_model, "%s (%s)", machine_model, buf); 311 312 aprint_normal(": %s, UPA id %d\n", buf, ci->ci_cpuid); 313 aprint_naive("\n"); 314 315 if (ci->ci_system_clockrate[0] != 0) { 316 aprint_normal_dev(dev, "system tick frequency %d MHz\n", 317 (int)ci->ci_system_clockrate[1]); 318 } 319 aprint_normal_dev(dev, ""); 320 321 bigcache = 0; 322 323 icachesize = prom_getpropint(node, "icache-size", 0); 324 if (icachesize > icache_size) 325 icache_size = icachesize; 326 linesize = l = prom_getpropint(node, "icache-line-size", 0); 327 if (linesize > icache_line_size) 328 icache_line_size = linesize; 329 330 for (i = 0; (1 << i) < l && l; i++) 331 /* void */; 332 if ((1 << i) != l && l) 333 panic("bad icache line size %d", l); 334 totalsize = icachesize; 335 if (totalsize == 0) 336 totalsize = l * 337 prom_getpropint(node, "icache-nlines", 64) * 338 prom_getpropint(node, "icache-associativity", 1); 339 340 cachesize = totalsize / 341 prom_getpropint(node, "icache-associativity", 1); 342 bigcache = cachesize; 343 344 sep = ""; 345 if (totalsize > 0) { 346 aprint_normal("%s%ldK instruction (%ld b/l)", sep, 347 (long)totalsize/1024, 348 (long)linesize); 349 sep = ", "; 350 } 351 352 dcachesize = prom_getpropint(node, "dcache-size", 0); 353 if (dcachesize > dcache_size) 354 dcache_size = dcachesize; 355 linesize = l = prom_getpropint(node, "dcache-line-size", 0); 356 if (linesize > dcache_line_size) 357 dcache_line_size = linesize; 358 359 for (i = 0; (1 << i) < l && l; i++) 360 /* void */; 361 if ((1 << i) != l && l) 362 panic("bad dcache line size %d", l); 363 totalsize = dcachesize; 364 if (totalsize == 0) 365 totalsize = l * 366 prom_getpropint(node, "dcache-nlines", 128) * 367 prom_getpropint(node, "dcache-associativity", 1); 368 369 cachesize = totalsize / 370 prom_getpropint(node, "dcache-associativity", 1); 371 if (cachesize > bigcache) 372 bigcache = cachesize; 373 374 if (totalsize > 0) { 375 aprint_normal("%s%ldK data (%ld b/l)", sep, 376 (long)totalsize/1024, 377 (long)linesize); 378 sep = ", "; 379 } 380 381 linesize = l = 382 prom_getpropint(node, "ecache-line-size", 0); 383 for (i = 0; (1 << i) < l && l; i++) 384 /* void */; 385 if ((1 << i) != l && l) 386 panic("bad ecache line size %d", l); 387 totalsize = prom_getpropint(node, "ecache-size", 0); 388 if (totalsize == 0) 389 totalsize = l * 390 prom_getpropint(node, "ecache-nlines", 32768) * 391 prom_getpropint(node, "ecache-associativity", 1); 392 393 cachesize = totalsize / 394 prom_getpropint(node, "ecache-associativity", 1); 395 if (cachesize > bigcache) 396 bigcache = cachesize; 397 398 if (totalsize > 0) { 399 aprint_normal("%s%ldK external (%ld b/l)", sep, 400 (long)totalsize/1024, 401 (long)linesize); 402 } 403 aprint_normal("\n"); 404 405 if (ecache_min_line_size == 0 || 406 linesize < ecache_min_line_size) 407 ecache_min_line_size = linesize; 408 409 /* 410 * Now that we know the size of the largest cache on this CPU, 411 * re-color our pages. 412 */ 413 uvm_page_recolor(atop(bigcache)); /* XXX */ 414 415 } 416 417 #if defined(MULTIPROCESSOR) 418 vaddr_t cpu_spinup_trampoline; 419 420 /* 421 * Start secondary processors in motion. 422 */ 423 void 424 cpu_boot_secondary_processors(void) 425 { 426 int i, pstate; 427 struct cpu_info *ci; 428 429 sync_tick = 0; 430 431 sparc64_ipi_init(); 432 433 if (boothowto & RB_MD1) { 434 cpus[0].ci_next = NULL; 435 sparc_ncpus = ncpu = ncpuonline = 1; 436 return; 437 } 438 439 for (ci = cpus; ci != NULL; ci = ci->ci_next) { 440 if (ci->ci_cpuid == CPU_UPAID) 441 continue; 442 443 cpu_pmap_prepare(ci, false); 444 cpu_args->cb_node = ci->ci_node; 445 cpu_args->cb_cpuinfo = ci->ci_paddr; 446 membar_Sync(); 447 448 /* Disable interrupts and start another CPU. */ 449 pstate = getpstate(); 450 setpstate(PSTATE_KERN); 451 452 prom_startcpu(ci->ci_node, (void *)cpu_spinup_trampoline, 0); 453 454 for (i = 0; i < 2000; i++) { 455 membar_Sync(); 456 if (CPUSET_HAS(cpus_active, ci->ci_index)) 457 break; 458 delay(10000); 459 } 460 461 /* synchronize %tick ( to some degree at least ) */ 462 delay(1000); 463 sync_tick = 1; 464 membar_Sync(); 465 settick(0); 466 if (ci->ci_system_clockrate[0] != 0) 467 setstick(0); 468 469 setpstate(pstate); 470 471 if (!CPUSET_HAS(cpus_active, ci->ci_index)) 472 printf("cpu%d: startup failed\n", ci->ci_cpuid); 473 } 474 } 475 476 void 477 cpu_hatch(void) 478 { 479 char *v = (char*)CPUINFO_VA; 480 int i; 481 482 for (i = 0; i < 4*PAGE_SIZE; i += sizeof(long)) 483 flush(v + i); 484 485 cpu_pmap_init(curcpu()); 486 CPUSET_ADD(cpus_active, cpu_number()); 487 cpu_reset_fpustate(); 488 curlwp = curcpu()->ci_data.cpu_idlelwp; 489 membar_Sync(); 490 491 /* wait for the boot CPU to flip the switch */ 492 while (sync_tick == 0) { 493 /* we do nothing here */ 494 } 495 settick(0); 496 if (curcpu()->ci_system_clockrate[0] != 0) { 497 setstick(0); 498 stickintr_establish(PIL_CLOCK, stickintr); 499 } else { 500 tickintr_establish(PIL_CLOCK, tickintr); 501 } 502 spl0(); 503 } 504 #endif /* MULTIPROCESSOR */ 505