1 /* $NetBSD: pte.h,v 1.22 2010/01/15 15:02:48 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _MACHINE_PTE_H_ 27 #define _MACHINE_PTE_H_ 28 29 #if defined(_KERNEL_OPT) 30 #include "opt_sparc_arch.h" 31 #endif 32 33 /* 34 * Address translation works as follows: 35 * 36 ** 37 * For sun4u: 38 * 39 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 40 * Oh, here's the sun4u TTE for reference: 41 * 42 * struct sun4u_tte { 43 * uint64 tag_g:1, (global flag) 44 * tag_reserved:2, (reserved for future use) 45 * tag_ctxt:13, (context for mapping) 46 * tag_unassigned:6, 47 * tag_va:42; (virtual address bits<64:22>) 48 * uint64 data_v:1, (valid bit) 49 * data_size:2, (page size [8K*8**<SIZE>]) 50 * data_nfo:1, (no-fault only) 51 * data_ie:1, (invert endianness [inefficient]) 52 * data_soft2:9, (reserved for S/W) 53 * data_reserved:7,(reserved for future use) 54 * data_pa:30, (physical address) 55 * data_soft:6, (reserved for S/W) 56 * data_lock:1, (lock into TLB) 57 * data_cacheable:2, (cacheability control) 58 * data_e:1, (explicit accesses only) 59 * data_priv:1, (privileged page) 60 * data_w:1, (writable) 61 * data_g:1; (same as tag_g) 62 * }; 63 */ 64 65 /* virtual address to virtual page number */ 66 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 67 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 68 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 69 70 /* virtual address to offset within page */ 71 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 72 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 73 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 74 75 /* When we go to 64-bit VAs we need to handle the hole */ 76 #define VA_VPG(va) VA_SUN4U_VPG(va) 77 #define VA_OFF(va) VA_SUN4U_OFF(va) 78 79 #define PG_SHIFT4U 13 80 #define MMU_PAGE_ALIGN 8192 81 82 /* If you know where a tte is in the tsb, how do you find its va? */ 83 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 84 85 #ifndef _LOCORE 86 /* 87 * This is the spitfire TTE. 88 * 89 * We could use bitmasks and shifts to construct this if 90 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 91 * a real pain to do this in C. 92 */ 93 #if 0 94 /* We don't use bitfeilds anyway. */ 95 struct sun4u_tag_fields { 96 uint64_t tag_g:1, /* global flag */ 97 tag_reserved:2, /* reserved for future use */ 98 tag_ctxt:13, /* context for mapping */ 99 tag_unassigned:6, 100 tag_va:42; /* virtual address bits<64:22> */ 101 }; 102 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 103 struct sun4u_data_fields { 104 uint64_t data_v:1, /* valid bit */ 105 data_size:2, /* page size [8K*8**<SIZE>] */ 106 data_nfo:1, /* no-fault only */ 107 data_ie:1, /* invert endianness [inefficient] */ 108 data_soft2:9, /* reserved for S/W */ 109 data_reserved:7,/* reserved for future use */ 110 data_pa:30, /* physical address */ 111 data_tsblock:1, /* S/W TSB locked entry */ 112 data_modified:1,/* S/W modified bit */ 113 data_realw:1, /* S/W real writable bit (to manage modified) */ 114 data_accessed:1,/* S/W accessed bit */ 115 data_exec:1, /* S/W Executable */ 116 data_onlyexec:1,/* S/W Executable only */ 117 data_lock:1, /* lock into TLB */ 118 data_cacheable:2, /* cacheability control */ 119 data_e:1, /* explicit accesses only */ 120 data_priv:1, /* privileged page */ 121 data_w:1, /* writable */ 122 data_g:1; /* same as tag_g */ 123 }; 124 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 125 struct sun4u_tte { 126 union sun4u_tag tag; 127 union sun4u_data data; 128 }; 129 #else 130 struct sun4u_tte { 131 int64_t tag; 132 int64_t data; 133 }; 134 #endif 135 typedef struct sun4u_tte pte_t; 136 137 #endif /* _LOCORE */ 138 139 /* TSB tag masks */ 140 #define CTX_MASK ((1<<13)-1) 141 #define TSB_TAG_CTX_SHIFT 48 142 #define TSB_TAG_VA_SHIFT 22 143 #define TSB_TAG_G 0x8000000000000000LL 144 145 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 146 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 147 #define TSB_TAG(g,ctx,va) ((((uint64_t)((g)!=0))<<63)|(((uint64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((uint64_t)va)>>TSB_TAG_VA_SHIFT)) 148 149 /* Page sizes */ 150 #define PGSZ_8K 0 151 #define PGSZ_64K 1 152 #define PGSZ_512K 2 153 #define PGSZ_4M 3 154 155 #define PGSZ_SHIFT 61 156 #define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT) 157 158 /* TLB data masks */ 159 #define TLB_V 0x8000000000000000LL 160 #define TLB_8K TLB_SZ(PGSZ_8K) 161 #define TLB_64K TLB_SZ(PGSZ_64K) 162 #define TLB_512K TLB_SZ(PGSZ_512K) 163 #define TLB_4M TLB_SZ(PGSZ_4M) 164 #define TLB_SZ_MASK 0x6000000000000000LL 165 #define TLB_NFO 0x1000000000000000LL 166 #define TLB_IE 0x0800000000000000LL 167 #define TLB_SOFT2_MASK 0x07fc000000000000LL 168 #define TLB_RESERVED_MASK 0x0003f80000000000LL 169 #define TLB_PA_MASK 0x000007ffffffe000LL 170 #define TLB_SOFT_MASK 0x0000000000001f80LL 171 /* S/W bits */ 172 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 173 /* #define TLB_ACCESS 0x0000000000001000LL */ 174 #define TLB_ACCESS 0x0000000000000200LL 175 #define TLB_MODIFY 0x0000000000000800LL 176 #define TLB_REAL_W 0x0000000000000400LL 177 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 178 #define TLB_TSB_LOCK 0x0000000000001000LL 179 #define TLB_EXEC 0x0000000000000100LL 180 #define TLB_EXEC_ONLY 0x0000000000000080LL 181 /* H/W bits */ 182 #define TLB_L 0x0000000000000040LL 183 #define TLB_CACHE_MASK 0x0000000000000030LL 184 #define TLB_CP 0x0000000000000020LL 185 #define TLB_CV 0x0000000000000010LL 186 #define TLB_E 0x0000000000000008LL 187 #define TLB_P 0x0000000000000004LL 188 #define TLB_W 0x0000000000000002LL 189 #define TLB_G 0x0000000000000001LL 190 191 /* Use a bit in the SOFT2 area to indicate a locked mapping. */ 192 #define TLB_WIRED 0x0010000000000000LL 193 194 /* 195 * The following bits are used by locore so they should 196 * be duplicates of the above w/o the "long long" 197 */ 198 /* S/W bits */ 199 /* #define TTE_ACCESS 0x0000000000001000 */ 200 #define TTE_ACCESS 0x0000000000000200 201 #define TTE_MODIFY 0x0000000000000800 202 #define TTE_REAL_W 0x0000000000000400 203 /* #define TTE_TSB_LOCK 0x0000000000000200 */ 204 #define TTE_TSB_LOCK 0x0000000000001000 205 #define TTE_EXEC 0x0000000000000100 206 #define TTE_EXEC_ONLY 0x0000000000000080 207 /* H/W bits */ 208 #define TTE_L 0x0000000000000040 209 #define TTE_CACHE_MASK 0x0000000000000030 210 #define TTE_CP 0x0000000000000020 211 #define TTE_CV 0x0000000000000010 212 #define TTE_E 0x0000000000000008 213 #define TTE_P 0x0000000000000004 214 #define TTE_W 0x0000000000000002 215 #define TTE_G 0x0000000000000001 216 217 #define TTE_DATA_BITS "\177\20" \ 218 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ 219 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ 220 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ 221 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ 222 "b\6L\0" "b\5CP\0" "b\4CV\0" \ 223 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" 224 225 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 226 (((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((uint64_t)(pa))&TLB_PA_MASK)|\ 227 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 228 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) 229 230 #define MMU_CACHE_VIRT 0x3 231 #define MMU_CACHE_PHYS 0x2 232 #define MMU_CACHE_NONE 0x0 233 234 /* This needs to be updated for sun4u IOMMUs */ 235 /* 236 * IOMMU PTE bits. 237 */ 238 #define IOPTE_PPN_MASK 0x07ffff00 239 #define IOPTE_PPN_SHIFT 8 240 #define IOPTE_RSVD 0x000000f1 241 #define IOPTE_WRITE 0x00000004 242 #define IOPTE_VALID 0x00000002 243 244 /* 245 * This is purely for compatibility with the old SPARC machines. 246 */ 247 #define NBPRG (1 << 24) /* bytes per region */ 248 #define RGSHIFT 24 /* log2(NBPRG) */ 249 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 250 251 #define NBPSG (1 << 18) /* bytes per segment */ 252 #define SGSHIFT 18 /* log2(NBPSG) */ 253 254 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 255 #define PG_V 0x80000000 256 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 257 258 /* virtual address to virtual region number */ 259 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 260 261 /* virtual address to virtual segment number */ 262 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 263 264 #ifndef _LOCORE 265 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 266 #endif 267 268 /* 269 * Here are the bit definitions for 4M/SRMMU pte's 270 */ 271 /* MMU TABLE ENTRIES */ 272 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 273 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 274 /* PTE FIELDS */ 275 #define SRMMU_PPNMASK 0xFFFFFF00 276 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 277 278 #endif /* _MACHINE_PTE_H_ */ 279