1 /* $NetBSD: param.h,v 1.44 2010/02/08 19:02:32 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)param.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * Copyright (c) 1996-2002 Eduardo Horvath 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 */ 65 66 #if defined(_KERNEL_OPT) 67 #include "opt_sparc_arch.h" 68 #endif 69 70 #ifdef __arch64__ 71 #define _MACHINE sparc64 72 #define MACHINE "sparc64" 73 #define _MACHINE_ARCH sparc64 74 #define MACHINE_ARCH "sparc64" 75 #define MID_MACHINE MID_SPARC64 76 #else 77 #define _MACHINE sparc 78 #define MACHINE "sparc" 79 #define _MACHINE_ARCH sparc 80 #define MACHINE_ARCH "sparc" 81 #define MID_MACHINE MID_SPARC 82 #endif 83 84 #ifdef _KERNEL /* XXX */ 85 #ifndef _LOCORE /* XXX */ 86 #include <machine/cpu.h> /* XXX */ 87 #endif /* XXX */ 88 #endif /* XXX */ 89 90 /* 91 * Round p (pointer or byte index) up to a correctly-aligned value for 92 * the machine's strictest data type. The result is u_int and must be 93 * cast to any desired pointer type. 94 * 95 * ALIGNED_POINTER is a boolean macro that checks whether an address 96 * is valid to fetch data elements of type t from on this architecture. 97 * This does not reflect the optimal alignment, just the possibility 98 * (within reasonable limits). 99 * 100 */ 101 #define ALIGNBYTES32 0x7 102 #define ALIGNBYTES64 0xf 103 #ifdef __arch64__ 104 #define ALIGNBYTES ALIGNBYTES64 105 #else 106 #define ALIGNBYTES ALIGNBYTES32 107 #endif 108 #define ALIGN(p) (((u_long)(p) + ALIGNBYTES) & ~ALIGNBYTES) 109 #define ALIGN32(p) (((u_long)(p) + ALIGNBYTES32) & ~ALIGNBYTES32) 110 #define ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0) 111 112 113 /* 114 * The following variables are always defined and initialized (in locore) 115 * so independently compiled modules (e.g. LKMs) can be used irrespective 116 * of the `options SUN4?' combination a particular kernel was configured with. 117 * See also the definitions of NBPG, PGOFSET and PGSHIFT below. 118 */ 119 #if (defined(_KERNEL) || defined(_STANDALONE)) && !defined(_LOCORE) 120 extern int nbpg, pgofset, pgshift; 121 #endif 122 123 #define DEV_BSIZE 512 124 #define DEV_BSHIFT 9 /* log2(DEV_BSIZE) */ 125 #define BLKDEV_IOSIZE 2048 126 #define MAXPHYS (64 * 1024) 127 128 #ifdef __arch64__ 129 /* We get stack overflows w/8K stacks in 64-bit mode */ 130 #define SSIZE 2 /* initial stack size in pages */ 131 #else 132 #define SSIZE 2 133 #endif 134 #define USPACE (SSIZE*8192) 135 136 137 /* 138 * Here are all the magic kernel virtual addresses and how they're allocated. 139 * 140 * First, the PROM is usually a fixed-sized block from 0x00000000f0000000 to 141 * 0x00000000f0100000. It also uses some space around 0x00000000fff00000 to 142 * map in device registers. The rest is pretty much ours to play with. 143 * 144 * The kernel starts at KERNBASE. Here's they layout. We use macros to set 145 * the addresses so we can relocate everything easily. We use 4MB locked TTEs 146 * to map in the kernel text and data segments. Any extra pages are recycled, 147 * so they can potentially be double-mapped. This shouldn't really be a 148 * problem since they're unused, but wild pointers can cause silent data 149 * corruption if they are in those segments. 150 * 151 * 0x0000000000000000: 64K NFO page zero 152 * 0x0000000000010000: Userland or PROM 153 * KERNBASE: 4MB kernel text and read only data 154 * This is mapped in the ITLB and 155 * Read-Only in the DTLB 156 * KERNBASE+0x400000: 4MB kernel data and BSS -- not in ITLB 157 * Contains context table, kernel pmap, 158 * and other important structures. 159 * KERNBASE+0x800000: Unmapped page -- redzone 160 * KERNBASE+0x802000: Process 0 stack and u-area 161 * KERNBASE+0x806000: 2 pages for pmap_copy_page and /dev/mem 162 * KERNBASE+0x80a000: Start of kernel VA segment 163 * KERNEND: End of kernel VA segment 164 * KERNEND+0x02000: Auxreg_va (unused?) 165 * KERNEND+0x04000: TMPMAP_VA (unused?) 166 * KERNEND+0x06000: message buffer. 167 * KERNEND+0x010000: INTSTACK -- per-cpu 64K locked TTE 168 * Contains interrupt stack (32KB), cpu_info structure 169 * and panicstack (32KB) 170 * KERNEND+0x018000: CPUINFO_VA -- cpu_info structure 171 * KERNEND+0x020000: unmapped space (top of panicstack) 172 * KERNEND+0x022000: IODEV_BASE -- begin mapping IO devices here. 173 * 0x00000000f0000000: IODEV_END -- end of device mapping space. 174 * 175 */ 176 #define KERNBASE 0x001000000 /* start of kernel virtual space */ 177 #define KERNEND 0x0e0000000 /* end of kernel virtual space */ 178 #define VM_MAX_KERNEL_BUF ((KERNEND-KERNBASE)/4) 179 180 #define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */ 181 182 #define AUXREG_VA ( KERNEND + _MAXNBPG) /* 1 page REDZONE */ 183 #define TMPMAP_VA ( AUXREG_VA + _MAXNBPG) 184 #define MSGBUF_VA ( TMPMAP_VA + _MAXNBPG) 185 /* 186 * Here's the location of the interrupt stack and CPU structure. 187 */ 188 #define INTSTACK ( KERNEND + 8*_MAXNBPG) 189 #define EINTSTACK ( INTSTACK + 4*_MAXNBPG) 190 #define CPUINFO_VA ( EINTSTACK ) 191 #define PANICSTACK ( INTSTACK + 8*_MAXNBPG) 192 #define IODEV_BASE ( INTSTACK + 9*_MAXNBPG) /* 1 page redzone */ 193 #define IODEV_END 0x0f0000000UL /* ~16 MB of iospace */ 194 195 /* 196 * Constants related to network buffer management. 197 * MCLBYTES must be no larger than NBPG (the software page size), and, 198 * on machines that exchange pages of input or output buffers with mbuf 199 * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple 200 * of the hardware page size. 201 */ 202 #define MSIZE 256 /* size of an mbuf */ 203 204 #ifndef MCLSHIFT 205 #define MCLSHIFT 11 /* convert bytes to m_buf clusters */ 206 /* 2K cluster can hold Ether frame */ 207 #endif /* MCLSHIFT */ 208 209 #define MCLBYTES (1 << MCLSHIFT) /* size of a m_buf cluster */ 210 211 #define MSGBUFSIZE NBPG 212 213 /* 214 * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized 215 * logical pages. 216 */ 217 #define NKMEMPAGES_MIN_DEFAULT ((6 * 1024 * 1024) >> PAGE_SHIFT) 218 #define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT) 219 220 #ifdef _KERNEL 221 #ifndef _LOCORE 222 223 extern void delay(unsigned int); 224 #define DELAY(n) delay(n) 225 226 #ifdef __arch64__ 227 /* If we're using a 64-bit kernel use 64-bit math */ 228 #define mstohz(ms) ((ms + 0UL) * hz / 1000) 229 #endif 230 231 extern int cputyp; 232 233 #endif /* _LOCORE */ 234 #endif /* _KERNEL */ 235 236 /* 237 * Values for the cputyp variable. 238 */ 239 #define CPU_SUN4 0 240 #define CPU_SUN4C 1 241 #define CPU_SUN4M 2 242 #define CPU_SUN4U 3 243 244 /* 245 * Shorthand CPU-type macros. Enumerate all eight cases. 246 * Let compiler optimize away code conditional on constants. 247 * 248 * On a sun4 machine, the page size is 8192, while on a sun4c and sun4m 249 * it is 4096. Therefore, in the (SUN4 && (SUN4C || SUN4M)) cases below, 250 * NBPG, PGOFSET and PGSHIFT are defined as variables which are initialized 251 * early in locore.s after the machine type has been detected. 252 * 253 * Note that whenever the macros defined below evaluate to expressions 254 * involving variables, the kernel will perform slightly worse due to the 255 * extra memory references they'll generate. 256 */ 257 258 #define CPU_ISSUN4U (1) 259 #define CPU_ISSUN4M (0) 260 #define CPU_ISSUN4C (0) 261 #define CPU_ISSUN4 (0) 262 263 264 #define PGSHIFT 13 /* log2(NBPG) */ 265 #define NBPG (1<<PGSHIFT) /* bytes/page */ 266 #define PGOFSET (NBPG-1) /* byte offset into page */ 267