1 /* $NetBSD: cpu.h,v 1.45 2004/06/18 12:51:39 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #define CTL_MACHDEP_NAMES { \ 56 { 0, 0 }, \ 57 { "booted_kernel", CTLTYPE_STRING }, \ 58 { "booted_device", CTLTYPE_STRING }, \ 59 { "boot_args", CTLTYPE_STRING }, \ 60 { "cpu_arch", CTLTYPE_INT }, \ 61 } 62 63 #ifdef _KERNEL 64 /* 65 * Exported definitions unique to SPARC cpu support. 66 */ 67 68 #if defined(_KERNEL_OPT) 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #endif 72 73 #include <machine/psl.h> 74 #include <machine/reg.h> 75 #include <machine/intr.h> 76 #include <machine/cpuset.h> 77 #include <sparc64/sparc64/intreg.h> 78 79 #include <sys/sched.h> 80 /* 81 * The cpu_info structure is part of a 64KB structure mapped both the kernel 82 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 83 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 84 * processor. Other processors can access that through an additional mapping 85 * in the kernel pmap. 86 * 87 * The 64KB page contains: 88 * 89 * cpu_info 90 * interrupt stack (all remaining space) 91 * idle PCB 92 * idle stack (STACKSPACE - sizeof(PCB)) 93 * 32KB TSB 94 */ 95 96 struct cpu_info { 97 98 /* 99 * SPARC cpu_info structures live at two VAs: one global 100 * VA (so each CPU can access any other CPU's cpu_info) 101 * and an alias VA CPUINFO_VA which is the same on each 102 * CPU and maps to that CPU's cpu_info. Since the alias 103 * CPUINFO_VA is how we locate our cpu_info, we have to 104 * self-reference the global VA so that we can return it 105 * in the curcpu() macro. 106 */ 107 struct cpu_info * __volatile ci_self; 108 109 /* Most important fields first */ 110 struct lwp *ci_curlwp; 111 struct pcb *ci_cpcb; 112 struct cpu_info *ci_next; 113 114 struct lwp *ci_fplwp; 115 int ci_number; 116 int ci_upaid; 117 int ci_cpuid; 118 struct schedstate_percpu ci_schedstate; 119 120 /* 121 * Variables used by cc_microtime(). 122 */ 123 struct timeval ci_cc_time; 124 int64_t ci_cc_cc; 125 int64_t ci_cc_ms_delta; 126 int64_t ci_cc_denom; 127 128 /* DEBUG/DIAGNOSTIC stuff */ 129 u_long ci_spin_locks; 130 u_long ci_simple_locks; 131 132 /* Spinning up the CPU */ 133 void (*ci_spinup) __P((void)); 134 void *ci_initstack; 135 paddr_t ci_paddr; 136 137 /* CPU PROM information. */ 138 u_int ci_node; 139 140 int ci_flags; 141 int ci_want_ast; 142 int ci_want_resched; 143 144 void *ci_eintstack; 145 struct pcb *ci_idle_u; 146 }; 147 148 #define CPUF_PRIMARY 1 149 150 /* 151 * CPU boot arguments. Used by secondary CPUs at the bootstrap time. 152 */ 153 struct cpu_bootargs { 154 u_int cb_node; /* PROM CPU node */ 155 __volatile int cb_flags; 156 157 vaddr_t cb_ktext; 158 paddr_t cb_ktextp; 159 vaddr_t cb_ektext; 160 161 vaddr_t cb_kdata; 162 paddr_t cb_kdatap; 163 vaddr_t cb_ekdata; 164 165 paddr_t cb_cpuinfo; 166 167 void *cb_initstack; 168 }; 169 170 extern struct cpu_bootargs *cpu_args; 171 172 extern int ncpus; 173 extern struct cpu_info *cpus; 174 175 #define curcpu() (((struct cpu_info *)CPUINFO_VA)->ci_self) 176 #define cpu_number() (curcpu()->ci_number) 177 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 178 179 #define CPU_INFO_ITERATOR int 180 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpus; ci != NULL; \ 181 ci = ci->ci_next 182 183 #define curlwp curcpu()->ci_curlwp 184 #define fplwp curcpu()->ci_fplwp 185 #define curpcb curcpu()->ci_cpcb 186 187 #define want_ast curcpu()->ci_want_ast 188 #define want_resched curcpu()->ci_want_resched 189 190 /* 191 * definitions of cpu-dependent requirements 192 * referenced in generic code 193 */ 194 #define cpu_swapin(p) /* nothing */ 195 #define cpu_swapout(p) /* nothing */ 196 #define cpu_wait(p) /* nothing */ 197 198 /* This really should be somewhere else. */ 199 #define cpu_proc_fork(p1, p2) /* nothing */ 200 201 #if defined(MULTIPROCESSOR) 202 void cpu_mp_startup __P((void)); 203 void cpu_boot_secondary_processors __P((void)); 204 #endif 205 206 /* 207 * definitions for MI microtime(). 208 */ 209 extern struct timeval cc_microset_time; 210 #define microtime(tv) cc_microtime(tv) 211 void cc_microtime __P((struct timeval *)); 212 void cc_microset __P((struct cpu_info *)); 213 214 extern uint64_t cpu_clockrate[]; 215 216 /* 217 * Arguments to hardclock, softclock and gatherstats encapsulate the 218 * previous machine state in an opaque clockframe. The ipl is here 219 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 220 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 221 */ 222 extern int intstack[]; 223 extern int eintstack[]; 224 struct clockframe { 225 struct trapframe64 t; 226 }; 227 228 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 229 /* 230 * XXX Disable CLKF_BASEPRI() for now. If we use a counter-timer for 231 * the clock, the interrupt remains blocked until the interrupt handler 232 * returns and we write to the clear interrupt register. If we use 233 * %tick for the clock, we could get multiple interrupts, but the 234 * currently enabled INTR_INTERLOCK will prevent the interrupt from being 235 * posted twice anyway. 236 * 237 * Switching to %tick for all machines and disabling INTR_INTERLOCK 238 * in locore.s would allow us to take advantage of CLKF_BASEPRI(). 239 */ 240 #if 0 241 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 242 #else 243 #define CLKF_BASEPRI(framep) (0) 244 #endif 245 #define CLKF_PC(framep) ((framep)->t.tf_pc) 246 /* Since some files in sys/kern do not know BIAS, I'm using 0x7ff here */ 247 #define CLKF_INTR(framep) \ 248 ((!CLKF_USERMODE(framep))&& \ 249 (((framep)->t.tf_out[6] & 1 ) ? \ 250 (((vaddr_t)(framep)->t.tf_out[6] < \ 251 (vaddr_t)EINTSTACK-0x7ff) && \ 252 ((vaddr_t)(framep)->t.tf_out[6] > \ 253 (vaddr_t)INTSTACK-0x7ff)) : \ 254 (((vaddr_t)(framep)->t.tf_out[6] < \ 255 (vaddr_t)EINTSTACK) && \ 256 ((vaddr_t)(framep)->t.tf_out[6] > \ 257 (vaddr_t)INTSTACK)))) 258 259 260 extern struct intrhand soft01intr, soft01net, soft01clock; 261 262 void setsoftint __P((void)); 263 void setsoftnet __P((void)); 264 265 /* 266 * Preempt the current process if in interrupt from user mode, 267 * or after the current trap/syscall if in system mode. 268 */ 269 #define need_resched(ci) (want_resched = 1, want_ast = 1) 270 271 /* 272 * Give a profiling tick to the current process when the user profiling 273 * buffer pages are invalid. On the sparc, request an ast to send us 274 * through trap(), marking the proc as needing a profiling tick. 275 */ 276 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 277 278 /* 279 * Notify the current process (p) that it has a signal pending, 280 * process as soon as possible. 281 */ 282 #define signotify(p) (want_ast = 1) 283 284 /* 285 * Interrupt handler chains. Interrupt handlers should return 0 for 286 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 287 * handler into the list. The handler is called with its (single) 288 * argument, or with a pointer to a clockframe if ih_arg is NULL. 289 */ 290 struct intrhand { 291 int (*ih_fun) __P((void *)); 292 void *ih_arg; 293 short ih_number; /* interrupt number */ 294 /* the H/W provides */ 295 char ih_pil; /* interrupt priority */ 296 struct intrhand *ih_next; /* global list */ 297 struct intrhand *ih_pending; /* interrupt queued */ 298 volatile u_int64_t *ih_map; /* Interrupt map reg */ 299 volatile u_int64_t *ih_clr; /* clear interrupt reg */ 300 }; 301 extern struct intrhand *intrhand[]; 302 extern struct intrhand *intrlev[MAXINTNUM]; 303 304 void intr_establish __P((int level, struct intrhand *)); 305 306 /* cpu.c */ 307 paddr_t cpu_alloc __P((void)); 308 void cpu_start __P((int)); 309 310 #define mp_pause_cpus() sparc64_ipi_pause_cpus() 311 #define mp_resume_cpus() sparc64_ipi_resume_cpus() 312 313 /* disksubr.c */ 314 struct dkbad; 315 int isbad __P((struct dkbad *bt, int, int, int)); 316 /* machdep.c */ 317 int ldcontrolb __P((caddr_t)); 318 void dumpconf __P((void)); 319 caddr_t reserve_dumppages __P((caddr_t)); 320 /* clock.c */ 321 struct timeval; 322 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 323 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 324 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 325 /* locore.s */ 326 struct fpstate64; 327 void savefpstate __P((struct fpstate64 *)); 328 void loadfpstate __P((struct fpstate64 *)); 329 u_int64_t probeget __P((paddr_t, int, int)); 330 int probeset __P((paddr_t, int, int, u_int64_t)); 331 332 #define write_all_windows() __asm __volatile("flushw" : : ) 333 #define write_user_windows() __asm __volatile("flushw" : : ) 334 335 void proc_trampoline __P((void)); 336 struct pcb; 337 void snapshot __P((struct pcb *)); 338 struct frame *getfp __P((void)); 339 int xldcontrolb __P((caddr_t, struct pcb *)); 340 void copywords __P((const void *, void *, size_t)); 341 void qcopy __P((const void *, void *, size_t)); 342 void qzero __P((void *, size_t)); 343 void switchtoctx __P((int)); 344 /* locore2.c */ 345 void remrq __P((struct proc *)); 346 /* trap.c */ 347 void kill_user_windows __P((struct lwp *)); 348 int rwindow_save __P((struct lwp *)); 349 /* cons.c */ 350 int cnrom __P((void)); 351 /* zs.c */ 352 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 353 #ifdef KGDB 354 void zs_kgdb_init __P((void)); 355 #endif 356 /* fb.c */ 357 void fb_unblank __P((void)); 358 /* kgdb_stub.c */ 359 #ifdef KGDB 360 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 361 void kgdb_connect __P((int)); 362 void kgdb_panic __P((void)); 363 #endif 364 /* emul.c */ 365 int fixalign __P((struct lwp *, struct trapframe64 *)); 366 int emulinstr __P((vaddr_t, struct trapframe64 *)); 367 368 /* 369 * 370 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 371 * of the trap vector table. The next eight bits are supplied by the 372 * hardware when the trap occurs, and the bottom four bits are always 373 * zero (so that we can shove up to 16 bytes of executable code---exactly 374 * four instructions---into each trap vector). 375 * 376 * The hardware allocates half the trap vectors to hardware and half to 377 * software. 378 * 379 * Traps have priorities assigned (lower number => higher priority). 380 */ 381 382 struct trapvec { 383 int tv_instr[8]; /* the eight instructions */ 384 }; 385 extern struct trapvec *trapbase; /* the 256 vectors */ 386 387 #endif /* _KERNEL */ 388 #endif /* _CPU_H_ */ 389