1 /* $NetBSD: cpu.h,v 1.47 2005/06/16 04:17:50 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #define CTL_MACHDEP_NAMES { \ 56 { 0, 0 }, \ 57 { "booted_kernel", CTLTYPE_STRING }, \ 58 { "booted_device", CTLTYPE_STRING }, \ 59 { "boot_args", CTLTYPE_STRING }, \ 60 { "cpu_arch", CTLTYPE_INT }, \ 61 } 62 63 #ifdef _KERNEL 64 /* 65 * Exported definitions unique to SPARC cpu support. 66 */ 67 68 #if defined(_KERNEL_OPT) 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #endif 72 73 #include <machine/psl.h> 74 #include <machine/reg.h> 75 #include <machine/intr.h> 76 #include <machine/cpuset.h> 77 #include <sparc64/sparc64/intreg.h> 78 79 #include <sys/cpu_data.h> 80 #include <sys/cc_microtime.h> 81 /* 82 * The cpu_info structure is part of a 64KB structure mapped both the kernel 83 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 84 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 85 * processor. Other processors can access that through an additional mapping 86 * in the kernel pmap. 87 * 88 * The 64KB page contains: 89 * 90 * cpu_info 91 * interrupt stack (all remaining space) 92 * idle PCB 93 * idle stack (STACKSPACE - sizeof(PCB)) 94 * 32KB TSB 95 */ 96 97 struct cpu_info { 98 99 /* 100 * SPARC cpu_info structures live at two VAs: one global 101 * VA (so each CPU can access any other CPU's cpu_info) 102 * and an alias VA CPUINFO_VA which is the same on each 103 * CPU and maps to that CPU's cpu_info. Since the alias 104 * CPUINFO_VA is how we locate our cpu_info, we have to 105 * self-reference the global VA so that we can return it 106 * in the curcpu() macro. 107 */ 108 struct cpu_info * __volatile ci_self; 109 110 /* Most important fields first */ 111 struct lwp *ci_curlwp; 112 struct cpu_data ci_data; /* MI per-cpu data */ 113 struct pcb *ci_cpcb; 114 struct cpu_info *ci_next; 115 116 struct lwp *ci_fplwp; 117 int ci_number; 118 int ci_upaid; 119 int ci_cpuid; 120 121 /* 122 * Variables used by cc_microtime(). 123 */ 124 struct cc_microtime_state ci_cc; 125 126 /* Spinning up the CPU */ 127 void (*ci_spinup) __P((void)); 128 void *ci_initstack; 129 paddr_t ci_paddr; 130 131 /* CPU PROM information. */ 132 u_int ci_node; 133 134 int ci_flags; 135 int ci_want_ast; 136 int ci_want_resched; 137 138 void *ci_eintstack; 139 struct pcb *ci_idle_u; 140 }; 141 142 #define CPUF_PRIMARY 1 143 144 /* 145 * CPU boot arguments. Used by secondary CPUs at the bootstrap time. 146 */ 147 struct cpu_bootargs { 148 u_int cb_node; /* PROM CPU node */ 149 __volatile int cb_flags; 150 151 vaddr_t cb_ktext; 152 paddr_t cb_ktextp; 153 vaddr_t cb_ektext; 154 155 vaddr_t cb_kdata; 156 paddr_t cb_kdatap; 157 vaddr_t cb_ekdata; 158 159 paddr_t cb_cpuinfo; 160 161 void *cb_initstack; 162 }; 163 164 extern struct cpu_bootargs *cpu_args; 165 166 extern int sparc_ncpus; 167 extern struct cpu_info *cpus; 168 169 #define curcpu() (((struct cpu_info *)CPUINFO_VA)->ci_self) 170 #define cpu_number() (curcpu()->ci_number) 171 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 172 173 #define CPU_INFO_ITERATOR int 174 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpus; ci != NULL; \ 175 ci = ci->ci_next 176 177 #define curlwp curcpu()->ci_curlwp 178 #define fplwp curcpu()->ci_fplwp 179 #define curpcb curcpu()->ci_cpcb 180 181 #define want_ast curcpu()->ci_want_ast 182 #define want_resched curcpu()->ci_want_resched 183 184 /* 185 * definitions of cpu-dependent requirements 186 * referenced in generic code 187 */ 188 #define cpu_swapin(p) /* nothing */ 189 #define cpu_swapout(p) /* nothing */ 190 #define cpu_wait(p) /* nothing */ 191 192 /* This really should be somewhere else. */ 193 #define cpu_proc_fork(p1, p2) /* nothing */ 194 195 #if defined(MULTIPROCESSOR) 196 void cpu_mp_startup __P((void)); 197 void cpu_boot_secondary_processors __P((void)); 198 #endif 199 200 /* 201 * definitions for MI microtime(). 202 */ 203 #define microtime(tv) cc_microtime(tv) 204 205 extern uint64_t cpu_clockrate[]; 206 207 /* 208 * Arguments to hardclock, softclock and gatherstats encapsulate the 209 * previous machine state in an opaque clockframe. The ipl is here 210 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 211 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 212 */ 213 extern int intstack[]; 214 extern int eintstack[]; 215 struct clockframe { 216 struct trapframe64 t; 217 }; 218 219 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 220 /* 221 * XXX Disable CLKF_BASEPRI() for now. If we use a counter-timer for 222 * the clock, the interrupt remains blocked until the interrupt handler 223 * returns and we write to the clear interrupt register. If we use 224 * %tick for the clock, we could get multiple interrupts, but the 225 * currently enabled INTR_INTERLOCK will prevent the interrupt from being 226 * posted twice anyway. 227 * 228 * Switching to %tick for all machines and disabling INTR_INTERLOCK 229 * in locore.s would allow us to take advantage of CLKF_BASEPRI(). 230 */ 231 #if 0 232 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 233 #else 234 #define CLKF_BASEPRI(framep) (0) 235 #endif 236 #define CLKF_PC(framep) ((framep)->t.tf_pc) 237 /* Since some files in sys/kern do not know BIAS, I'm using 0x7ff here */ 238 #define CLKF_INTR(framep) \ 239 ((!CLKF_USERMODE(framep))&& \ 240 (((framep)->t.tf_out[6] & 1 ) ? \ 241 (((vaddr_t)(framep)->t.tf_out[6] < \ 242 (vaddr_t)EINTSTACK-0x7ff) && \ 243 ((vaddr_t)(framep)->t.tf_out[6] > \ 244 (vaddr_t)INTSTACK-0x7ff)) : \ 245 (((vaddr_t)(framep)->t.tf_out[6] < \ 246 (vaddr_t)EINTSTACK) && \ 247 ((vaddr_t)(framep)->t.tf_out[6] > \ 248 (vaddr_t)INTSTACK)))) 249 250 251 extern struct intrhand soft01intr, soft01net, soft01clock; 252 253 void setsoftint __P((void)); 254 void setsoftnet __P((void)); 255 256 /* 257 * Preempt the current process if in interrupt from user mode, 258 * or after the current trap/syscall if in system mode. 259 */ 260 #define need_resched(ci) (want_resched = 1, want_ast = 1) 261 262 /* 263 * Give a profiling tick to the current process when the user profiling 264 * buffer pages are invalid. On the sparc, request an ast to send us 265 * through trap(), marking the proc as needing a profiling tick. 266 */ 267 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 268 269 /* 270 * Notify the current process (p) that it has a signal pending, 271 * process as soon as possible. 272 */ 273 #define signotify(p) (want_ast = 1) 274 275 /* 276 * Interrupt handler chains. Interrupt handlers should return 0 for 277 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 278 * handler into the list. The handler is called with its (single) 279 * argument, or with a pointer to a clockframe if ih_arg is NULL. 280 */ 281 struct intrhand { 282 int (*ih_fun) __P((void *)); 283 void *ih_arg; 284 short ih_number; /* interrupt number */ 285 /* the H/W provides */ 286 char ih_pil; /* interrupt priority */ 287 struct intrhand *ih_next; /* global list */ 288 struct intrhand *ih_pending; /* interrupt queued */ 289 volatile u_int64_t *ih_map; /* Interrupt map reg */ 290 volatile u_int64_t *ih_clr; /* clear interrupt reg */ 291 }; 292 extern struct intrhand *intrhand[]; 293 extern struct intrhand *intrlev[MAXINTNUM]; 294 295 void intr_establish __P((int level, struct intrhand *)); 296 297 /* cpu.c */ 298 paddr_t cpu_alloc __P((void)); 299 void cpu_start __P((int)); 300 301 #define mp_pause_cpus() sparc64_ipi_pause_cpus() 302 #define mp_resume_cpus() sparc64_ipi_resume_cpus() 303 304 /* disksubr.c */ 305 struct dkbad; 306 int isbad __P((struct dkbad *bt, int, int, int)); 307 /* machdep.c */ 308 int ldcontrolb __P((caddr_t)); 309 void dumpconf __P((void)); 310 caddr_t reserve_dumppages __P((caddr_t)); 311 /* clock.c */ 312 struct timeval; 313 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 314 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 315 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 316 /* locore.s */ 317 struct fpstate64; 318 void savefpstate __P((struct fpstate64 *)); 319 void loadfpstate __P((struct fpstate64 *)); 320 u_int64_t probeget __P((paddr_t, int, int)); 321 int probeset __P((paddr_t, int, int, u_int64_t)); 322 323 #define write_all_windows() __asm __volatile("flushw" : : ) 324 #define write_user_windows() __asm __volatile("flushw" : : ) 325 326 void proc_trampoline __P((void)); 327 struct pcb; 328 void snapshot __P((struct pcb *)); 329 struct frame *getfp __P((void)); 330 int xldcontrolb __P((caddr_t, struct pcb *)); 331 void copywords __P((const void *, void *, size_t)); 332 void qcopy __P((const void *, void *, size_t)); 333 void qzero __P((void *, size_t)); 334 void switchtoctx __P((int)); 335 /* locore2.c */ 336 void remrq __P((struct proc *)); 337 /* trap.c */ 338 void kill_user_windows __P((struct lwp *)); 339 int rwindow_save __P((struct lwp *)); 340 /* cons.c */ 341 int cnrom __P((void)); 342 /* zs.c */ 343 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 344 #ifdef KGDB 345 void zs_kgdb_init __P((void)); 346 #endif 347 /* fb.c */ 348 void fb_unblank __P((void)); 349 /* kgdb_stub.c */ 350 #ifdef KGDB 351 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 352 void kgdb_connect __P((int)); 353 void kgdb_panic __P((void)); 354 #endif 355 /* emul.c */ 356 int fixalign __P((struct lwp *, struct trapframe64 *)); 357 int emulinstr __P((vaddr_t, struct trapframe64 *)); 358 359 /* 360 * 361 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 362 * of the trap vector table. The next eight bits are supplied by the 363 * hardware when the trap occurs, and the bottom four bits are always 364 * zero (so that we can shove up to 16 bytes of executable code---exactly 365 * four instructions---into each trap vector). 366 * 367 * The hardware allocates half the trap vectors to hardware and half to 368 * software. 369 * 370 * Traps have priorities assigned (lower number => higher priority). 371 */ 372 373 struct trapvec { 374 int tv_instr[8]; /* the eight instructions */ 375 }; 376 extern struct trapvec *trapbase; /* the 256 vectors */ 377 378 #endif /* _KERNEL */ 379 #endif /* _CPU_H_ */ 380