1 /* $NetBSD: cpu.h,v 1.111 2014/06/08 17:33:24 palle Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_VIS 5 /* 0 - no VIS, 1 - VIS 1.0, etc. */ 54 #define CPU_MAXID 6 /* number of valid machdep ids */ 55 56 #if defined(_KERNEL) || defined(_KMEMUSER) 57 /* 58 * Exported definitions unique to SPARC cpu support. 59 */ 60 61 #if defined(_KERNEL_OPT) 62 #include "opt_multiprocessor.h" 63 #include "opt_lockdebug.h" 64 #endif 65 66 #include <machine/psl.h> 67 #include <machine/reg.h> 68 #include <machine/pte.h> 69 #include <machine/intr.h> 70 #if defined(_KERNEL) 71 #include <machine/cpuset.h> 72 #include <sparc64/sparc64/intreg.h> 73 #endif 74 75 #include <sys/cpu_data.h> 76 #include <sys/evcnt.h> 77 78 /* 79 * The cpu_info structure is part of a 64KB structure mapped both the kernel 80 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 81 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 82 * processor. Other processors can access that through an additional mapping 83 * in the kernel pmap. 84 * 85 * The 64KB page contains: 86 * 87 * cpu_info 88 * interrupt stack (all remaining space) 89 * idle PCB 90 * idle stack (STACKSPACE - sizeof(PCB)) 91 * 32KB TSB 92 */ 93 94 struct cpu_info { 95 struct cpu_data ci_data; /* MI per-cpu data */ 96 97 98 /* 99 * SPARC cpu_info structures live at two VAs: one global 100 * VA (so each CPU can access any other CPU's cpu_info) 101 * and an alias VA CPUINFO_VA which is the same on each 102 * CPU and maps to that CPU's cpu_info. Since the alias 103 * CPUINFO_VA is how we locate our cpu_info, we have to 104 * self-reference the global VA so that we can return it 105 * in the curcpu() macro. 106 */ 107 struct cpu_info * volatile ci_self; 108 109 /* Most important fields first */ 110 struct lwp *ci_curlwp; 111 struct pcb *ci_cpcb; 112 struct cpu_info *ci_next; 113 114 struct lwp *ci_fplwp; 115 116 void *ci_eintstack; 117 118 int ci_mtx_count; 119 int ci_mtx_oldspl; 120 121 /* Spinning up the CPU */ 122 void (*ci_spinup)(void); 123 paddr_t ci_paddr; 124 125 int ci_cpuid; 126 127 /* CPU PROM information. */ 128 u_int ci_node; 129 130 /* %tick and cpu frequency information */ 131 u_long ci_tick_increment; 132 uint64_t ci_cpu_clockrate[2]; /* %tick */ 133 uint64_t ci_system_clockrate[2]; /* %stick */ 134 135 /* Interrupts */ 136 struct intrhand *ci_intrpending[16]; 137 struct intrhand *ci_tick_ih; 138 139 /* Event counters */ 140 struct evcnt ci_tick_evcnt; 141 142 /* This could be under MULTIPROCESSOR, but there's no good reason */ 143 struct evcnt ci_ipi_evcnt[IPI_EVCNT_NUM]; 144 145 int ci_flags; 146 int ci_want_ast; 147 int ci_want_resched; 148 int ci_idepth; 149 150 /* 151 * A context is simply a small number that differentiates multiple mappings 152 * of the same address. Contexts on the spitfire are 13 bits, but could 153 * be as large as 17 bits. 154 * 155 * Each context is either free or attached to a pmap. 156 * 157 * The context table is an array of pointers to psegs. Just dereference 158 * the right pointer and you get to the pmap segment tables. These are 159 * physical addresses, of course. 160 * 161 * ci_ctx_lock protects this CPUs context allocation/free. 162 * These are all allocated almost with in the same cacheline. 163 */ 164 kmutex_t ci_ctx_lock; 165 int ci_pmap_next_ctx; 166 int ci_numctx; 167 paddr_t *ci_ctxbusy; 168 LIST_HEAD(, pmap) ci_pmap_ctxlist; 169 170 /* 171 * The TSBs are per cpu too (since MMU context differs between 172 * cpus). These are just caches for the TLBs. 173 */ 174 pte_t *ci_tsb_dmmu; 175 pte_t *ci_tsb_immu; 176 177 /* MMU Fault Status Area (sun4v). 178 * Will be initialized to the physical address of the bottom of 179 * the interrupt stack. 180 */ 181 paddr_t ci_mmfsa; 182 183 /* 184 * sun4v mondo control fields 185 */ 186 paddr_t ci_cpumq; /* cpu mondo queue address */ 187 paddr_t ci_devmq; /* device mondo queue address */ 188 paddr_t ci_cpuset; /* mondo recipient address */ 189 paddr_t ci_mondo; /* mondo message address */ 190 191 /* probe fault in PCI config space reads */ 192 bool ci_pci_probe; 193 bool ci_pci_fault; 194 195 volatile void *ci_ddb_regs; /* DDB regs */ 196 }; 197 198 #endif /* _KERNEL || _KMEMUSER */ 199 200 #ifdef _KERNEL 201 202 #define CPUF_PRIMARY 1 203 204 /* 205 * CPU boot arguments. Used by secondary CPUs at the bootstrap time. 206 */ 207 struct cpu_bootargs { 208 u_int cb_node; /* PROM CPU node */ 209 volatile int cb_flags; 210 211 vaddr_t cb_ktext; 212 paddr_t cb_ktextp; 213 vaddr_t cb_ektext; 214 215 vaddr_t cb_kdata; 216 paddr_t cb_kdatap; 217 vaddr_t cb_ekdata; 218 219 paddr_t cb_cpuinfo; 220 }; 221 222 extern struct cpu_bootargs *cpu_args; 223 224 #if defined(MULTIPROCESSOR) 225 extern int sparc_ncpus; 226 #else 227 #define sparc_ncpus 1 228 #endif 229 230 extern struct cpu_info *cpus; 231 extern struct pool_cache *fpstate_cache; 232 233 #define curcpu() (((struct cpu_info *)CPUINFO_VA)->ci_self) 234 #define cpu_number() (curcpu()->ci_index) 235 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 236 237 #define CPU_INFO_ITERATOR int __unused 238 #define CPU_INFO_FOREACH(cii, ci) ci = cpus; ci != NULL; ci = ci->ci_next 239 240 #define curlwp curcpu()->ci_curlwp 241 #define fplwp curcpu()->ci_fplwp 242 #define curpcb curcpu()->ci_cpcb 243 244 #define want_ast curcpu()->ci_want_ast 245 #define want_resched curcpu()->ci_want_resched 246 247 /* 248 * definitions of cpu-dependent requirements 249 * referenced in generic code 250 */ 251 #define cpu_wait(p) /* nothing */ 252 void cpu_proc_fork(struct proc *, struct proc *); 253 254 /* run on the cpu itself */ 255 void cpu_pmap_init(struct cpu_info *); 256 /* run upfront to prepare the cpu_info */ 257 void cpu_pmap_prepare(struct cpu_info *, bool); 258 259 #if defined(MULTIPROCESSOR) 260 extern vaddr_t cpu_spinup_trampoline; 261 262 extern char *mp_tramp_code; 263 extern u_long mp_tramp_code_len; 264 extern u_long mp_tramp_tlb_slots; 265 extern u_long mp_tramp_func; 266 extern u_long mp_tramp_ci; 267 268 void cpu_hatch(void); 269 void cpu_boot_secondary_processors(void); 270 271 /* 272 * Call a function on other cpus: 273 * multicast - send to everyone in the sparc64_cpuset_t 274 * broadcast - send to to all cpus but ourselves 275 * send - send to just this cpu 276 * The called function do not follow the C ABI, so need to be coded in 277 * assembler. 278 */ 279 typedef void (* ipifunc_t)(void *, void *); 280 281 void sparc64_multicast_ipi(sparc64_cpuset_t, ipifunc_t, uint64_t, uint64_t); 282 void sparc64_broadcast_ipi(ipifunc_t, uint64_t, uint64_t); 283 void sparc64_send_ipi(int, ipifunc_t, uint64_t, uint64_t); 284 285 /* 286 * Call an arbitrary C function on another cpu (or all others but ourself) 287 */ 288 typedef void (*ipi_c_call_func_t)(void*); 289 void sparc64_generic_xcall(struct cpu_info*, ipi_c_call_func_t, void*); 290 291 #endif 292 293 /* Provide %pc of a lwp */ 294 #define LWP_PC(l) ((l)->l_md.md_tf->tf_pc) 295 296 /* 297 * Arguments to hardclock, softclock and gatherstats encapsulate the 298 * previous machine state in an opaque clockframe. The ipl is here 299 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 300 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 301 */ 302 struct clockframe { 303 struct trapframe64 t; 304 }; 305 306 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 307 #define CLKF_PC(framep) ((framep)->t.tf_pc) 308 /* Since some files in sys/kern do not know BIAS, I'm using 0x7ff here */ 309 #define CLKF_INTR(framep) \ 310 ((!CLKF_USERMODE(framep))&& \ 311 (((framep)->t.tf_out[6] & 1 ) ? \ 312 (((vaddr_t)(framep)->t.tf_out[6] < \ 313 (vaddr_t)EINTSTACK-0x7ff) && \ 314 ((vaddr_t)(framep)->t.tf_out[6] > \ 315 (vaddr_t)INTSTACK-0x7ff)) : \ 316 (((vaddr_t)(framep)->t.tf_out[6] < \ 317 (vaddr_t)EINTSTACK) && \ 318 ((vaddr_t)(framep)->t.tf_out[6] > \ 319 (vaddr_t)INTSTACK)))) 320 321 /* 322 * Give a profiling tick to the current process when the user profiling 323 * buffer pages are invalid. On the sparc, request an ast to send us 324 * through trap(), marking the proc as needing a profiling tick. 325 */ 326 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, want_ast = 1) 327 328 /* 329 * Notify an LWP that it has a signal pending, process as soon as possible. 330 */ 331 void cpu_signotify(struct lwp *); 332 333 /* 334 * Interrupt handler chains. Interrupt handlers should return 0 for 335 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 336 * handler into the list. The handler is called with its (single) 337 * argument, or with a pointer to a clockframe if ih_arg is NULL. 338 */ 339 struct intrhand { 340 int (*ih_fun)(void *); 341 void *ih_arg; 342 /* if we have to take the biglock, we interpose a wrapper 343 * and need to save the original function and arg */ 344 int (*ih_realfun)(void *); 345 void *ih_realarg; 346 short ih_number; /* interrupt number */ 347 /* the H/W provides */ 348 char ih_pil; /* interrupt priority */ 349 struct intrhand *ih_next; /* global list */ 350 struct intrhand *ih_pending; /* interrupt queued */ 351 volatile uint64_t *ih_map; /* Interrupt map reg */ 352 volatile uint64_t *ih_clr; /* clear interrupt reg */ 353 struct evcnt ih_cnt; /* counter for vmstat */ 354 uint32_t ih_ivec; 355 char ih_name[32]; /* name for the above */ 356 }; 357 extern struct intrhand *intrhand[]; 358 extern struct intrhand *intrlev[MAXINTNUM]; 359 360 void intr_establish(int level, bool mpsafe, struct intrhand *); 361 void *sparc_softintr_establish(int, int (*)(void *), void *); 362 void sparc_softintr_schedule(void *); 363 void sparc_softintr_disestablish(void *); 364 365 /* cpu.c */ 366 int cpu_myid(void); 367 368 /* disksubr.c */ 369 struct dkbad; 370 int isbad(struct dkbad *bt, int, int, int); 371 /* machdep.c */ 372 void * reserve_dumppages(void *); 373 /* clock.c */ 374 struct timeval; 375 int tickintr(void *); /* level 10/14 (tick) interrupt code */ 376 int stickintr(void *); /* system tick interrupt code */ 377 int stick2eintr(void *); /* system tick interrupt code */ 378 int clockintr(void *); /* level 10 (clock) interrupt code */ 379 int statintr(void *); /* level 14 (statclock) interrupt code */ 380 int schedintr(void *); /* level 10 (schedclock) interrupt code */ 381 void tickintr_establish(int, int (*)(void *)); 382 void stickintr_establish(int, int (*)(void *)); 383 void stick2eintr_establish(int, int (*)(void *)); 384 385 /* locore.s */ 386 struct fpstate64; 387 void savefpstate(struct fpstate64 *); 388 void loadfpstate(struct fpstate64 *); 389 void clearfpstate(void); 390 uint64_t probeget(paddr_t, int, int); 391 int probeset(paddr_t, int, int, uint64_t); 392 void setcputyp(int); 393 394 #define write_all_windows() __asm volatile("flushw" : : ) 395 #define write_user_windows() __asm volatile("flushw" : : ) 396 397 struct pcb; 398 void snapshot(struct pcb *); 399 struct frame *getfp(void); 400 void switchtoctx_us(int); 401 void switchtoctx_usiii(int); 402 void next_tick(long); 403 void next_stick(long); 404 /* trap.c */ 405 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 406 int rwindow_save(struct lwp *); 407 /* cons.c */ 408 int cnrom(void); 409 /* zs.c */ 410 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 411 /* fb.c */ 412 void fb_unblank(void); 413 /* kgdb_stub.c */ 414 #ifdef KGDB 415 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 416 void kgdb_connect(int); 417 void kgdb_panic(void); 418 #endif 419 /* emul.c */ 420 int fixalign(struct lwp *, struct trapframe64 *); 421 int emulinstr(vaddr_t, struct trapframe64 *); 422 423 #else /* _KERNEL */ 424 425 /* 426 * XXX: provide some definitions for crash(8), probably can share 427 */ 428 #if defined(_KMEMUSER) 429 #define curcpu() (((struct cpu_info *)CPUINFO_VA)->ci_self) 430 #define curlwp curcpu()->ci_curlwp 431 #endif 432 433 #endif /* _KERNEL */ 434 #endif /* _CPU_H_ */ 435