1 /* $NetBSD: zs.c,v 1.14 2000/03/06 21:36:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/autoconf.h> 62 #include <machine/openfirm.h> 63 #include <machine/bsd_openprom.h> 64 #include <machine/conf.h> 65 #include <machine/cpu.h> 66 #include <machine/eeprom.h> 67 #include <machine/psl.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include <sparc64/sparc64/vaddrs.h> 74 #include <sparc64/sparc64/auxreg.h> 75 #include <sparc64/dev/cons.h> 76 77 #include "kbd.h" /* NKBD */ 78 #include "zs.h" /* NZS */ 79 80 /* Make life easier for the initialized arrays here. */ 81 #if NZS < 3 82 #undef NZS 83 #define NZS 3 84 #endif 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 int zs_major = 12; 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 /* 100 * Select software interrupt bit based on TTY ipl. 101 */ 102 #if PIL_TTY == 1 103 # define IE_ZSSOFT IE_L1 104 #elif PIL_TTY == 4 105 # define IE_ZSSOFT IE_L4 106 #elif PIL_TTY == 6 107 # define IE_ZSSOFT IE_L6 108 #else 109 # error "no suitable software interrupt bit" 110 #endif 111 112 #define ZS_DELAY() 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 volatile u_char zc_data; /* data */ 119 u_char zc_xxx1; 120 }; 121 struct zsdevice { 122 /* Yes, they are backwards. */ 123 struct zschan zs_chan_b; 124 struct zschan zs_chan_a; 125 }; 126 127 /* Saved PROM mappings */ 128 static struct zsdevice *zsaddr[NZS]; 129 130 /* Flags from cninit() */ 131 static int zs_hwflags[NZS][2]; 132 133 /* Default speed for each channel */ 134 static int zs_defspeed[NZS][2] = { 135 { 9600, /* ttya */ 136 9600 }, /* ttyb */ 137 { 1200, /* keyboard */ 138 1200 }, /* mouse */ 139 { 9600, /* ttyc */ 140 9600 }, /* ttyd */ 141 }; 142 143 static u_char zs_init_reg[16] = { 144 0, /* 0: CMD (reset, etc.) */ 145 0, /* 1: No interrupts yet. */ 146 0, /* 2: IVECT */ 147 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 148 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 149 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 150 0, /* 6: TXSYNC/SYNCLO */ 151 0, /* 7: RXSYNC/SYNCHI */ 152 0, /* 8: alias for data port */ 153 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 154 0, /*10: Misc. TX/RX control bits */ 155 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 156 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 157 0, /*13: BAUDHI (default=9600) */ 158 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 159 ZSWR15_BREAK_IE, 160 }; 161 162 struct zschan * 163 zs_get_chan_addr(zs_unit, channel) 164 int zs_unit, channel; 165 { 166 struct zsdevice *addr; 167 struct zschan *zc; 168 169 if (zs_unit >= NZS) 170 return (NULL); 171 addr = zsaddr[zs_unit]; 172 #ifdef DEBUG 173 if (addr == NULL) { 174 db_printf("zs_get_chan_addr(): unit %d channel %d not found\n", zs_unit, channel); 175 Debugger(); 176 } 177 #endif 178 if (addr == NULL) 179 return (NULL); 180 if (channel == 0) { 181 zc = &addr->zs_chan_a; 182 } else { 183 zc = &addr->zs_chan_b; 184 } 185 return (zc); 186 } 187 188 189 /**************************************************************** 190 * Autoconfig 191 ****************************************************************/ 192 193 /* Definition of the driver for autoconfig. */ 194 static int zs_match_sbus __P((struct device *, struct cfdata *, void *)); 195 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 196 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 197 static void zs_attach_sbus __P((struct device *, struct device *, void *)); 198 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 199 static void zs_attach_obio __P((struct device *, struct device *, void *)); 200 201 static void zs_attach __P((struct zsc_softc *, int)); 202 static int zs_print __P((void *, const char *name)); 203 204 struct cfattach zs_ca = { 205 sizeof(struct zsc_softc), zs_match_sbus, zs_attach_sbus 206 }; 207 208 struct cfattach zs_mainbus_ca = { 209 sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus 210 }; 211 212 struct cfattach zs_obio_ca = { 213 sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio 214 }; 215 216 extern struct cfdriver zs_cd; 217 extern struct consdev consdev_kd; 218 extern struct consdev consdev_zs; 219 extern struct consdev *cn_hw; 220 extern int stdinnode; 221 extern int fbnode; 222 223 /* Interrupt handlers. */ 224 static int zshard __P((void *)); 225 static int zssoft __P((void *)); 226 static struct intrhand levelsoft = { zssoft }; 227 228 static int zs_get_speed __P((struct zs_chanstate *)); 229 230 231 /* 232 * Is the zs chip present? 233 */ 234 static int 235 zs_match_mainbus(parent, cf, aux) 236 struct device *parent; 237 struct cfdata *cf; 238 void *aux; 239 { 240 struct mainbus_attach_args *ma = aux; 241 242 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0) 243 return (0); 244 245 return (getpropint(ma->ma_node, "slave", -2) == cf->cf_unit); 246 } 247 248 static int 249 zs_match_sbus(parent, cf, aux) 250 struct device *parent; 251 struct cfdata *cf; 252 void *aux; 253 { 254 struct sbus_attach_args *sa = aux; 255 256 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 257 return (0); 258 259 return 1; 260 } 261 262 static int 263 zs_match_obio(parent, cf, aux) 264 struct device *parent; 265 struct cfdata *cf; 266 void *aux; 267 { 268 #ifdef SUN4U 269 return 0; 270 #else 271 union obio_attach_args *uoba = aux; 272 struct obio4_attach_args *oba; 273 274 if (uoba->uoba_isobio4 == 0) { 275 struct sbus_attach_args *sa = &uoba->uoba_sbus; 276 277 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 278 return (0); 279 280 return (getpropint(sa->sa_node, "slave", -2) == cf->cf_unit); 281 } 282 283 oba = &uoba->uoba_oba4; 284 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 285 1, 0, 0, NULL, NULL)); 286 #endif 287 } 288 289 static void 290 zs_attach_mainbus(parent, self, aux) 291 struct device *parent; 292 struct device *self; 293 void *aux; 294 { 295 #ifdef SUN4U 296 return; 297 #else 298 struct zsc_softc *zsc = (void *) self; 299 struct mainbus_attach_args *ma = aux; 300 int zs_unit = zsc->zsc_dev.dv_unit; 301 302 zsc->zsc_bustag = ma->ma_bustag; 303 zsc->zsc_dmatag = ma->ma_dmatag; 304 305 /* Use the mapping setup by the Sun PROM. */ 306 if (zsaddr[zs_unit] == NULL) 307 zsaddr[zs_unit] = findzs(zs_unit); 308 if ((void*)zsaddr[zs_unit] != (void*)(u_long)ma->ma_address[0]) 309 panic("zsattach_mainbus"); 310 zs_attach(zsc, ma->ma_pri); 311 #endif 312 } 313 314 315 static void 316 zs_attach_sbus(parent, self, aux) 317 struct device *parent; 318 struct device *self; 319 void *aux; 320 { 321 struct zsc_softc *zsc = (void *) self; 322 struct sbus_attach_args *sa = aux; 323 int zs_unit = zsc->zsc_dev.dv_unit; 324 struct consdev *cn = NULL; 325 326 zsc->zsc_bustag = sa->sa_bustag; 327 zsc->zsc_dmatag = sa->sa_dmatag; 328 329 /* Use the mapping setup by the Sun PROM. */ 330 if (zsaddr[zs_unit] == NULL) { 331 if (sa->sa_npromvaddrs) { 332 /* 333 * We're converting from a 32-bit pointer to a 64-bit 334 * pointer. Since the 32-bit entity is negative, but 335 * the kernel is still mapped into the lower 4GB 336 * range, this needs to be zero-extended. 337 * 338 * XXXXX If we map the kernel and devices into the 339 * high 4GB range, this needs to be changed to 340 * sign-extend the address. 341 */ 342 zsaddr[zs_unit] = 343 (struct zsdevice *) 344 (unsigned long)sa->sa_promvaddrs[0]; 345 } else { 346 bus_space_handle_t kvaddr; 347 348 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 349 sa->sa_offset, 350 sa->sa_size, 351 BUS_SPACE_MAP_LINEAR, 352 0, &kvaddr) != 0) { 353 printf("%s @ sbus: cannot map registers\n", 354 self->dv_xname); 355 return; 356 } 357 zsaddr[zs_unit] = (struct zsdevice *) 358 (long)kvaddr; 359 } 360 } 361 /* 362 * Check to see if we're the console. We presume the input comes from 363 * the same location as the output, although that may not be true. 364 * To support input from the serial line but output to a display we 365 * would need to generate some really weird consdev vectors. 366 */ 367 if (sa->sa_node == stdinnode) { 368 char buf[256]; 369 int chan = 0; 370 int len; 371 372 if ((len = OF_instance_to_path(sa->sa_node, buf, sizeof(buf))) > 0) { 373 /* With zs nodes, the last :a or :b selects the channel */ 374 if (buf[len] == 0) len--; 375 if (buf[len] == 'b') chan = 1; 376 /* But keyboards don't have a :a or :b */ 377 } 378 zs_hwflags[zs_unit][chan] = ZS_HWFLAG_CONSOLE; 379 zs_conschan = zs_get_chan_addr(zs_unit, chan); 380 if (OF_getproplen(sa->sa_node, "keyboard") >= 0) { 381 cn_hw = &consdev_zs; 382 cn = &consdev_kd; 383 } else { 384 cn = &consdev_zs; 385 } 386 } 387 zs_attach(zsc, sa->sa_pri); 388 if (cn) { 389 cn_tab = cn; 390 (*cn->cn_init)(cn); 391 #ifdef KGDB 392 zs_kgdb_init(); 393 #endif 394 } 395 } 396 397 static void 398 zs_attach_obio(parent, self, aux) 399 struct device *parent; 400 struct device *self; 401 void *aux; 402 { 403 #ifndef SUN4U 404 struct zsc_softc *zsc = (void *) self; 405 union obio_attach_args *uoba = aux; 406 int zs_unit = zsc->zsc_dev.dv_unit; 407 408 /* Use the mapping setup by the Sun PROM. */ 409 if (zsaddr[zs_unit] == NULL) 410 zsaddr[zs_unit] = findzs(zs_unit); 411 412 if (uoba->uoba_isobio4 == 0) { 413 struct sbus_attach_args *sa = &uoba->uoba_sbus; 414 zsc->zsc_bustag = sa->sa_bustag; 415 zsc->zsc_dmatag = sa->sa_dmatag; 416 zs_attach(zsc, sa->sa_pri); 417 } else { 418 struct obio4_attach_args *oba = &uoba->uoba_oba4; 419 zsc->zsc_bustag = oba->oba_bustag; 420 zsc->zsc_dmatag = oba->oba_dmatag; 421 zs_attach(zsc, oba->oba_pri); 422 } 423 #endif 424 } 425 /* 426 * Attach a found zs. 427 * 428 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 429 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 430 */ 431 static void 432 zs_attach(zsc, pri) 433 struct zsc_softc *zsc; 434 int pri; 435 { 436 struct zsc_attach_args zsc_args; 437 volatile struct zschan *zc; 438 struct zs_chanstate *cs; 439 int s, zs_unit, channel; 440 static int didintr, prevpri; 441 442 printf(" softpri %d\n", PIL_TTY); 443 444 /* 445 * Initialize software state for each channel. 446 */ 447 zs_unit = zsc->zsc_dev.dv_unit; 448 for (channel = 0; channel < 2; channel++) { 449 zsc_args.channel = channel; 450 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 451 cs = &zsc->zsc_cs_store[channel]; 452 zsc->zsc_cs[channel] = cs; 453 454 cs->cs_channel = channel; 455 cs->cs_private = NULL; 456 cs->cs_ops = &zsops_null; 457 cs->cs_brg_clk = PCLK / 16; 458 459 zc = zs_get_chan_addr(zs_unit, channel); 460 if (zs_hwflags[zs_unit][channel] == ZS_HWFLAG_CONSOLE) { 461 zs_conschan = (struct zschan *)zc; 462 } 463 cs->cs_reg_csr = &zc->zc_csr; 464 cs->cs_reg_data = &zc->zc_data; 465 466 bcopy(zs_init_reg, cs->cs_creg, 16); 467 bcopy(zs_init_reg, cs->cs_preg, 16); 468 469 /* XXX: Get these from the PROM properties! */ 470 /* XXX: See the mvme167 code. Better. */ 471 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 472 cs->cs_defspeed = zs_get_speed(cs); 473 else 474 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 475 cs->cs_defcflag = zs_def_cflag; 476 477 /* Make these correspond to cs_defcflag (-crtscts) */ 478 cs->cs_rr0_dcd = ZSRR0_DCD; 479 cs->cs_rr0_cts = 0; 480 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 481 cs->cs_wr5_rts = 0; 482 483 /* 484 * Clear the master interrupt enable. 485 * The INTENA is common to both channels, 486 * so just do it on the A channel. 487 */ 488 if (channel == 0) { 489 zs_write_reg(cs, 9, 0); 490 } 491 492 /* 493 * Look for a child driver for this channel. 494 * The child attach will setup the hardware. 495 */ 496 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 497 /* No sub-driver. Just reset it. */ 498 u_char reset = (channel == 0) ? 499 ZSWR9_A_RESET : ZSWR9_B_RESET; 500 s = splzs(); 501 zs_write_reg(cs, 9, reset); 502 splx(s); 503 } 504 } 505 506 /* 507 * Now safe to install interrupt handlers. Note the arguments 508 * to the interrupt handlers aren't used. Note, we only do this 509 * once since both SCCs interrupt at the same level and vector. 510 */ 511 if (!didintr) { 512 didintr = 1; 513 prevpri = pri; 514 bus_intr_establish(zsc->zsc_bustag, pri, 0, zshard, NULL); 515 intr_establish(PIL_TTY, &levelsoft); 516 } else if (pri != prevpri) 517 panic("broken zs interrupt scheme"); 518 519 evcnt_attach(&zsc->zsc_dev, "intr", &zsc->zsc_intrcnt); 520 521 /* 522 * Set the master interrupt enable and interrupt vector. 523 * (common to both channels, do it on A) 524 */ 525 cs = zsc->zsc_cs[0]; 526 s = splhigh(); 527 /* interrupt vector */ 528 zs_write_reg(cs, 2, zs_init_reg[2]); 529 /* master interrupt control (enable) */ 530 zs_write_reg(cs, 9, zs_init_reg[9]); 531 splx(s); 532 533 #if 0 534 /* 535 * XXX: L1A hack - We would like to be able to break into 536 * the debugger during the rest of autoconfiguration, so 537 * lower interrupts just enough to let zs interrupts in. 538 * This is done after both zs devices are attached. 539 */ 540 if (zs_unit == 1) { 541 printf("zs1: enabling zs interrupts\n"); 542 (void)splfd(); /* XXX: splzs - 1 */ 543 } 544 #endif 545 } 546 547 static int 548 zs_print(aux, name) 549 void *aux; 550 const char *name; 551 { 552 struct zsc_attach_args *args = aux; 553 554 if (name != NULL) 555 printf("%s: ", name); 556 557 if (args->channel != -1) 558 printf(" channel %d", args->channel); 559 560 return (UNCONF); 561 } 562 563 static volatile int zssoftpending; 564 565 /* 566 * Our ZS chips all share a common, autovectored interrupt, 567 * so we have to look at all of them on each interrupt. 568 */ 569 static int 570 zshard(arg) 571 void *arg; 572 { 573 register struct zsc_softc *zsc; 574 register int unit, rr3, rval, softreq; 575 576 rval = softreq = 0; 577 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 578 zsc = zs_cd.cd_devs[unit]; 579 if (zsc == NULL) 580 continue; 581 rr3 = zsc_intr_hard(zsc); 582 /* Count up the interrupts. */ 583 if (rr3) { 584 rval |= rr3; 585 zsc->zsc_intrcnt.ev_count++; 586 } 587 softreq |= zsc->zsc_cs[0]->cs_softreq; 588 softreq |= zsc->zsc_cs[1]->cs_softreq; 589 } 590 591 /* We are at splzs here, so no need to lock. */ 592 if (softreq && (zssoftpending == 0)) { 593 zssoftpending = IE_ZSSOFT; 594 #if defined(SUN4M) 595 if (CPU_ISSUN4M) 596 raise(0, PIL_TTY); 597 else 598 #endif 599 ienab_bis(IE_ZSSOFT); 600 } 601 return (rval); 602 } 603 604 /* 605 * Similar scheme as for zshard (look at all of them) 606 */ 607 static int 608 zssoft(arg) 609 void *arg; 610 { 611 register struct zsc_softc *zsc; 612 register int s, unit; 613 614 /* This is not the only ISR on this IPL. */ 615 if (zssoftpending == 0) 616 return (0); 617 618 /* 619 * The soft intr. bit will be set by zshard only if 620 * the variable zssoftpending is zero. The order of 621 * these next two statements prevents our clearing 622 * the soft intr bit just after zshard has set it. 623 */ 624 /* ienab_bic(IE_ZSSOFT); */ 625 zssoftpending = 0; 626 627 /* Make sure we call the tty layer at spltty. */ 628 s = spltty(); 629 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 630 zsc = zs_cd.cd_devs[unit]; 631 if (zsc == NULL) 632 continue; 633 (void)zsc_intr_soft(zsc); 634 #ifdef TTY_DEBUG 635 { 636 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 637 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 638 if (zst0->zst_overflows || zst1->zst_overflows ) { 639 struct trapframe *frame = (struct trapframe *)arg; 640 641 printf("zs silo overflow from %p\n", 642 (long)frame->tf_pc); 643 } 644 } 645 #endif 646 } 647 splx(s); 648 return (1); 649 } 650 651 652 /* 653 * Compute the current baud rate given a ZS channel. 654 */ 655 static int 656 zs_get_speed(cs) 657 struct zs_chanstate *cs; 658 { 659 int tconst; 660 661 tconst = zs_read_reg(cs, 12); 662 tconst |= zs_read_reg(cs, 13) << 8; 663 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 664 } 665 666 /* 667 * MD functions for setting the baud rate and control modes. 668 */ 669 int 670 zs_set_speed(cs, bps) 671 struct zs_chanstate *cs; 672 int bps; /* bits per second */ 673 { 674 int tconst, real_bps; 675 676 if (bps == 0) 677 return (0); 678 679 #ifdef DIAGNOSTIC 680 if (cs->cs_brg_clk == 0) 681 panic("zs_set_speed"); 682 #endif 683 684 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 685 if (tconst < 0) 686 return (EINVAL); 687 688 /* Convert back to make sure we can do it. */ 689 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 690 691 /* XXX - Allow some tolerance here? */ 692 if (real_bps != bps) 693 return (EINVAL); 694 695 cs->cs_preg[12] = tconst; 696 cs->cs_preg[13] = tconst >> 8; 697 698 /* Caller will stuff the pending registers. */ 699 return (0); 700 } 701 702 int 703 zs_set_modes(cs, cflag) 704 struct zs_chanstate *cs; 705 int cflag; /* bits per second */ 706 { 707 int s; 708 709 /* 710 * Output hardware flow control on the chip is horrendous: 711 * if carrier detect drops, the receiver is disabled, and if 712 * CTS drops, the transmitter is stoped IN MID CHARACTER! 713 * Therefore, NEVER set the HFC bit, and instead use the 714 * status interrupt to detect CTS changes. 715 */ 716 s = splzs(); 717 cs->cs_rr0_pps = 0; 718 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 719 cs->cs_rr0_dcd = 0; 720 if ((cflag & MDMBUF) == 0) 721 cs->cs_rr0_pps = ZSRR0_DCD; 722 } else 723 cs->cs_rr0_dcd = ZSRR0_DCD; 724 if ((cflag & CRTSCTS) != 0) { 725 cs->cs_wr5_dtr = ZSWR5_DTR; 726 cs->cs_wr5_rts = ZSWR5_RTS; 727 cs->cs_rr0_cts = ZSRR0_CTS; 728 } else if ((cflag & CDTRCTS) != 0) { 729 cs->cs_wr5_dtr = 0; 730 cs->cs_wr5_rts = ZSWR5_DTR; 731 cs->cs_rr0_cts = ZSRR0_CTS; 732 } else if ((cflag & MDMBUF) != 0) { 733 cs->cs_wr5_dtr = 0; 734 cs->cs_wr5_rts = ZSWR5_DTR; 735 cs->cs_rr0_cts = ZSRR0_DCD; 736 } else { 737 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 738 cs->cs_wr5_rts = 0; 739 cs->cs_rr0_cts = 0; 740 } 741 splx(s); 742 743 /* Caller will stuff the pending registers. */ 744 return (0); 745 } 746 747 748 /* 749 * Read or write the chip with suitable delays. 750 */ 751 752 u_char 753 zs_read_reg(cs, reg) 754 struct zs_chanstate *cs; 755 u_char reg; 756 { 757 u_char val; 758 759 *cs->cs_reg_csr = reg; 760 ZS_DELAY(); 761 val = *cs->cs_reg_csr; 762 ZS_DELAY(); 763 return (val); 764 } 765 766 void 767 zs_write_reg(cs, reg, val) 768 struct zs_chanstate *cs; 769 u_char reg, val; 770 { 771 *cs->cs_reg_csr = reg; 772 ZS_DELAY(); 773 *cs->cs_reg_csr = val; 774 ZS_DELAY(); 775 } 776 777 u_char 778 zs_read_csr(cs) 779 struct zs_chanstate *cs; 780 { 781 register u_char val; 782 783 val = *cs->cs_reg_csr; 784 ZS_DELAY(); 785 return (val); 786 } 787 788 void zs_write_csr(cs, val) 789 struct zs_chanstate *cs; 790 u_char val; 791 { 792 *cs->cs_reg_csr = val; 793 ZS_DELAY(); 794 } 795 796 u_char zs_read_data(cs) 797 struct zs_chanstate *cs; 798 { 799 register u_char val; 800 801 val = *cs->cs_reg_data; 802 ZS_DELAY(); 803 return (val); 804 } 805 806 void zs_write_data(cs, val) 807 struct zs_chanstate *cs; 808 u_char val; 809 { 810 *cs->cs_reg_data = val; 811 ZS_DELAY(); 812 } 813 814 /**************************************************************** 815 * Console support functions (Sun specific!) 816 * Note: this code is allowed to know about the layout of 817 * the chip registers, and uses that to keep things simple. 818 * XXX - I think I like the mvme167 code better. -gwr 819 ****************************************************************/ 820 821 extern void Debugger __P((void)); 822 void *zs_conschan; 823 824 /* 825 * Handle user request to enter kernel debugger. 826 */ 827 void 828 zs_abort(cs) 829 struct zs_chanstate *cs; 830 { 831 register volatile struct zschan *zc = zs_conschan; 832 int rr0; 833 834 /* Wait for end of break to avoid PROM abort. */ 835 /* XXX - Limit the wait? */ 836 do { 837 rr0 = zc->zc_csr; 838 ZS_DELAY(); 839 } while (rr0 & ZSRR0_BREAK); 840 841 #if defined(KGDB) 842 zskgdb(cs); 843 #elif defined(DDB) 844 { 845 extern int db_active; 846 847 if (!db_active) 848 Debugger(); 849 else 850 /* Debugger is probably hozed */ 851 callrom(); 852 } 853 #else 854 printf("stopping on keyboard abort\n"); 855 callrom(); 856 #endif 857 } 858 859 /* 860 * Polled input char. 861 */ 862 int 863 zs_getc(arg) 864 void *arg; 865 { 866 register volatile struct zschan *zc = arg; 867 register int s, c, rr0; 868 869 s = splhigh(); 870 /* Wait for a character to arrive. */ 871 do { 872 rr0 = zc->zc_csr; 873 ZS_DELAY(); 874 } while ((rr0 & ZSRR0_RX_READY) == 0); 875 876 c = zc->zc_data; 877 ZS_DELAY(); 878 splx(s); 879 880 /* 881 * This is used by the kd driver to read scan codes, 882 * so don't translate '\r' ==> '\n' here... 883 */ 884 return (c); 885 } 886 887 /* 888 * Polled output char. 889 */ 890 void 891 zs_putc(arg, c) 892 void *arg; 893 int c; 894 { 895 register volatile struct zschan *zc = arg; 896 register int s, rr0; 897 898 s = splhigh(); 899 900 /* Wait for transmitter to become ready. */ 901 do { 902 rr0 = zc->zc_csr; 903 ZS_DELAY(); 904 } while ((rr0 & ZSRR0_TX_READY) == 0); 905 906 /* 907 * Send the next character. 908 * Now you'd think that this could be followed by a ZS_DELAY() 909 * just like all the other chip accesses, but it turns out that 910 * the `transmit-ready' interrupt isn't de-asserted until 911 * some period of time after the register write completes 912 * (more than a couple instructions). So to avoid stray 913 * interrupts we put in the 2us delay regardless of cpu model. 914 */ 915 zc->zc_data = c; 916 delay(2); 917 918 splx(s); 919 } 920 921 /*****************************************************************/ 922 923 static void zscninit __P((struct consdev *)); 924 static int zscngetc __P((dev_t)); 925 static void zscnputc __P((dev_t, int)); 926 static void zscnpollc __P((dev_t, int)); 927 /* 928 * Console table shared by ttya, ttyb 929 */ 930 struct consdev consdev_zs = { 931 nullcnprobe, 932 zscninit, 933 zscngetc, 934 zscnputc, 935 zscnpollc, 936 NULL, 937 }; 938 939 static void 940 zscninit(cn) 941 struct consdev *cn; 942 { 943 } 944 945 /* 946 * Polled console input putchar. 947 */ 948 static int 949 zscngetc(dev) 950 dev_t dev; 951 { 952 return (zs_getc(zs_conschan)); 953 } 954 955 /* 956 * Polled console output putchar. 957 */ 958 static void 959 zscnputc(dev, c) 960 dev_t dev; 961 int c; 962 { 963 zs_putc(zs_conschan, c); 964 } 965 966 int swallow_zsintrs; 967 968 static void 969 zscnpollc(dev, on) 970 dev_t dev; 971 int on; 972 { 973 /* 974 * Need to tell zs driver to acknowledge all interrupts or we get 975 * annoying spurious interrupt messages. This is because mucking 976 * with spl() levels during polling does not prevent interrupts from 977 * being generated. 978 */ 979 980 if (on) swallow_zsintrs++; 981 else swallow_zsintrs--; 982 } 983