xref: /netbsd-src/sys/arch/sparc64/dev/zs.c (revision 1b9578b8c2c1f848eeb16dabbfd7d1f0d9fdefbd) 
1 /*	$NetBSD: zs.c,v 1.70 2011/03/12 11:43:38 nakayama Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Zilog Z8530 Dual UART driver (machine-dependent part)
34  *
35  * Runs two serial lines per chip using slave drivers.
36  * Plain tty/async lines use the zs_async slave.
37  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
38  */
39 
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.70 2011/03/12 11:43:38 nakayama Exp $");
42 
43 #include "opt_ddb.h"
44 #include "opt_kgdb.h"
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/conf.h>
49 #include <sys/device.h>
50 #include <sys/file.h>
51 #include <sys/ioctl.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h>
54 #include <sys/tty.h>
55 #include <sys/time.h>
56 #include <sys/syslog.h>
57 #include <sys/intr.h>
58 
59 #include <machine/autoconf.h>
60 #include <machine/openfirm.h>
61 #include <machine/cpu.h>
62 #include <machine/eeprom.h>
63 #include <machine/psl.h>
64 #include <machine/z8530var.h>
65 
66 #include <dev/cons.h>
67 #include <dev/ic/z8530reg.h>
68 #include <dev/sun/kbd_ms_ttyvar.h>
69 #include <ddb/db_output.h>
70 
71 #include <dev/sbus/sbusvar.h>
72 #include <sparc64/dev/cons.h>
73 
74 #include "ioconf.h"
75 #include "kbd.h"	/* NKBD */
76 #include "ms.h"		/* NMS */
77 #include "zs.h" 	/* NZS */
78 
79 /* Make life easier for the initialized arrays here. */
80 #if NZS < 3
81 #undef  NZS
82 #define NZS 3
83 #endif
84 
85 /*
86  * Some warts needed by z8530tty.c -
87  * The default parity REALLY needs to be the same as the PROM uses,
88  * or you can not see messages done with printf during boot-up...
89  */
90 int zs_def_cflag = (CREAD | CS8 | HUPCL);
91 
92 /*
93  * The Sun provides a 4.9152 MHz clock to the ZS chips.
94  */
95 #define PCLK	(9600 * 512)	/* PCLK pin input clock rate */
96 
97 #define	ZS_DELAY()
98 
99 /* The layout of this is hardware-dependent (padding, order). */
100 struct zschan {
101 	volatile uint8_t zc_csr;	/* ctrl,status, and indirect access */
102 	uint8_t		zc_xxx0;
103 	volatile uint8_t zc_data;	/* data */
104 	uint8_t		zc_xxx1;
105 };
106 struct zsdevice {
107 	/* Yes, they are backwards. */
108 	struct	zschan zs_chan_b;
109 	struct	zschan zs_chan_a;
110 };
111 
112 /* ZS channel used as the console device (if any) */
113 void *zs_conschan_get, *zs_conschan_put;
114 
115 /* Saved PROM mappings */
116 static struct zsdevice *zsaddr[NZS];
117 
118 static uint8_t zs_init_reg[16] = {
119 	0,	/* 0: CMD (reset, etc.) */
120 	0,	/* 1: No interrupts yet. */
121 	0,	/* 2: IVECT */
122 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
123 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
124 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
125 	0,	/* 6: TXSYNC/SYNCLO */
126 	0,	/* 7: RXSYNC/SYNCHI */
127 	0,	/* 8: alias for data port */
128 	ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
129 	0,	/*10: Misc. TX/RX control bits */
130 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
131 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
132 	0,			/*13: BAUDHI (default=9600) */
133 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
134 	ZSWR15_BREAK_IE,
135 };
136 
137 /* Console ops */
138 static int  zscngetc(dev_t);
139 static void zscnputc(dev_t, int);
140 static void zscnpollc(dev_t, int);
141 
142 struct consdev zs_consdev = {
143 	.cn_getc = zscngetc,
144 	.cn_putc = zscnputc,
145 	.cn_pollc = zscnpollc,
146 };
147 
148 
149 /****************************************************************
150  * Autoconfig
151  ****************************************************************/
152 
153 /* Definition of the driver for autoconfig. */
154 static int  zs_match_sbus(device_t, cfdata_t, void *);
155 static void zs_attach_sbus(device_t, device_t, void *);
156 
157 static void zs_attach(struct zsc_softc *, struct zsdevice *, int);
158 static int  zs_print(void *, const char *);
159 
160 CFATTACH_DECL_NEW(zs, sizeof(struct zsc_softc),
161     zs_match_sbus, zs_attach_sbus, NULL, NULL);
162 
163 /* Interrupt handlers. */
164 int zscheckintr(void *);
165 static int zshard(void *);
166 static void zssoft(void *);
167 
168 static int zs_get_speed(struct zs_chanstate *);
169 
170 /* Console device support */
171 static int zs_console_flags(int, int, int);
172 
173 /* Power management hooks */
174 int  zs_enable(struct zs_chanstate *);
175 void zs_disable(struct zs_chanstate *);
176 
177 /* from dev/ic/z8530tty.c */
178 struct tty *zstty_get_tty_from_dev(struct device *);
179 
180 /*
181  * Is the zs chip present?
182  */
183 static int
184 zs_match_sbus(device_t parent, cfdata_t cf, void *aux)
185 {
186 	struct sbus_attach_args *sa = aux;
187 
188 	if (strcmp(cf->cf_name, sa->sa_name) != 0)
189 		return (0);
190 
191 	return (1);
192 }
193 
194 static void
195 zs_attach_sbus(device_t parent, device_t self, void *aux)
196 {
197 	struct zsc_softc *zsc = device_private(self);
198 	struct sbus_attach_args *sa = aux;
199 	bus_space_handle_t bh;
200 	int zs_unit;
201 
202 	zsc->zsc_dev = self;
203 	zs_unit = device_unit(self);
204 
205 	if (sa->sa_nintr == 0) {
206 		aprint_error(": no interrupt lines\n");
207 		return;
208 	}
209 
210 	/* Use the mapping setup by the Sun PROM if possible. */
211 	if (zsaddr[zs_unit] == NULL) {
212 		/* Only map registers once. */
213 		if (sa->sa_npromvaddrs) {
214 			/*
215 			 * We're converting from a 32-bit pointer to a 64-bit
216 			 * pointer.  Since the 32-bit entity is negative, but
217 			 * the kernel is still mapped into the lower 4GB
218 			 * range, this needs to be zero-extended.
219 			 *
220 			 * XXXXX If we map the kernel and devices into the
221 			 * high 4GB range, this needs to be changed to
222 			 * sign-extend the address.
223 			 */
224 			sparc_promaddr_to_handle(sa->sa_bustag,
225 				sa->sa_promvaddrs[0], &bh);
226 
227 		} else {
228 
229 			if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
230 					 sa->sa_offset,
231 					 sa->sa_size,
232 					 BUS_SPACE_MAP_LINEAR,
233 					 &bh) != 0) {
234 				aprint_error(": cannot map registers\n");
235 				return;
236 			}
237 		}
238 		zsaddr[zs_unit] = bus_space_vaddr(sa->sa_bustag, bh);
239 	}
240 	zsc->zsc_bustag = sa->sa_bustag;
241 	zsc->zsc_dmatag = sa->sa_dmatag;
242 	zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2);
243 	zsc->zsc_node = sa->sa_node;
244 	zs_attach(zsc, zsaddr[zs_unit], sa->sa_pri);
245 }
246 
247 /*
248  * Attach a found zs.
249  *
250  * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
251  * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
252  */
253 static void
254 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri)
255 {
256 	struct zsc_attach_args zsc_args;
257 	struct zs_chanstate *cs;
258 	int channel;
259 
260 	if (zsd == NULL) {
261 		aprint_error(": configuration incomplete\n");
262 		return;
263 	}
264 
265 	/*
266 	 * Initialize software state for each channel.
267 	 */
268 	for (channel = 0; channel < 2; channel++) {
269 		struct zschan *zc;
270 		struct device *child;
271 
272 		zsc_args.channel = channel;
273 		cs = &zsc->zsc_cs_store[channel];
274 		zsc->zsc_cs[channel] = cs;
275 
276 		zs_lock_init(cs);
277 		cs->cs_channel = channel;
278 		cs->cs_private = NULL;
279 		cs->cs_ops = &zsops_null;
280 		cs->cs_brg_clk = PCLK / 16;
281 
282 		zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
283 
284 		zsc_args.consdev = NULL;
285 		zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit,
286 						    zsc->zsc_node,
287 						    channel);
288 
289 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
290 			zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV;
291 			zsc_args.consdev = &zs_consdev;
292 		}
293 
294 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
295 			zs_conschan_get = zc;
296 		}
297 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
298 			zs_conschan_put = zc;
299 		}
300 
301 		/* Children need to set cn_dev, etc */
302 		cs->cs_reg_csr  = &zc->zc_csr;
303 		cs->cs_reg_data = &zc->zc_data;
304 
305 		memcpy(cs->cs_creg, zs_init_reg, 16);
306 		memcpy(cs->cs_preg, zs_init_reg, 16);
307 
308 		/* XXX: Consult PROM properties for this?! */
309 		cs->cs_defspeed = zs_get_speed(cs);
310 		cs->cs_defcflag = zs_def_cflag;
311 
312 		/* Make these correspond to cs_defcflag (-crtscts) */
313 		cs->cs_rr0_dcd = ZSRR0_DCD;
314 		cs->cs_rr0_cts = 0;
315 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
316 		cs->cs_wr5_rts = 0;
317 
318 		/*
319 		 * Clear the master interrupt enable.
320 		 * The INTENA is common to both channels,
321 		 * so just do it on the A channel.
322 		 */
323 		if (channel == 0) {
324 			zs_write_reg(cs, 9, 0);
325 		}
326 
327 		/*
328 		 * Look for a child driver for this channel.
329 		 * The child attach will setup the hardware.
330 		 */
331 		child = config_found(zsc->zsc_dev, (void *)&zsc_args,
332 		    zs_print);
333 		if (child == NULL) {
334 			/* No sub-driver.  Just reset it. */
335 			uint8_t reset = (channel == 0) ?
336 				ZSWR9_A_RESET : ZSWR9_B_RESET;
337 			zs_lock_chan(cs);
338 			zs_write_reg(cs,  9, reset);
339 			zs_unlock_chan(cs);
340 		}
341 #if (NKBD > 0) || (NMS > 0)
342 		/*
343 		 * If this was a zstty it has a keyboard
344 		 * property on it we need to attach the
345 		 * sunkbd and sunms line disciplines.
346 		 */
347 		if (child
348 		    && (device_is_a(child, "zstty"))
349 		    && (prom_getproplen(zsc->zsc_node, "keyboard") == 0)) {
350 			struct kbd_ms_tty_attach_args kma;
351 			struct tty *tp;
352 
353 			kma.kmta_tp = tp = zstty_get_tty_from_dev(child);
354 			kma.kmta_dev = tp->t_dev;
355 			kma.kmta_consdev = zsc_args.consdev;
356 
357 			/* Attach 'em if we got 'em. */
358 #if (NKBD > 0)
359 			if (channel == 0) {
360 				kma.kmta_name = "keyboard";
361 				config_found(child, (void *)&kma, NULL);
362 			}
363 #endif
364 #if (NMS > 0)
365 			if (channel == 1) {
366 				kma.kmta_name = "mouse";
367 				config_found(child, (void *)&kma, NULL);
368 			}
369 #endif
370 		}
371 #endif
372 	}
373 
374 	/*
375 	 * Now safe to install interrupt handlers.  Note the arguments
376 	 * to the interrupt handlers aren't used.  Note, we only do this
377 	 * once since both SCCs interrupt at the same level and vector.
378 	 */
379 	bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc);
380 	if (!(zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL, zssoft, zsc)))
381 		panic("zsattach: could not establish soft interrupt");
382 
383 	evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
384 	    device_xname(zsc->zsc_dev), "intr");
385 
386 
387 	/*
388 	 * Set the master interrupt enable and interrupt vector.
389 	 * (common to both channels, do it on A)
390 	 */
391 	cs = zsc->zsc_cs[0];
392 	zs_lock_chan(cs);
393 	/* interrupt vector */
394 	zs_write_reg(cs, 2, zs_init_reg[2]);
395 	/* master interrupt control (enable) */
396 	zs_write_reg(cs, 9, zs_init_reg[9]);
397 	zs_unlock_chan(cs);
398 }
399 
400 static int
401 zs_print(void *aux, const char *name)
402 {
403 	struct zsc_attach_args *args = aux;
404 
405 	if (name != NULL)
406 		aprint_normal("%s: ", name);
407 
408 	if (args->channel != -1)
409 		aprint_normal(" channel %d", args->channel);
410 
411 	return (UNCONF);
412 }
413 
414 static int
415 zshard(void *arg)
416 {
417 	struct zsc_softc *zsc = arg;
418 	int rr3, rval;
419 
420 	rval = 0;
421 	while ((rr3 = zsc_intr_hard(zsc))) {
422 		/* Count up the interrupts. */
423 		rval |= rr3;
424 		zsc->zsc_intrcnt.ev_count++;
425 	}
426 	if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) ||
427 	     (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) &&
428 	    zsc->zsc_softintr) {
429 		softint_schedule(zsc->zsc_softintr);
430 	}
431 	return (rval);
432 }
433 
434 int
435 zscheckintr(void *arg)
436 {
437 	struct zsc_softc *zsc;
438 	int unit, rval;
439 
440 	rval = 0;
441 	for (unit = 0; unit < zs_cd.cd_ndevs; unit++) {
442 
443 		zsc = device_lookup_private(&zs_cd, unit);
444 		if (zsc == NULL)
445 			continue;
446 		rval = (zshard((void *)zsc) || rval);
447 	}
448 	return (rval);
449 }
450 
451 
452 /*
453  * We need this only for TTY_DEBUG purposes.
454  */
455 static void
456 zssoft(void *arg)
457 {
458 	struct zsc_softc *zsc = arg;
459 
460 #if 0 /* not yet */
461 	/* Make sure we call the tty layer with tty_lock held. */
462 	mutex_spin_enter(&tty_lock);
463 #endif
464 	(void)zsc_intr_soft(zsc);
465 #ifdef TTY_DEBUG
466 	{
467 		struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private;
468 		struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private;
469 		if (zst0->zst_overflows || zst1->zst_overflows ) {
470 			struct trapframe *frame = (struct trapframe *)arg;
471 
472 			printf("zs silo overflow from %p\n",
473 			       (long)frame->tf_pc);
474 		}
475 	}
476 #endif
477 #if 0 /* not yet */
478 	mutex_spin_exit(&tty_lock);
479 #endif
480 }
481 
482 
483 /*
484  * Compute the current baud rate given a ZS channel.
485  */
486 static int
487 zs_get_speed(struct zs_chanstate *cs)
488 {
489 	int tconst;
490 
491 	tconst = zs_read_reg(cs, 12);
492 	tconst |= zs_read_reg(cs, 13) << 8;
493 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
494 }
495 
496 /*
497  * MD functions for setting the baud rate and control modes.
498  */
499 int
500 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */)
501 {
502 	int tconst, real_bps;
503 
504 	if (bps == 0)
505 		return (0);
506 
507 #ifdef	DIAGNOSTIC
508 	if (cs->cs_brg_clk == 0)
509 		panic("zs_set_speed");
510 #endif
511 
512 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
513 	if (tconst < 0)
514 		return (EINVAL);
515 
516 	/* Convert back to make sure we can do it. */
517 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
518 
519 	/* XXX - Allow some tolerance here? */
520 	if (real_bps != bps)
521 		return (EINVAL);
522 
523 	cs->cs_preg[12] = tconst;
524 	cs->cs_preg[13] = tconst >> 8;
525 
526 	/* Caller will stuff the pending registers. */
527 	return (0);
528 }
529 
530 int
531 zs_set_modes(struct zs_chanstate *cs, int cflag)
532 {
533 
534 	/*
535 	 * Output hardware flow control on the chip is horrendous:
536 	 * if carrier detect drops, the receiver is disabled, and if
537 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
538 	 * Therefore, NEVER set the HFC bit, and instead use the
539 	 * status interrupt to detect CTS changes.
540 	 */
541 	zs_lock_chan(cs);
542 	cs->cs_rr0_pps = 0;
543 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
544 		cs->cs_rr0_dcd = 0;
545 		if ((cflag & MDMBUF) == 0)
546 			cs->cs_rr0_pps = ZSRR0_DCD;
547 	} else
548 		cs->cs_rr0_dcd = ZSRR0_DCD;
549 	if ((cflag & CRTSCTS) != 0) {
550 		cs->cs_wr5_dtr = ZSWR5_DTR;
551 		cs->cs_wr5_rts = ZSWR5_RTS;
552 		cs->cs_rr0_cts = ZSRR0_CTS;
553 	} else if ((cflag & CDTRCTS) != 0) {
554 		cs->cs_wr5_dtr = 0;
555 		cs->cs_wr5_rts = ZSWR5_DTR;
556 		cs->cs_rr0_cts = ZSRR0_CTS;
557 	} else if ((cflag & MDMBUF) != 0) {
558 		cs->cs_wr5_dtr = 0;
559 		cs->cs_wr5_rts = ZSWR5_DTR;
560 		cs->cs_rr0_cts = ZSRR0_DCD;
561 	} else {
562 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
563 		cs->cs_wr5_rts = 0;
564 		cs->cs_rr0_cts = 0;
565 	}
566 	zs_unlock_chan(cs);
567 
568 	/* Caller will stuff the pending registers. */
569 	return (0);
570 }
571 
572 
573 /*
574  * Read or write the chip with suitable delays.
575  */
576 
577 u_char
578 zs_read_reg(struct zs_chanstate *cs, u_char reg)
579 {
580 	u_char val;
581 
582 	*cs->cs_reg_csr = reg;
583 	ZS_DELAY();
584 	val = *cs->cs_reg_csr;
585 	ZS_DELAY();
586 	return (val);
587 }
588 
589 void
590 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
591 {
592 	*cs->cs_reg_csr = reg;
593 	ZS_DELAY();
594 	*cs->cs_reg_csr = val;
595 	ZS_DELAY();
596 }
597 
598 u_char
599 zs_read_csr(struct zs_chanstate *cs)
600 {
601 	u_char val;
602 
603 	val = *cs->cs_reg_csr;
604 	ZS_DELAY();
605 	return (val);
606 }
607 
608 void
609 zs_write_csr(struct zs_chanstate *cs, u_char val)
610 {
611 	*cs->cs_reg_csr = val;
612 	ZS_DELAY();
613 }
614 
615 u_char
616 zs_read_data(struct zs_chanstate *cs)
617 {
618 	u_char val;
619 
620 	val = *cs->cs_reg_data;
621 	ZS_DELAY();
622 	return (val);
623 }
624 
625 void
626 zs_write_data(struct zs_chanstate *cs, u_char val)
627 {
628 	*cs->cs_reg_data = val;
629 	ZS_DELAY();
630 }
631 
632 /****************************************************************
633  * Console support functions (Sun specific!)
634  * Note: this code is allowed to know about the layout of
635  * the chip registers, and uses that to keep things simple.
636  * XXX - I think I like the mvme167 code better. -gwr
637  ****************************************************************/
638 
639 extern void Debugger(void);
640 
641 /*
642  * Handle user request to enter kernel debugger.
643  */
644 void
645 zs_abort(struct zs_chanstate *cs)
646 {
647 	volatile struct zschan *zc = zs_conschan_get;
648 	int rr0;
649 
650 	/* Wait for end of break to avoid PROM abort. */
651 	/* XXX - Limit the wait? */
652 	do {
653 		rr0 = zc->zc_csr;
654 		ZS_DELAY();
655 	} while (rr0 & ZSRR0_BREAK);
656 
657 #if defined(KGDB)
658 	zskgdb(cs);
659 #elif defined(DDB)
660 	{
661 		extern int db_active;
662 
663 		if (!db_active)
664 			Debugger();
665 		else
666 			/* Debugger is probably hozed */
667 			callrom();
668 	}
669 #else
670 	printf("stopping on keyboard abort\n");
671 	callrom();
672 #endif
673 }
674 
675 
676 /*
677  * Polled input char.
678  */
679 int
680 zs_getc(void *arg)
681 {
682 	volatile struct zschan *zc = arg;
683 	int s, c, rr0;
684 
685 	s = splhigh();
686 	/* Wait for a character to arrive. */
687 	do {
688 		rr0 = zc->zc_csr;
689 		ZS_DELAY();
690 	} while ((rr0 & ZSRR0_RX_READY) == 0);
691 
692 	c = zc->zc_data;
693 	ZS_DELAY();
694 	splx(s);
695 
696 	/*
697 	 * This is used by the kd driver to read scan codes,
698 	 * so don't translate '\r' ==> '\n' here...
699 	 */
700 	return (c);
701 }
702 
703 /*
704  * Polled output char.
705  */
706 void
707 zs_putc(void *arg, int c)
708 {
709 	volatile struct zschan *zc = arg;
710 	int s, rr0;
711 
712 	s = splhigh();
713 
714 	/* Wait for transmitter to become ready. */
715 	do {
716 		rr0 = zc->zc_csr;
717 		ZS_DELAY();
718 	} while ((rr0 & ZSRR0_TX_READY) == 0);
719 
720 	/*
721 	 * Send the next character.
722 	 * Now you'd think that this could be followed by a ZS_DELAY()
723 	 * just like all the other chip accesses, but it turns out that
724 	 * the `transmit-ready' interrupt isn't de-asserted until
725 	 * some period of time after the register write completes
726 	 * (more than a couple instructions).  So to avoid stray
727 	 * interrupts we put in the 2us delay regardless of CPU model.
728 	 */
729 	zc->zc_data = c;
730 	delay(2);
731 
732 	splx(s);
733 }
734 
735 /*****************************************************************/
736 
737 
738 
739 
740 /*
741  * Polled console input putchar.
742  */
743 static int
744 zscngetc(dev_t dev)
745 {
746 	return (zs_getc(zs_conschan_get));
747 }
748 
749 /*
750  * Polled console output putchar.
751  */
752 static void
753 zscnputc(dev_t dev, int c)
754 {
755 	zs_putc(zs_conschan_put, c);
756 }
757 
758 int swallow_zsintrs;
759 
760 static void
761 zscnpollc(dev_t dev, int on)
762 {
763 	/*
764 	 * Need to tell zs driver to acknowledge all interrupts or we get
765 	 * annoying spurious interrupt messages.  This is because mucking
766 	 * with spl() levels during polling does not prevent interrupts from
767 	 * being generated.
768 	 */
769 
770 	if (on) swallow_zsintrs++;
771 	else swallow_zsintrs--;
772 }
773 
774 int
775 zs_console_flags(int promunit, int node, int channel)
776 {
777 	int cookie, flags = 0;
778 	char buf[255];
779 
780 	/*
781 	 * We'll just do the OBP grovelling down here since that's
782 	 * the only type of firmware we support.
783 	 */
784 
785 	/* Default to channel 0 if there are no explicit prom args */
786 	cookie = 0;
787 	if (node == prom_instance_to_package(prom_stdin())) {
788 		if (prom_getoption("input-device", buf, sizeof buf) == 0 &&
789 		    strcmp("ttyb", buf) == 0)
790 			cookie = 1;
791 
792 		if (channel == cookie)
793 			flags |= ZS_HWFLAG_CONSOLE_INPUT;
794 	}
795 
796 	if (node == prom_instance_to_package(prom_stdout())) {
797 		if (prom_getoption("output-device", buf, sizeof buf) == 0 &&
798 		    strcmp("ttyb", buf) == 0)
799 			cookie = 1;
800 
801 		if (channel == cookie)
802 			flags |= ZS_HWFLAG_CONSOLE_OUTPUT;
803 	}
804 
805 	return (flags);
806 }
807 
808