1 /* $NetBSD: psycho.c,v 1.127 2019/02/05 06:10:53 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.127 2019/02/05 06:10:53 mrg Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 #define PDB_STICK 0x20 74 int psycho_debug = 0x0; 75 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 76 #else 77 #define DPRINTF(l, s) 78 #endif 79 80 #include <sys/param.h> 81 #include <sys/device.h> 82 #include <sys/errno.h> 83 #include <sys/extent.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/time.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #define _SPARC_BUS_DMA_PRIVATE 92 #include <sys/bus.h> 93 #include <machine/autoconf.h> 94 #include <machine/psl.h> 95 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcireg.h> 98 #include <dev/sysmon/sysmon_taskq.h> 99 100 #include <sparc64/dev/iommureg.h> 101 #include <sparc64/dev/iommuvar.h> 102 #include <sparc64/dev/psychoreg.h> 103 #include <sparc64/dev/psychovar.h> 104 105 #include "ioconf.h" 106 107 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 108 pci_chipset_tag_t); 109 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 110 const char *); 111 static void psycho_get_bus_range(int, int *); 112 static void psycho_fixup_bus_range(int, int *); 113 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 114 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 115 uint64_t *); 116 117 /* chipset handlers */ 118 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 119 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 120 pcireg_t); 121 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 122 pci_intr_handle_t, 123 int, int (*)(void *), void *); 124 static int psycho_pci_find_ino(const struct pci_attach_args *, 125 pci_intr_handle_t *); 126 127 /* Interrupt handlers */ 128 static int psycho_ue(void *); 129 static int psycho_ce(void *); 130 static int psycho_bus_a(void *); 131 static int psycho_bus_b(void *); 132 static int psycho_powerfail(void *); 133 static int psycho_wakeup(void *); 134 135 136 /* IOMMU support */ 137 static void psycho_iommu_init(struct psycho_softc *, int); 138 139 /* 140 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 141 * of the bus DMA support is provided by the iommu dvma controller. 142 */ 143 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 144 145 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 146 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 147 vaddr_t, bus_space_handle_t *); 148 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 149 void *, void(*)(void)); 150 151 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 152 bus_size_t, int, bus_dmamap_t *); 153 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 154 bus_size_t, int); 155 156 /* base pci_chipset */ 157 extern struct sparc_pci_chipset _sparc_pci_chipset; 158 159 /* power button handlers */ 160 static void psycho_register_power_button(struct psycho_softc *sc); 161 static void psycho_power_button_pressed(void *arg); 162 163 /* 164 * autoconfiguration 165 */ 166 static int psycho_match(device_t, cfdata_t, void *); 167 static void psycho_attach(device_t, device_t, void *); 168 static int psycho_print(void *aux, const char *p); 169 170 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 171 psycho_match, psycho_attach, NULL, NULL); 172 173 /* 174 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 175 * single PCI bus and does not have a streaming buffer. It often has an APB 176 * (advanced PCI bridge) connected to it, which was designed specifically for 177 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 178 * appears as two "simba"'s underneath the sabre. 179 * 180 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 181 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 182 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 183 * will usually find a "psycho+" since I don't think the original "psycho" 184 * ever shipped, and if it did it would be in the U30. 185 * 186 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 187 * both part of the same IC, they only have a single register space. As such, 188 * they need to be configured together, even though the autoconfiguration will 189 * attach them separately. 190 * 191 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 192 * as pci1 and pci2, although they have been implemented with other PCI bus 193 * numbers on some machines. 194 * 195 * On UltraII machines, there can be any number of "psycho+" ICs, each 196 * providing two PCI buses. 197 * 198 * 199 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 200 * the values of the following interrupts in this order: 201 * 202 * PCI Bus Error (30) 203 * DMA UE (2e) 204 * DMA CE (2f) 205 * Power Fail (25) 206 * 207 * We really should attach handlers for each. 208 * 209 */ 210 211 #define ROM_PCI_NAME "pci" 212 213 struct psycho_names { 214 const char *p_name; 215 int p_type; 216 } psycho_names[] = { 217 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 218 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 219 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 220 { "pci108e,a000", PSYCHO_MODE_SABRE }, 221 { "pci108e,a001", PSYCHO_MODE_SABRE }, 222 { NULL, 0 } 223 }; 224 225 struct psycho_softc *psycho0 = NULL; 226 227 static int 228 psycho_match(device_t parent, cfdata_t match, void *aux) 229 { 230 struct mainbus_attach_args *ma = aux; 231 char *model; 232 int i; 233 234 if (ma->ma_node == 0) 235 return 0; /* no OF node, can't be us */ 236 237 model = prom_getpropstring(ma->ma_node, "model"); 238 /* match on a name of "pci" and a sabre or a psycho */ 239 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 240 for (i=0; psycho_names[i].p_name; i++) 241 if (strcmp(model, psycho_names[i].p_name) == 0) 242 return (1); 243 244 model = prom_getpropstring(ma->ma_node, "compatible"); 245 for (i=0; psycho_names[i].p_name; i++) 246 if (strcmp(model, psycho_names[i].p_name) == 0) 247 return (1); 248 } 249 return (0); 250 } 251 252 #ifdef DEBUG 253 static void psycho_dump_intmap(struct psycho_softc *sc); 254 static void 255 psycho_dump_intmap(struct psycho_softc *sc) 256 { 257 volatile uint64_t *intrmapptr = NULL; 258 259 printf("psycho_dump_intmap: OBIO\n"); 260 261 for (intrmapptr = &sc->sc_regs->scsi_int_map; 262 intrmapptr < &sc->sc_regs->ue_int_map; 263 intrmapptr++) 264 printf("%p: %llx\n", intrmapptr, 265 (unsigned long long)*intrmapptr); 266 267 printf("\tintmap:pci\n"); 268 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 269 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 270 intrmapptr++) 271 printf("%p: %llx\n", intrmapptr, 272 (unsigned long long)*intrmapptr); 273 274 printf("\tintmap:ffb\n"); 275 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 276 intrmapptr <= &sc->sc_regs->ffb1_int_map; 277 intrmapptr++) 278 printf("%p: %llx\n", intrmapptr, 279 (unsigned long long)*intrmapptr); 280 } 281 #endif 282 283 /* 284 * SUNW,psycho initialisation .. 285 * - find the per-psycho registers 286 * - figure out the IGN. 287 * - find our partner psycho 288 * - configure ourselves 289 * - bus range, bus, 290 * - get interrupt-map and interrupt-map-mask 291 * - setup the chipsets. 292 * - if we're the first of the pair, initialise the IOMMU, otherwise 293 * just copy its tags and addresses. 294 */ 295 static void 296 psycho_attach(device_t parent, device_t self, void *aux) 297 { 298 struct psycho_softc *sc = device_private(self); 299 struct psycho_softc *osc = NULL; 300 struct psycho_pbm *pp; 301 struct pcibus_attach_args pba; 302 struct mainbus_attach_args *ma = aux; 303 struct psycho_ranges *pr; 304 prop_dictionary_t dict; 305 bus_space_handle_t bh; 306 uint64_t csr, mem_base; 307 int psycho_br[2], n, i; 308 bus_space_handle_t pci_ctl; 309 char *model = prom_getpropstring(ma->ma_node, "model"); 310 311 aprint_normal("\n"); 312 313 sc->sc_dev = self; 314 sc->sc_node = ma->ma_node; 315 sc->sc_bustag = ma->ma_bustag; 316 sc->sc_dmatag = ma->ma_dmatag; 317 sc->sc_last_stick = 0; 318 319 if (psycho0 == NULL) 320 psycho0 = sc; 321 DPRINTF(PDB_STICK, ("init psycho0 %lx\n", (long)sc)); 322 /* 323 * Identify the device. 324 */ 325 for (i=0; psycho_names[i].p_name; i++) 326 if (strcmp(model, psycho_names[i].p_name) == 0) { 327 sc->sc_mode = psycho_names[i].p_type; 328 goto found; 329 } 330 331 model = prom_getpropstring(ma->ma_node, "compatible"); 332 for (i=0; psycho_names[i].p_name; i++) 333 if (strcmp(model, psycho_names[i].p_name) == 0) { 334 sc->sc_mode = psycho_names[i].p_type; 335 goto found; 336 } 337 338 panic("unknown psycho model %s", model); 339 found: 340 341 /* 342 * The psycho gets three register banks: 343 * (0) per-PBM configuration and status registers 344 * (1) per-PBM PCI configuration space, containing only the 345 * PBM 256-byte PCI header 346 * (2) the shared psycho configuration registers (struct psychoreg) 347 */ 348 349 /* Register layouts are different. stuupid. */ 350 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 351 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 352 353 if (ma->ma_naddress > 2) { 354 sparc_promaddr_to_handle(sc->sc_bustag, 355 ma->ma_address[2], &sc->sc_bh); 356 sparc_promaddr_to_handle(sc->sc_bustag, 357 ma->ma_address[0], &pci_ctl); 358 359 sc->sc_regs = (struct psychoreg *) 360 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 361 } else if (ma->ma_nreg > 2) { 362 363 /* We need to map this in ourselves. */ 364 if (bus_space_map(sc->sc_bustag, 365 ma->ma_reg[2].ur_paddr, 366 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 367 &sc->sc_bh)) 368 panic("psycho_attach: cannot map regs"); 369 sc->sc_regs = (struct psychoreg *) 370 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 371 372 if (bus_space_map(sc->sc_bustag, 373 ma->ma_reg[0].ur_paddr, 374 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 375 &pci_ctl)) 376 panic("psycho_attach: cannot map ctl"); 377 } else 378 panic("psycho_attach: %d not enough registers", 379 ma->ma_nreg); 380 381 } else { 382 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 383 384 if (ma->ma_naddress) { 385 sparc_promaddr_to_handle(sc->sc_bustag, 386 ma->ma_address[0], &sc->sc_bh); 387 sc->sc_regs = (struct psychoreg *) 388 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 389 390 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 391 offsetof(struct psychoreg, psy_pcictl), 392 sizeof(struct pci_ctl), &pci_ctl); 393 } else if (ma->ma_nreg) { 394 395 /* We need to map this in ourselves. */ 396 if (bus_space_map(sc->sc_bustag, 397 ma->ma_reg[0].ur_paddr, 398 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 399 &sc->sc_bh)) 400 panic("psycho_attach: cannot map regs"); 401 sc->sc_regs = (struct psychoreg *) 402 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 403 404 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 405 offsetof(struct psychoreg, psy_pcictl), 406 sizeof(struct pci_ctl), &pci_ctl); 407 } else 408 panic("psycho_attach: %d not enough registers", 409 ma->ma_nreg); 410 } 411 412 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 413 offsetof(struct psychoreg, psy_csr)); 414 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 415 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 416 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 417 418 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 419 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 420 sc->sc_ign); 421 /* 422 * Match other psycho's that are already configured against 423 * the base physical address. This will be the same for a 424 * pair of devices that share register space. 425 */ 426 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 427 428 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 429 430 if (asc == NULL || asc == sc) 431 /* This entry is not there or it is me */ 432 continue; 433 434 if (asc->sc_basepaddr != sc->sc_basepaddr) 435 /* This is an unrelated psycho */ 436 continue; 437 438 /* Found partner */ 439 osc = asc; 440 break; 441 } 442 443 444 /* Oh, dear. OK, lets get started */ 445 446 /* 447 * Setup the PCI control register 448 */ 449 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 450 offsetof(struct pci_ctl, pci_csr)); 451 csr |= PCICTL_MRLM | 452 PCICTL_ARB_PARK | 453 PCICTL_ERRINTEN | 454 PCICTL_4ENABLE; 455 csr &= ~(PCICTL_SERR | 456 PCICTL_CPU_PRIO | 457 PCICTL_ARB_PRIO | 458 PCICTL_RTRYWAIT); 459 bus_space_write_8(sc->sc_bustag, pci_ctl, 460 offsetof(struct pci_ctl, pci_csr), csr); 461 462 463 /* 464 * Allocate our psycho_pbm 465 */ 466 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 467 M_NOWAIT | M_ZERO); 468 if (pp == NULL) 469 panic("could not allocate psycho pbm"); 470 471 pp->pp_sc = sc; 472 473 /* grab the psycho ranges */ 474 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 475 476 /* get the bus-range for the psycho */ 477 psycho_get_bus_range(sc->sc_node, psycho_br); 478 479 pba.pba_bus = psycho_br[0]; 480 pba.pba_bridgetag = NULL; 481 482 /* Fix up invalid 0x00-0xff bus-range, as found on SPARCle */ 483 if (psycho_br[0] == 0 && psycho_br[1] == 0xff) 484 psycho_fixup_bus_range(sc->sc_node, psycho_br); 485 486 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 487 aprint_normal("; PCI bus %d", psycho_br[0]); 488 489 pp->pp_pcictl = pci_ctl; 490 491 /* allocate our tags */ 492 pp->pp_memt = psycho_alloc_mem_tag(pp); 493 pp->pp_iot = psycho_alloc_io_tag(pp); 494 pp->pp_dmat = psycho_alloc_dma_tag(pp); 495 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 496 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 497 498 /* allocate a chipset for this */ 499 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 500 pp->pp_pc->spc_busmax = psycho_br[1]; 501 502 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 503 case 0x2000: 504 pp->pp_id = PSYCHO_PBM_A; 505 break; 506 case 0x4000: 507 pp->pp_id = PSYCHO_PBM_B; 508 break; 509 } 510 511 aprint_normal("\n"); 512 513 /* allocate extents for free bus space */ 514 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 515 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 516 517 #ifdef DEBUG 518 if (psycho_debug & PDB_INTR) 519 psycho_dump_intmap(sc); 520 #endif 521 522 /* 523 * And finally, if we're a sabre or the first of a pair of psycho's to 524 * arrive here, start up the IOMMU and get a config space tag. 525 */ 526 if (osc == NULL) { 527 uint64_t timeo; 528 529 /* 530 * Establish handlers for interesting interrupts.... 531 * 532 * XXX We need to remember these and remove this to support 533 * hotplug on the UPA/FHC bus. 534 * 535 * XXX Not all controllers have these, but installing them 536 * is better than trying to sort through this mess. 537 */ 538 psycho_set_intr(sc, 15, psycho_ue, 539 &sc->sc_regs->ue_int_map, 540 &sc->sc_regs->ue_clr_int); 541 psycho_set_intr(sc, 1, psycho_ce, 542 &sc->sc_regs->ce_int_map, 543 &sc->sc_regs->ce_clr_int); 544 psycho_set_intr(sc, 15, psycho_bus_a, 545 &sc->sc_regs->pciaerr_int_map, 546 &sc->sc_regs->pciaerr_clr_int); 547 /* 548 * Netra X1 may hang when the powerfail interrupt is enabled. 549 */ 550 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 551 psycho_set_intr(sc, 15, psycho_powerfail, 552 &sc->sc_regs->power_int_map, 553 &sc->sc_regs->power_clr_int); 554 psycho_register_power_button(sc); 555 } 556 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 557 /* sabre doesn't have these interrupts */ 558 psycho_set_intr(sc, 15, psycho_bus_b, 559 &sc->sc_regs->pciberr_int_map, 560 &sc->sc_regs->pciberr_clr_int); 561 psycho_set_intr(sc, 1, psycho_wakeup, 562 &sc->sc_regs->pwrmgt_int_map, 563 &sc->sc_regs->pwrmgt_clr_int); 564 } 565 566 /* 567 * Apparently a number of machines with psycho and psycho+ 568 * controllers have interrupt latency issues. We'll try 569 * setting the interrupt retry timeout to 0xff which gives us 570 * a retry of 3-6 usec (which is what sysio is set to) for the 571 * moment, which seems to help alleviate this problem. 572 */ 573 timeo = sc->sc_regs->intr_retry_timer; 574 if (timeo > 0xfff) { 575 #ifdef DEBUG 576 printf("decreasing interrupt retry timeout " 577 "from %lx to 0xff\n", (long)timeo); 578 #endif 579 sc->sc_regs->intr_retry_timer = 0xff; 580 } 581 582 /* 583 * Allocate bus node, this contains a prom node per bus. 584 */ 585 pp->pp_pc->spc_busnode = 586 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 587 M_NOWAIT | M_ZERO); 588 if (pp->pp_pc->spc_busnode == NULL) 589 panic("psycho_attach: malloc busnode"); 590 591 /* 592 * Setup IOMMU and PCI configuration if we're the first 593 * of a pair of psycho's to arrive here. 594 * 595 * We should calculate a TSB size based on amount of RAM 596 * and number of bus controllers and number an type of 597 * child devices. 598 * 599 * For the moment, 32KB should be more than enough. 600 */ 601 sc->sc_is = malloc(sizeof(struct iommu_state), 602 M_DEVBUF, M_NOWAIT); 603 if (sc->sc_is == NULL) 604 panic("psycho_attach: malloc iommu_state"); 605 606 /* Point the strbuf_ctl at the iommu_state */ 607 pp->pp_sb.sb_is = sc->sc_is; 608 609 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 610 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 611 struct strbuf_ctl *sb = &pp->pp_sb; 612 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 613 614 /* 615 * Initialize the strbuf_ctl. 616 * 617 * The flush sync buffer must be 64-byte aligned. 618 */ 619 sb->sb_flush = (void *)(va & ~0x3f); 620 621 bus_space_subregion(sc->sc_bustag, pci_ctl, 622 offsetof(struct pci_ctl, pci_strbuf), 623 sizeof (struct iommu_strbuf), &sb->sb_sb); 624 625 /* Point our iommu at the strbuf_ctl */ 626 sc->sc_is->is_sb[0] = sb; 627 } 628 629 psycho_iommu_init(sc, 2); 630 631 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 632 633 /* 634 * XXX This is a really ugly hack because PCI config space 635 * is explicitly handled with unmapped accesses. 636 */ 637 i = sc->sc_bustag->type; 638 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 639 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 640 0x01000000, 0, &bh)) 641 panic("could not map psycho PCI configuration space"); 642 sc->sc_bustag->type = i; 643 sc->sc_configaddr = bh; 644 } else { 645 /* Share bus numbers with the pair of mine */ 646 pp->pp_pc->spc_busnode = 647 osc->sc_psycho_this->pp_pc->spc_busnode; 648 649 /* Just copy IOMMU state, config tag and address */ 650 sc->sc_is = osc->sc_is; 651 sc->sc_configtag = osc->sc_configtag; 652 sc->sc_configaddr = osc->sc_configaddr; 653 654 /* Point the strbuf_ctl at the iommu_state */ 655 pp->pp_sb.sb_is = sc->sc_is; 656 657 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 658 struct strbuf_ctl *sb = &pp->pp_sb; 659 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 660 661 /* 662 * Initialize the strbuf_ctl. 663 * 664 * The flush sync buffer must be 64-byte aligned. 665 */ 666 sb->sb_flush = (void *)(va & ~0x3f); 667 668 bus_space_subregion(sc->sc_bustag, pci_ctl, 669 offsetof(struct pci_ctl, pci_strbuf), 670 sizeof (struct iommu_strbuf), &sb->sb_sb); 671 672 /* Point our iommu at the strbuf_ctl */ 673 sc->sc_is->is_sb[1] = sb; 674 } 675 iommu_reset(sc->sc_is); 676 } 677 678 dict = device_properties(self); 679 pr = get_psychorange(pp, 2); /* memory range */ 680 #ifdef DEBUG 681 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 682 #endif 683 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 684 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 685 686 /* 687 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 688 */ 689 pba.pba_flags = sc->sc_psycho_this->pp_flags; 690 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 691 pba.pba_dmat64 = NULL; 692 pba.pba_iot = sc->sc_psycho_this->pp_iot; 693 pba.pba_memt = sc->sc_psycho_this->pp_memt; 694 pba.pba_pc = pp->pp_pc; 695 696 config_found_ia(self, "pcibus", &pba, psycho_print); 697 } 698 699 static int 700 psycho_print(void *aux, const char *p) 701 { 702 703 if (p == NULL) 704 return (UNCONF); 705 return (QUIET); 706 } 707 708 static void 709 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 710 uint64_t *mapper, uint64_t *clearer) 711 { 712 struct intrhand *ih; 713 714 ih = intrhand_alloc(); 715 ih->ih_arg = sc; 716 ih->ih_map = mapper; 717 ih->ih_clr = clearer; 718 ih->ih_fun = handler; 719 ih->ih_pil = ipl; 720 ih->ih_number = INTVEC(*(ih->ih_map)); 721 ih->ih_pending = 0; 722 intr_establish(ipl, ipl != IPL_VM, ih); 723 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 724 } 725 726 /* 727 * power button handlers 728 */ 729 static void 730 psycho_register_power_button(struct psycho_softc *sc) 731 { 732 sysmon_task_queue_init(); 733 734 sc->sc_powerpressed = 0; 735 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 736 if (!sc->sc_smcontext) { 737 aprint_error_dev(sc->sc_dev, "could not allocate power button context\n"); 738 return; 739 } 740 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 741 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 742 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 743 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 744 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 745 } 746 747 static void 748 psycho_power_button_pressed(void *arg) 749 { 750 struct psycho_softc *sc = arg; 751 752 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 753 sc->sc_powerpressed = 0; 754 } 755 756 /* 757 * PCI bus support 758 */ 759 760 /* 761 * allocate a PCI chipset tag and set its cookie. 762 */ 763 static pci_chipset_tag_t 764 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 765 { 766 pci_chipset_tag_t npc; 767 768 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 769 if (npc == NULL) 770 panic("could not allocate pci_chipset_tag_t"); 771 memcpy(npc, pc, sizeof *pc); 772 npc->cookie = pp; 773 npc->rootnode = node; 774 npc->spc_conf_read = psycho_pci_conf_read; 775 npc->spc_conf_write = psycho_pci_conf_write; 776 npc->spc_intr_map = NULL; 777 npc->spc_intr_establish = psycho_pci_intr_establish; 778 npc->spc_find_ino = psycho_pci_find_ino; 779 780 return (npc); 781 } 782 783 /* 784 * create extent for free bus space, then allocate assigned regions. 785 */ 786 static struct extent * 787 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 788 { 789 struct psycho_registers *pa = NULL; 790 struct psycho_ranges *pr; 791 struct extent *ex; 792 bus_addr_t baddr, addr; 793 bus_size_t bsize, size; 794 int i, num; 795 796 /* get bus space size */ 797 pr = get_psychorange(pp, ss); 798 if (pr == NULL) { 799 printf("psycho_alloc_extent: get_psychorange failed\n"); 800 return NULL; 801 } 802 baddr = 0x00000000; 803 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 804 805 /* get available lists */ 806 num = 0; 807 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 808 printf("psycho_alloc_extent: no \"available\" property\n"); 809 return NULL; 810 } 811 812 /* create extent */ 813 ex = extent_create(name, baddr, bsize - baddr - 1, 0, 0, EX_NOWAIT); 814 if (ex == NULL) { 815 printf("psycho_alloc_extent: extent_create failed\n"); 816 goto ret; 817 } 818 819 /* allocate assigned regions */ 820 for (i = 0; i < num; i++) 821 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 822 /* allocate bus space */ 823 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 824 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 825 if (extent_alloc_region(ex, baddr, addr - baddr, 826 EX_NOWAIT)) { 827 printf("psycho_alloc_extent: " 828 "extent_alloc_region %" PRIx64 "-%" 829 PRIx64 " failed\n", baddr, addr); 830 extent_destroy(ex); 831 ex = NULL; 832 goto ret; 833 } 834 baddr = addr + size; 835 } 836 /* allocate left region if available */ 837 if (baddr < bsize) 838 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 839 printf("psycho_alloc_extent: extent_alloc_region %" 840 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 841 extent_destroy(ex); 842 ex = NULL; 843 goto ret; 844 } 845 846 #ifdef DEBUG 847 /* print extent */ 848 extent_print(ex); 849 #endif 850 851 ret: 852 /* return extent */ 853 free(pa, M_DEVBUF); 854 return ex; 855 } 856 857 /* 858 * grovel the OBP for various psycho properties 859 */ 860 static void 861 psycho_get_bus_range(int node, int *brp) 862 { 863 int n, error; 864 865 n = 2; 866 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 867 if (error) 868 panic("could not get psycho bus-range, error %d", error); 869 if (n != 2) 870 panic("broken psycho bus-range"); 871 DPRINTF(PDB_PROM, ("%s: got `bus-range' for node %08x: %u - %u\n", 872 __func__, node, brp[0], brp[1])); 873 } 874 875 static void 876 psycho_fixup_bus_range(int node0, int *brp0) 877 { 878 int node; 879 int len, busrange[2], *brp; 880 881 DPRINTF(PDB_PROM, 882 ("%s: fixing up `bus-range' for node %08x: %u - %u\n", 883 __func__, node0, brp0[0], brp0[1])); 884 885 /* 886 * Check all nodes under this one and increase the bus range to 887 * match. Recurse through PCI-PCI bridges. Cardbus bridges are 888 * fixed up in pccbb_attach_hook(). Assumes that "bus-range" for 889 * PCI-PCI bridges apart from this one is correct. 890 */ 891 brp0[1] = brp0[0]; 892 node = prom_firstchild(node0); 893 for (node = ((node)); node; node = prom_nextsibling(node)) { 894 len = 2; 895 brp = busrange; 896 if (prom_getprop(node, "bus-range", sizeof(*brp), 897 &len, &brp) != 0) 898 break; 899 if (len != 2) 900 break; 901 psycho_fixup_bus_range(node, busrange); 902 if (brp0[0] > busrange[0] && busrange[0] >= 0) 903 brp0[0] = busrange[0]; 904 if (brp0[1] < busrange[1] && busrange[1] < 256) 905 brp0[1] = busrange[1]; 906 } 907 908 DPRINTF(PDB_PROM, 909 ("%s: fixed up `bus-range' for node %08x: %u - %u\n", 910 __func__, node0, brp[0], brp[1])); 911 } 912 913 static void 914 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 915 { 916 917 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 918 panic("could not get psycho ranges"); 919 DPRINTF(PDB_PROM, ("%s: got `ranges' for node %08x: %d entries\n", 920 __func__, node, *np)); 921 } 922 923 /* 924 * Interrupt handlers. 925 */ 926 927 static int 928 psycho_ue(void *arg) 929 { 930 struct psycho_softc *sc = (struct psycho_softc *)arg; 931 struct psychoreg *regs = sc->sc_regs; 932 struct iommu_state *is = sc->sc_is; 933 uint64_t afsr = regs->psy_ue_afsr; 934 uint64_t afar = regs->psy_ue_afar; 935 psize_t size = PAGE_SIZE << is->is_tsbsize; 936 char bits[128]; 937 938 /* 939 * It's uncorrectable. Dump the regs and panic. 940 */ 941 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 942 aprint_error_dev(sc->sc_dev, 943 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 944 945 /* Sometimes the AFAR points to an IOTSB entry */ 946 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 947 aprint_error_dev(sc->sc_dev, 948 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 949 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 950 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 951 } 952 #ifdef DDB 953 Debugger(); 954 #endif 955 regs->psy_ue_afar = 0; 956 regs->psy_ue_afsr = 0; 957 return (1); 958 } 959 960 static int 961 psycho_ce(void *arg) 962 { 963 struct psycho_softc *sc = (struct psycho_softc *)arg; 964 struct psychoreg *regs = sc->sc_regs; 965 966 /* 967 * It's correctable. Dump the regs and continue. 968 */ 969 aprint_error_dev(sc->sc_dev, 970 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 971 regs->psy_ce_afar, regs->psy_ce_afsr); 972 return (1); 973 } 974 975 static int 976 psycho_bus_a(void *arg) 977 { 978 struct psycho_softc *sc = (struct psycho_softc *)arg; 979 struct psychoreg *regs = sc->sc_regs; 980 981 /* 982 * It's uncorrectable. Dump the regs and panic. 983 */ 984 985 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 986 device_xname(sc->sc_dev), 987 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 988 return (1); 989 } 990 991 static int 992 psycho_bus_b(void *arg) 993 { 994 struct psycho_softc *sc = (struct psycho_softc *)arg; 995 struct psychoreg *regs = sc->sc_regs; 996 997 /* 998 * It's uncorrectable. Dump the regs and panic. 999 */ 1000 1001 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 1002 device_xname(sc->sc_dev), 1003 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 1004 return (1); 1005 } 1006 1007 static int 1008 psycho_powerfail(void *arg) 1009 { 1010 struct psycho_softc *sc = (struct psycho_softc *)arg; 1011 1012 /* 1013 * We lost power. Queue a callback with thread context to 1014 * handle all the real work. 1015 */ 1016 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 1017 sc->sc_powerpressed = 1; 1018 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 1019 } 1020 return (1); 1021 } 1022 1023 static 1024 int psycho_wakeup(void *arg) 1025 { 1026 struct psycho_softc *sc = (struct psycho_softc *)arg; 1027 1028 /* 1029 * Gee, we don't really have a framework to deal with this 1030 * properly. 1031 */ 1032 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 1033 return (1); 1034 } 1035 1036 1037 /* 1038 * initialise the IOMMU.. 1039 */ 1040 void 1041 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 1042 { 1043 char *name; 1044 struct iommu_state *is = sc->sc_is; 1045 uint32_t iobase = -1; 1046 int *vdma = NULL; 1047 int nitem; 1048 1049 /* punch in our copies */ 1050 is->is_bustag = sc->sc_bustag; 1051 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1052 offsetof(struct psychoreg, psy_iommu), 1053 sizeof (struct iommureg), 1054 &is->is_iommu); 1055 1056 /* 1057 * Separate the men from the boys. Get the `virtual-dma' 1058 * property for sabre and use that to make sure the damn 1059 * iommu works. 1060 * 1061 * We could query the `#virtual-dma-size-cells' and 1062 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1063 */ 1064 nitem = 0; 1065 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1066 &vdma)) { 1067 /* Damn. Gotta use these values. */ 1068 iobase = vdma[0]; 1069 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1070 switch (vdma[1]) { 1071 TSBCASE(1); 1072 TSBCASE(2); 1073 TSBCASE(3); 1074 TSBCASE(4); 1075 TSBCASE(5); 1076 TSBCASE(6); 1077 TSBCASE(7); 1078 default: 1079 printf("bogus tsb size %x, using 7\n", vdma[1]); 1080 tsbsize = 7; 1081 } 1082 #undef TSBCASE 1083 } 1084 1085 /* give us a nice name.. */ 1086 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1087 if (name == 0) 1088 panic("couldn't malloc iommu name"); 1089 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 1090 1091 iommu_init(name, is, tsbsize, iobase); 1092 } 1093 1094 /* 1095 * below here is bus space and bus DMA support 1096 */ 1097 bus_space_tag_t 1098 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1099 { 1100 struct psycho_softc *sc = pp->pp_sc; 1101 bus_space_tag_t bt; 1102 1103 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1104 M_DEVBUF, M_NOWAIT | M_ZERO); 1105 if (bt == NULL) 1106 panic("could not allocate psycho bus tag"); 1107 1108 bt->cookie = pp; 1109 bt->parent = sc->sc_bustag; 1110 bt->type = type; 1111 bt->sparc_bus_map = _psycho_bus_map; 1112 bt->sparc_bus_mmap = psycho_bus_mmap; 1113 bt->sparc_intr_establish = psycho_intr_establish; 1114 return (bt); 1115 } 1116 1117 bus_dma_tag_t 1118 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1119 { 1120 struct psycho_softc *sc = pp->pp_sc; 1121 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1122 1123 dt = (bus_dma_tag_t) 1124 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1125 if (dt == NULL) 1126 panic("could not allocate psycho DMA tag"); 1127 1128 memset(dt, 0, sizeof *dt); 1129 dt->_cookie = pp; 1130 dt->_parent = pdt; 1131 #define PCOPY(x) dt->x = pdt->x 1132 dt->_dmamap_create = psycho_dmamap_create; 1133 PCOPY(_dmamap_destroy); 1134 dt->_dmamap_load = iommu_dvmamap_load; 1135 PCOPY(_dmamap_load_mbuf); 1136 PCOPY(_dmamap_load_uio); 1137 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1138 dt->_dmamap_unload = iommu_dvmamap_unload; 1139 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1140 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1141 else 1142 dt->_dmamap_sync = iommu_dvmamap_sync; 1143 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1144 dt->_dmamem_free = iommu_dvmamem_free; 1145 dt->_dmamem_map = iommu_dvmamem_map; 1146 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1147 PCOPY(_dmamem_mmap); 1148 #undef PCOPY 1149 return (dt); 1150 } 1151 1152 /* 1153 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1154 * PCI physical addresses. 1155 */ 1156 1157 static struct psycho_ranges * 1158 get_psychorange(struct psycho_pbm *pp, int ss) 1159 { 1160 int i; 1161 1162 for (i = 0; i < pp->pp_nrange; i++) { 1163 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1164 return (&pp->pp_range[i]); 1165 } 1166 /* not found */ 1167 return (NULL); 1168 } 1169 1170 static int 1171 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1172 int flags, vaddr_t unused, bus_space_handle_t *hp) 1173 { 1174 struct psycho_pbm *pp = t->cookie; 1175 struct psycho_softc *sc = pp->pp_sc; 1176 struct psycho_ranges *pr; 1177 bus_addr_t paddr; 1178 int ss; 1179 1180 DPRINTF(PDB_BUSMAP, 1181 ("%s: type %d off %qx sz %qx flags %d", 1182 __func__, t->type, (unsigned long long)offset, 1183 (unsigned long long)size, flags)); 1184 1185 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1186 1187 ss = sparc_pci_childspace(t->type); 1188 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1189 1190 pr = get_psychorange(pp, ss); 1191 if (pr != NULL) { 1192 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1193 DPRINTF(PDB_BUSMAP, ("\n%s: mapping paddr " 1194 "space %lx offset %lx paddr %qx\n", 1195 __func__, (long)ss, (long)offset, 1196 (unsigned long long)paddr)); 1197 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1198 flags, 0, hp)); 1199 } 1200 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1201 return (EINVAL); 1202 } 1203 1204 static paddr_t 1205 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1206 int flags) 1207 { 1208 bus_addr_t offset = paddr; 1209 struct psycho_pbm *pp = t->cookie; 1210 struct psycho_softc *sc = pp->pp_sc; 1211 struct psycho_ranges *pr; 1212 int ss; 1213 1214 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1215 1216 ss = sparc_pci_childspace(t->type); 1217 1218 DPRINTF(PDB_BUSMAP, ("%s: prot %x flags %d busaddr %qx\n", 1219 __func__, prot, flags, (unsigned long long)paddr)); 1220 1221 pr = get_psychorange(pp, ss); 1222 if (pr != NULL) { 1223 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1224 DPRINTF(PDB_BUSMAP, ("%s: mapping paddr " 1225 "space %lx offset %lx paddr %qx\n", 1226 __func__, (long)ss, (long)offset, 1227 (unsigned long long)paddr)); 1228 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1229 prot, flags)); 1230 } 1231 1232 return (-1); 1233 } 1234 1235 /* 1236 * Get a PCI offset address from bus_space_handle_t. 1237 */ 1238 bus_addr_t 1239 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1240 { 1241 struct psycho_pbm *pp = t->cookie; 1242 struct psycho_ranges *pr; 1243 bus_addr_t addr, offset; 1244 vaddr_t va; 1245 int ss; 1246 1247 addr = hp->_ptr; 1248 ss = sparc_pci_childspace(t->type); 1249 DPRINTF(PDB_BUSMAP, ("%s: type %d addr %" PRIx64" cspace %d", 1250 __func__, t->type, addr, ss)); 1251 1252 pr = get_psychorange(pp, ss); 1253 if (pr != NULL) { 1254 if (!PHYS_ASI(hp->_asi)) { 1255 va = trunc_page((vaddr_t)addr); 1256 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1257 DPRINTF(PDB_BUSMAP, 1258 ("- pmap_extract FAILED\n")); 1259 return (-1); 1260 } 1261 addr += hp->_ptr & PGOFSET; 1262 } 1263 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1264 DPRINTF(PDB_BUSMAP, ("- paddr %" PRIx64" offset %" PRIx64 "\n", 1265 addr, offset)); 1266 return (offset); 1267 } 1268 DPRINTF(PDB_BUSMAP, ("- FAILED\n")); 1269 return (-1); 1270 } 1271 1272 1273 /* 1274 * install an interrupt handler for a PCI device 1275 */ 1276 void * 1277 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1278 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1279 { 1280 struct psycho_pbm *pp = t->cookie; 1281 struct psycho_softc *sc = pp->pp_sc; 1282 struct intrhand *ih; 1283 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1284 int64_t imap = 0; 1285 int ino; 1286 long vec = INTVEC(ihandle); 1287 1288 ih = intrhand_alloc(); 1289 1290 ih->ih_ivec = ihandle; 1291 1292 /* 1293 * Hunt through all the interrupt mapping regs to look for our 1294 * interrupt vector. 1295 * 1296 * XXX We only compare INOs rather than IGNs since the firmware may 1297 * not provide the IGN and the IGN is constant for all device on that 1298 * PCI controller. This could cause problems for the FFB/external 1299 * interrupt which has a full vector that can be set arbitrarily. 1300 */ 1301 1302 DPRINTF(PDB_INTR, ("%s: ihandle %x vec %lx", __func__, ihandle, vec)); 1303 ino = INTINO(vec); 1304 DPRINTF(PDB_INTR, (" ino %x\n", ino)); 1305 1306 /* If the device didn't ask for an IPL, use the one encoded. */ 1307 if (level == IPL_NONE) level = INTLEV(vec); 1308 /* If it still has no level, print a warning and assign IPL 2 */ 1309 if (level == IPL_NONE) { 1310 printf("ERROR: no IPL, setting IPL 2.\n"); 1311 level = 2; 1312 } 1313 1314 DPRINTF(PDB_INTR, ("%s: intr %lx: %p\nHunting for IRQ...\n", 1315 __func__, (long)ino, intrlev[ino])); 1316 1317 /* 1318 * First look for PCI interrupts, otherwise the PCI A slot 0 1319 * INTA# interrupt might match an unused non-PCI (obio) 1320 * interrupt. 1321 */ 1322 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1323 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1324 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1325 intrmapptr++, intrclrptr += 4) { 1326 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1327 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1328 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1329 continue; 1330 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1331 intrclrptr += vec & 0x3; 1332 goto found; 1333 } 1334 } 1335 1336 /* Now hunt thru obio. */ 1337 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1338 intrclrptr = &sc->sc_regs->scsi_clr_int; 1339 intrmapptr < &sc->sc_regs->ue_int_map; 1340 intrmapptr++, intrclrptr++) { 1341 if (INTINO(*intrmapptr) == ino) 1342 goto found; 1343 } 1344 1345 /* Finally check the two FFB slots */ 1346 intrclrptr = NULL; /* XXX? */ 1347 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1348 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1349 intrmapptr++) { 1350 if (INTVEC(*intrmapptr) == ino) 1351 goto found; 1352 } 1353 1354 printf("Cannot find interrupt vector %lx\n", vec); 1355 free(ih, M_DEVBUF); 1356 return (NULL); 1357 1358 found: 1359 /* Register the map and clear intr registers */ 1360 ih->ih_map = intrmapptr; 1361 ih->ih_clr = intrclrptr; 1362 1363 ih->ih_fun = handler; 1364 ih->ih_arg = arg; 1365 ih->ih_pil = level; 1366 ih->ih_number = ino | sc->sc_ign; 1367 ih->ih_pending = 0; 1368 1369 DPRINTF(PDB_INTR, ( 1370 "%s: installing handler %p arg %p with ino %u pil %u\n", 1371 __func__, handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1372 1373 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1374 1375 /* 1376 * Enable the interrupt now we have the handler installed. 1377 * Read the current value as we can't change it besides the 1378 * valid bit so so make sure only this bit is changed. 1379 * 1380 * XXXX --- we really should use bus_space for this. 1381 */ 1382 if (intrmapptr) { 1383 imap = *intrmapptr; 1384 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", 1385 __func__, (unsigned long long)imap)); 1386 1387 /* Enable the interrupt */ 1388 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1389 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1390 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1391 (unsigned long long)imap)); 1392 *intrmapptr = imap; 1393 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx\n", 1394 (unsigned long long)(imap = *intrmapptr))); 1395 } 1396 if (intrclrptr) { 1397 /* set state to IDLE */ 1398 *intrclrptr = 0; 1399 } 1400 return (ih); 1401 } 1402 1403 /* 1404 * per-controller driver calls 1405 */ 1406 1407 /* assume we are mapped little-endian/side-effect */ 1408 static pcireg_t 1409 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1410 { 1411 struct psycho_pbm *pp = pc->cookie; 1412 struct psycho_softc *sc = pp->pp_sc; 1413 struct cpu_info *ci = curcpu(); 1414 pcireg_t val = (pcireg_t)~0; 1415 int s; 1416 1417 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1418 (long)tag, reg)); 1419 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 1420 1421 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1422 sc->sc_configaddr._asi, 1423 (long long)(sc->sc_configaddr._ptr + 1424 PCITAG_OFFSET(tag) + reg), 1425 (int)PCITAG_OFFSET(tag) + reg)); 1426 1427 s = splhigh(); 1428 ci->ci_pci_probe = true; 1429 membar_Sync(); 1430 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1431 PCITAG_OFFSET(tag) + reg); 1432 membar_Sync(); 1433 if (ci->ci_pci_fault) 1434 val = (pcireg_t)~0; 1435 ci->ci_pci_probe = ci->ci_pci_fault = false; 1436 splx(s); 1437 } 1438 #ifdef DEBUG 1439 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x -", __func__, 1440 (int)PCITAG_OFFSET(tag))); 1441 #endif 1442 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1443 1444 return (val); 1445 } 1446 1447 static void 1448 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1449 { 1450 struct psycho_pbm *pp = pc->cookie; 1451 struct psycho_softc *sc = pp->pp_sc; 1452 1453 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1454 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1455 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1456 sc->sc_configaddr._asi, 1457 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1458 (int)PCITAG_OFFSET(tag) + reg)); 1459 1460 /* If we don't know it, just punt it. */ 1461 if (PCITAG_NODE(tag) == -1) { 1462 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1463 return; 1464 } 1465 1466 if ((unsigned int)reg >= PCI_CONF_SIZE) 1467 return; 1468 1469 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1470 PCITAG_OFFSET(tag) + reg, data); 1471 } 1472 1473 static void * 1474 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1475 int (*func)(void *), void *arg) 1476 { 1477 void *cookie; 1478 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1479 1480 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1481 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1482 1483 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1484 return (cookie); 1485 } 1486 1487 static int 1488 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1489 { 1490 struct psycho_pbm *pp = pa->pa_pc->cookie; 1491 struct psycho_softc *sc = pp->pp_sc; 1492 u_int bus; 1493 u_int dev; 1494 u_int pin; 1495 1496 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1497 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1498 (int)PCITAG_DEV(pa->pa_tag), 1499 (int)PCITAG_FUN(pa->pa_tag))); 1500 DPRINTF(PDB_INTMAP, 1501 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1502 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1503 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1504 PCITAG_NODE(pa->pa_intrtag), 1505 (int)PCITAG_BUS(pa->pa_intrtag), 1506 (int)PCITAG_DEV(pa->pa_intrtag), 1507 (int)PCITAG_FUN(pa->pa_intrtag))); 1508 1509 bus = (pp->pp_id == PSYCHO_PBM_B); 1510 /* 1511 * If we are on a ppb, use the devno on the underlying bus when forming 1512 * the ivec. 1513 */ 1514 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1515 dev = PCITAG_DEV(pa->pa_intrtag); 1516 else 1517 dev = pa->pa_device; 1518 dev--; 1519 1520 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1521 pp->pp_id == PSYCHO_PBM_B) 1522 dev--; 1523 1524 pin = pa->pa_intrpin - 1; 1525 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1526 sc->sc_mode, pp->pp_id, dev, pin)); 1527 1528 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1529 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1530 1531 return (0); 1532 } 1533 1534 /* 1535 * hooks into the iommu dvma calls. 1536 */ 1537 static int 1538 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1539 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1540 bus_dmamap_t *dmamp) 1541 { 1542 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1543 int error; 1544 1545 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1546 boundary, flags, dmamp); 1547 if (error == 0) 1548 (*dmamp)->_dm_cookie = &pp->pp_sb; 1549 return error; 1550 } 1551 1552 /* 1553 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1554 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1555 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1556 */ 1557 static void 1558 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1559 bus_size_t len, int ops) 1560 { 1561 struct psycho_pbm *pp; 1562 struct psycho_softc *sc; 1563 1564 /* If len is 0, then there is nothing to do. */ 1565 if (len == 0) 1566 return; 1567 1568 if (ops & BUS_DMASYNC_POSTREAD) { 1569 pp = (struct psycho_pbm *)t->_cookie; 1570 sc = pp->pp_sc; 1571 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1572 offsetof(struct psychoreg, pci_dma_write_sync)); 1573 } 1574 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1575 } 1576 1577 /* US-IIe STICK support */ 1578 1579 uint64_t 1580 psycho_getstick(void) 1581 { 1582 uint64_t stick; 1583 1584 stick = bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1585 STICK_CNT_LOW) | 1586 (bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1587 STICK_CNT_HIGH) & 0x7fffffff) << 32; 1588 return stick; 1589 } 1590 1591 uint32_t 1592 psycho_getstick32(void) 1593 { 1594 1595 return bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1596 STICK_CNT_LOW); 1597 } 1598 1599 void 1600 psycho_setstick(long cnt) 1601 { 1602 1603 /* 1604 * looks like we can't actually write the STICK counter, so instead we 1605 * prepare sc_last_stick for the coming interrupt setup 1606 */ 1607 #if 0 1608 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1609 STICK_CNT_HIGH, (cnt >> 32)); 1610 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1611 STICK_CNT_LOW, (uint32_t)(cnt & 0xffffffff)); 1612 #endif 1613 1614 if (cnt == 0) { 1615 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1616 STICK_CMP_HIGH, 0); 1617 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1618 STICK_CMP_LOW, 0); 1619 psycho0->sc_last_stick = 0; 1620 } 1621 1622 psycho0->sc_last_stick = psycho_getstick(); 1623 DPRINTF(PDB_STICK, ("%s: %ld\n", __func__, psycho0->sc_last_stick)); 1624 } 1625 1626 void 1627 psycho_nextstick(long diff) 1628 { 1629 uint64_t cmp, now; 1630 1631 /* 1632 * there is no way we'll ever overflow 1633 * the counter is 63 bits wide, at 12MHz that's >24000 years 1634 */ 1635 now = psycho_getstick() + 1000; 1636 cmp = psycho0->sc_last_stick; 1637 1638 while (cmp < now) 1639 cmp += diff; 1640 1641 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1642 STICK_CMP_HIGH, (cmp >> 32) & 0x7fffffff); 1643 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1644 STICK_CMP_LOW, (cmp & 0xffffffff)); 1645 1646 psycho0->sc_last_stick = cmp; 1647 } 1648