1 /* $NetBSD: psycho.c,v 1.63 2003/06/15 23:09:06 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "opt_ddb.h" 33 34 /* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39 #ifdef DEBUG 40 #define PDB_PROM 0x01 41 #define PDB_BUSMAP 0x02 42 #define PDB_INTR 0x04 43 int psycho_debug = 0x0; 44 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 45 #else 46 #define DPRINTF(l, s) 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/systm.h> 55 #include <sys/time.h> 56 #include <sys/reboot.h> 57 58 #include <uvm/uvm.h> 59 60 #define _SPARC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/autoconf.h> 63 #include <machine/psl.h> 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/sysmon/sysmon_taskq.h> 68 69 #include <sparc64/dev/iommureg.h> 70 #include <sparc64/dev/iommuvar.h> 71 #include <sparc64/dev/psychoreg.h> 72 #include <sparc64/dev/psychovar.h> 73 #include <sparc64/sparc64/cache.h> 74 75 #include "ioconf.h" 76 77 static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int, 78 pci_chipset_tag_t)); 79 static struct extent *psycho_alloc_extent __P((struct psycho_pbm *, int, int, 80 char *)); 81 static void psycho_get_bus_range __P((int, int *)); 82 static void psycho_get_ranges __P((int, struct psycho_ranges **, int *)); 83 static void psycho_set_intr __P((struct psycho_softc *, int, void *, 84 u_int64_t *, u_int64_t *)); 85 86 /* Interrupt handlers */ 87 static int psycho_ue __P((void *)); 88 static int psycho_ce __P((void *)); 89 static int psycho_bus_a __P((void *)); 90 static int psycho_bus_b __P((void *)); 91 static int psycho_powerfail __P((void *)); 92 static int psycho_wakeup __P((void *)); 93 94 95 /* IOMMU support */ 96 static void psycho_iommu_init __P((struct psycho_softc *, int)); 97 98 /* 99 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 100 * of the bus DMA support is provided by the iommu dvma controller. 101 */ 102 static int get_childspace __P((int)); 103 static struct psycho_ranges *get_psychorange __P((struct psycho_pbm *, int)); 104 105 static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 106 int, int)); 107 static int _psycho_bus_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, 108 vaddr_t, bus_space_handle_t *)); 109 static void *psycho_intr_establish __P((bus_space_tag_t, int, int, 110 int (*) __P((void *)), void *, void(*)__P((void)))); 111 112 static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 113 bus_size_t, struct proc *, int)); 114 static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 115 static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 116 bus_dma_segment_t *, int, bus_size_t, int)); 117 static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 118 bus_size_t, int)); 119 int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 120 bus_dma_segment_t *, int, int *, int)); 121 void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 122 int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 123 caddr_t *, int)); 124 void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 125 126 /* base pci_chipset */ 127 extern struct sparc_pci_chipset _sparc_pci_chipset; 128 129 /* power button handlers */ 130 static void psycho_register_power_button(struct psycho_softc *sc); 131 static void psycho_power_button_pressed(void *arg); 132 133 /* 134 * autoconfiguration 135 */ 136 static int psycho_match __P((struct device *, struct cfdata *, void *)); 137 static void psycho_attach __P((struct device *, struct device *, void *)); 138 static int psycho_print __P((void *aux, const char *p)); 139 140 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 141 psycho_match, psycho_attach, NULL, NULL); 142 143 /* 144 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 145 * single PCI bus and does not have a streaming buffer. It often has an APB 146 * (advanced PCI bridge) connected to it, which was designed specifically for 147 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 148 * appears as two "simba"'s underneath the sabre. 149 * 150 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 151 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 152 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 153 * will usually find a "psycho+" since I don't think the original "psycho" 154 * ever shipped, and if it did it would be in the U30. 155 * 156 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 157 * both part of the same IC, they only have a single register space. As such, 158 * they need to be configured together, even though the autoconfiguration will 159 * attach them separately. 160 * 161 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 162 * as pci1 and pci2, although they have been implemented with other PCI bus 163 * numbers on some machines. 164 * 165 * On UltraII machines, there can be any number of "psycho+" ICs, each 166 * providing two PCI buses. 167 * 168 * 169 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 170 * the values of the following interrupts in this order: 171 * 172 * PCI Bus Error (30) 173 * DMA UE (2e) 174 * DMA CE (2f) 175 * Power Fail (25) 176 * 177 * We really should attach handlers for each. 178 * 179 */ 180 181 #define ROM_PCI_NAME "pci" 182 183 struct psycho_names { 184 char *p_name; 185 int p_type; 186 } psycho_names[] = { 187 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 188 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 189 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 190 { "pci108e,a000", PSYCHO_MODE_SABRE }, 191 { "pci108e,a001", PSYCHO_MODE_SABRE }, 192 { NULL, 0 } 193 }; 194 195 static int 196 psycho_match(parent, match, aux) 197 struct device *parent; 198 struct cfdata *match; 199 void *aux; 200 { 201 struct mainbus_attach_args *ma = aux; 202 char *model = PROM_getpropstring(ma->ma_node, "model"); 203 int i; 204 205 /* match on a name of "pci" and a sabre or a psycho */ 206 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 207 for (i=0; psycho_names[i].p_name; i++) 208 if (strcmp(model, psycho_names[i].p_name) == 0) 209 return (1); 210 211 model = PROM_getpropstring(ma->ma_node, "compatible"); 212 for (i=0; psycho_names[i].p_name; i++) 213 if (strcmp(model, psycho_names[i].p_name) == 0) 214 return (1); 215 } 216 return (0); 217 } 218 219 /* 220 * SUNW,psycho initialisation .. 221 * - find the per-psycho registers 222 * - figure out the IGN. 223 * - find our partner psycho 224 * - configure ourselves 225 * - bus range, bus, 226 * - get interrupt-map and interrupt-map-mask 227 * - setup the chipsets. 228 * - if we're the first of the pair, initialise the IOMMU, otherwise 229 * just copy it's tags and addresses. 230 */ 231 static void 232 psycho_attach(parent, self, aux) 233 struct device *parent, *self; 234 void *aux; 235 { 236 struct psycho_softc *sc = (struct psycho_softc *)self; 237 struct psycho_softc *osc = NULL; 238 struct psycho_pbm *pp; 239 struct pcibus_attach_args pba; 240 struct mainbus_attach_args *ma = aux; 241 bus_space_handle_t bh; 242 u_int64_t csr; 243 int psycho_br[2], n, i; 244 bus_space_handle_t pci_ctl; 245 char *model = PROM_getpropstring(ma->ma_node, "model"); 246 247 printf("\n"); 248 249 sc->sc_node = ma->ma_node; 250 sc->sc_bustag = ma->ma_bustag; 251 sc->sc_dmatag = ma->ma_dmatag; 252 253 /* 254 * Identify the device. 255 */ 256 for (i=0; psycho_names[i].p_name; i++) 257 if (strcmp(model, psycho_names[i].p_name) == 0) { 258 sc->sc_mode = psycho_names[i].p_type; 259 goto found; 260 } 261 262 model = PROM_getpropstring(ma->ma_node, "compatible"); 263 for (i=0; psycho_names[i].p_name; i++) 264 if (strcmp(model, psycho_names[i].p_name) == 0) { 265 sc->sc_mode = psycho_names[i].p_type; 266 goto found; 267 } 268 269 panic("unknown psycho model %s", model); 270 found: 271 272 /* 273 * The psycho gets three register banks: 274 * (0) per-PBM configuration and status registers 275 * (1) per-PBM PCI configuration space, containing only the 276 * PBM 256-byte PCI header 277 * (2) the shared psycho configuration registers (struct psychoreg) 278 */ 279 280 /* Register layouts are different. stuupid. */ 281 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 282 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 283 284 if (ma->ma_naddress > 2) { 285 sparc_promaddr_to_handle(sc->sc_bustag, 286 ma->ma_address[2], &sc->sc_bh); 287 sparc_promaddr_to_handle(sc->sc_bustag, 288 ma->ma_address[0], &pci_ctl); 289 290 sc->sc_regs = (struct psychoreg *) 291 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 292 } else if (ma->ma_nreg > 2) { 293 294 /* We need to map this in ourselves. */ 295 if (bus_space_map(sc->sc_bustag, 296 ma->ma_reg[2].ur_paddr, 297 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 298 &sc->sc_bh)) 299 panic("psycho_attach: cannot map regs"); 300 sc->sc_regs = (struct psychoreg *) 301 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 302 303 if (bus_space_map(sc->sc_bustag, 304 ma->ma_reg[0].ur_paddr, 305 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 306 &pci_ctl)) 307 panic("psycho_attach: cannot map ctl"); 308 } else 309 panic("psycho_attach: %d not enough registers", 310 ma->ma_nreg); 311 } else { 312 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 313 314 if (ma->ma_naddress) { 315 sparc_promaddr_to_handle(sc->sc_bustag, 316 ma->ma_address[0], &sc->sc_bh); 317 sc->sc_regs = (struct psychoreg *) 318 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 319 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 320 offsetof(struct psychoreg, psy_pcictl), 321 sizeof(struct pci_ctl), &pci_ctl); 322 } else if (ma->ma_nreg) { 323 324 /* We need to map this in ourselves. */ 325 if (bus_space_map(sc->sc_bustag, 326 ma->ma_reg[0].ur_paddr, 327 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 328 &sc->sc_bh)) 329 panic("psycho_attach: cannot map regs"); 330 sc->sc_regs = (struct psychoreg *) 331 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 332 333 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 334 offsetof(struct psychoreg, psy_pcictl), 335 sizeof(struct pci_ctl), &pci_ctl); 336 } else 337 panic("psycho_attach: %d not enough registers", 338 ma->ma_nreg); 339 } 340 341 342 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 343 offsetof(struct psychoreg, psy_csr)); 344 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 345 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 346 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 347 348 printf("%s: impl %d, version %d: ign %x ", 349 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 350 sc->sc_ign); 351 /* 352 * Match other psycho's that are already configured against 353 * the base physical address. This will be the same for a 354 * pair of devices that share register space. 355 */ 356 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 357 358 struct psycho_softc *asc = 359 (struct psycho_softc *)psycho_cd.cd_devs[n]; 360 361 if (asc == NULL || asc == sc) 362 /* This entry is not there or it is me */ 363 continue; 364 365 if (asc->sc_basepaddr != sc->sc_basepaddr) 366 /* This is an unrelated psycho */ 367 continue; 368 369 /* Found partner */ 370 osc = asc; 371 break; 372 } 373 374 375 /* Oh, dear. OK, lets get started */ 376 377 /* 378 * Setup the PCI control register 379 */ 380 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 381 offsetof(struct pci_ctl, pci_csr)); 382 csr |= PCICTL_MRLM | 383 PCICTL_ARB_PARK | 384 PCICTL_ERRINTEN | 385 PCICTL_4ENABLE; 386 csr &= ~(PCICTL_SERR | 387 PCICTL_CPU_PRIO | 388 PCICTL_ARB_PRIO | 389 PCICTL_RTRYWAIT); 390 bus_space_write_8(sc->sc_bustag, pci_ctl, 391 offsetof(struct pci_ctl, pci_csr), csr); 392 393 394 /* 395 * Allocate our psycho_pbm 396 */ 397 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 398 M_NOWAIT | M_ZERO); 399 if (pp == NULL) 400 panic("could not allocate psycho pbm"); 401 402 pp->pp_sc = sc; 403 404 /* grab the psycho ranges */ 405 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 406 407 /* get the bus-range for the psycho */ 408 psycho_get_bus_range(sc->sc_node, psycho_br); 409 410 pba.pba_bus = psycho_br[0]; 411 pba.pba_bridgetag = NULL; 412 pp->pp_busmax = psycho_br[1]; 413 414 printf("bus range %u to %u", psycho_br[0], psycho_br[1]); 415 printf("; PCI bus %d", psycho_br[0]); 416 417 pp->pp_pcictl = pci_ctl; 418 419 /* allocate our tags */ 420 pp->pp_memt = psycho_alloc_mem_tag(pp); 421 pp->pp_iot = psycho_alloc_io_tag(pp); 422 pp->pp_dmat = psycho_alloc_dma_tag(pp); 423 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 424 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 425 426 /* allocate a chipset for this */ 427 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 428 429 /* setup the rest of the psycho pbm */ 430 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 431 432 printf("\n"); 433 434 /* allocate extents for free bus space */ 435 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 436 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 437 438 /* 439 * And finally, if we're a sabre or the first of a pair of psycho's to 440 * arrive here, start up the IOMMU and get a config space tag. 441 */ 442 if (osc == NULL) { 443 uint64_t timeo; 444 445 /* 446 * Establish handlers for interesting interrupts.... 447 * 448 * XXX We need to remember these and remove this to support 449 * hotplug on the UPA/FHC bus. 450 * 451 * XXX Not all controllers have these, but installing them 452 * is better than trying to sort through this mess. 453 */ 454 psycho_set_intr(sc, 15, psycho_ue, 455 &sc->sc_regs->ue_int_map, 456 &sc->sc_regs->ue_clr_int); 457 psycho_set_intr(sc, 1, psycho_ce, 458 &sc->sc_regs->ce_int_map, 459 &sc->sc_regs->ce_clr_int); 460 psycho_set_intr(sc, 15, psycho_bus_a, 461 &sc->sc_regs->pciaerr_int_map, 462 &sc->sc_regs->pciaerr_clr_int); 463 psycho_set_intr(sc, 15, psycho_bus_b, 464 &sc->sc_regs->pciberr_int_map, 465 &sc->sc_regs->pciberr_clr_int); 466 psycho_set_intr(sc, 15, psycho_powerfail, 467 &sc->sc_regs->power_int_map, 468 &sc->sc_regs->power_clr_int); 469 psycho_register_power_button(sc); 470 psycho_set_intr(sc, 1, psycho_wakeup, 471 &sc->sc_regs->pwrmgt_int_map, 472 &sc->sc_regs->pwrmgt_clr_int); 473 474 475 /* 476 * Apparently a number of machines with psycho and psycho+ 477 * controllers have interrupt latency issues. We'll try 478 * setting the interrupt retry timeout to 0xff which gives us 479 * a retry of 3-6 usec (which is what sysio is set to) for the 480 * moment, which seems to help alleviate this problem. 481 */ 482 timeo = sc->sc_regs->intr_retry_timer; 483 if (timeo > 0xfff) { 484 #ifdef DEBUG 485 printf("decreasing interrupt retry timeout " 486 "from %lx to 0xff\n", (long)timeo); 487 #endif 488 sc->sc_regs->intr_retry_timer = 0xff; 489 } 490 491 /* 492 * Allocate bus node, this contains a prom node per bus. 493 */ 494 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 495 M_NOWAIT | M_ZERO); 496 if (pp->pp_busnode == NULL) 497 panic("psycho_attach: malloc pp->pp_busnode"); 498 499 /* 500 * Setup IOMMU and PCI configuration if we're the first 501 * of a pair of psycho's to arrive here. 502 * 503 * We should calculate a TSB size based on amount of RAM 504 * and number of bus controllers and number an type of 505 * child devices. 506 * 507 * For the moment, 32KB should be more than enough. 508 */ 509 sc->sc_is = malloc(sizeof(struct iommu_state), 510 M_DEVBUF, M_NOWAIT); 511 if (sc->sc_is == NULL) 512 panic("psycho_attach: malloc iommu_state"); 513 514 /* Point the strbuf_ctl at the iommu_state */ 515 pp->pp_sb.sb_is = sc->sc_is; 516 517 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 518 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 519 struct strbuf_ctl *sb = &pp->pp_sb; 520 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 521 522 /* 523 * Initialize the strbuf_ctl. 524 * 525 * The flush sync buffer must be 64-byte aligned. 526 */ 527 sb->sb_flush = (void *)(va & ~0x3f); 528 529 bus_space_subregion(sc->sc_bustag, pci_ctl, 530 offsetof(struct pci_ctl, pci_strbuf), 531 sizeof (struct iommu_strbuf), &sb->sb_sb); 532 533 /* Point our iommu at the strbuf_ctl */ 534 sc->sc_is->is_sb[0] = sb; 535 } 536 537 psycho_iommu_init(sc, 2); 538 539 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 540 541 /* 542 * XXX This is a really ugly hack because PCI config space 543 * is explicitly handled with unmapped accesses. 544 */ 545 i = sc->sc_bustag->type; 546 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 547 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 548 0x01000000, 0, &bh)) 549 panic("could not map psycho PCI configuration space"); 550 sc->sc_bustag->type = i; 551 sc->sc_configaddr = bh; 552 } else { 553 /* Share bus numbers with the pair of mine */ 554 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 555 556 /* Just copy IOMMU state, config tag and address */ 557 sc->sc_is = osc->sc_is; 558 sc->sc_configtag = osc->sc_configtag; 559 sc->sc_configaddr = osc->sc_configaddr; 560 561 /* Point the strbuf_ctl at the iommu_state */ 562 pp->pp_sb.sb_is = sc->sc_is; 563 564 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 565 struct strbuf_ctl *sb = &pp->pp_sb; 566 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 567 568 /* 569 * Initialize the strbuf_ctl. 570 * 571 * The flush sync buffer must be 64-byte aligned. 572 */ 573 sb->sb_flush = (void *)(va & ~0x3f); 574 575 bus_space_subregion(sc->sc_bustag, pci_ctl, 576 offsetof(struct pci_ctl, pci_strbuf), 577 sizeof (struct iommu_strbuf), &sb->sb_sb); 578 579 /* Point our iommu at the strbuf_ctl */ 580 sc->sc_is->is_sb[1] = sb; 581 } 582 iommu_reset(sc->sc_is); 583 } 584 585 /* 586 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 587 */ 588 pba.pba_busname = "pci"; 589 pba.pba_flags = sc->sc_psycho_this->pp_flags; 590 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 591 pba.pba_dmat64 = NULL; 592 pba.pba_iot = sc->sc_psycho_this->pp_iot; 593 pba.pba_memt = sc->sc_psycho_this->pp_memt; 594 595 config_found(self, &pba, psycho_print); 596 } 597 598 static int 599 psycho_print(aux, p) 600 void *aux; 601 const char *p; 602 { 603 604 if (p == NULL) 605 return (UNCONF); 606 return (QUIET); 607 } 608 609 static void 610 psycho_set_intr(sc, ipl, handler, mapper, clearer) 611 struct psycho_softc *sc; 612 int ipl; 613 void *handler; 614 u_int64_t *mapper; 615 u_int64_t *clearer; 616 { 617 struct intrhand *ih; 618 619 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 620 M_DEVBUF, M_NOWAIT); 621 ih->ih_arg = sc; 622 ih->ih_map = mapper; 623 ih->ih_clr = clearer; 624 ih->ih_fun = handler; 625 ih->ih_pil = (1<<ipl); 626 ih->ih_number = INTVEC(*(ih->ih_map)); 627 intr_establish(ipl, ih); 628 *(ih->ih_map) |= INTMAP_V; 629 } 630 631 /* 632 * power button handlers 633 */ 634 static void 635 psycho_register_power_button(struct psycho_softc *sc) 636 { 637 sysmon_task_queue_init(); 638 639 sc->sc_powerpressed = 0; 640 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 641 if (!sc->sc_smcontext) { 642 printf("%s: could not allocate power button context\n", 643 sc->sc_dev.dv_xname); 644 return; 645 } 646 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 647 sc->sc_smcontext->smpsw_name = sc->sc_dev.dv_xname; 648 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 649 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 650 printf("%s: unable to register power button with sysmon\n", 651 sc->sc_dev.dv_xname); 652 } 653 654 static void 655 psycho_power_button_pressed(void *arg) 656 { 657 struct psycho_softc *sc = arg; 658 659 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 660 sc->sc_powerpressed = 0; 661 } 662 663 /* 664 * PCI bus support 665 */ 666 667 /* 668 * allocate a PCI chipset tag and set it's cookie. 669 */ 670 static pci_chipset_tag_t 671 psycho_alloc_chipset(pp, node, pc) 672 struct psycho_pbm *pp; 673 int node; 674 pci_chipset_tag_t pc; 675 { 676 pci_chipset_tag_t npc; 677 678 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 679 if (npc == NULL) 680 panic("could not allocate pci_chipset_tag_t"); 681 memcpy(npc, pc, sizeof *pc); 682 npc->cookie = pp; 683 npc->rootnode = node; 684 685 return (npc); 686 } 687 688 /* 689 * create extent for free bus space, then allocate assigned regions. 690 */ 691 static struct extent * 692 psycho_alloc_extent(pp, node, ss, name) 693 struct psycho_pbm *pp; 694 int node; 695 int ss; 696 char *name; 697 { 698 struct psycho_registers *pa = NULL; 699 struct psycho_ranges *pr; 700 struct extent *ex; 701 bus_addr_t baddr, addr; 702 bus_size_t bsize, size; 703 int i, num; 704 705 /* get bus space size */ 706 pr = get_psychorange(pp, ss); 707 if (pr == NULL) { 708 printf("psycho_alloc_extent: get_psychorange failed\n"); 709 return NULL; 710 } 711 baddr = 0x00000000; 712 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 713 714 /* get available lists */ 715 if (PROM_getprop(node, "available", sizeof(*pa), &num, (void *)&pa)) { 716 printf("psycho_alloc_extent: PROM_getprop failed\n"); 717 return NULL; 718 } 719 720 /* create extent */ 721 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 722 EX_NOWAIT); 723 if (ex == NULL) { 724 printf("psycho_alloc_extent: extent_create failed\n"); 725 goto ret; 726 } 727 728 /* allocate assigned regions */ 729 for (i = 0; i < num; i++) 730 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 731 /* allocate bus space */ 732 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 733 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 734 if (extent_alloc_region(ex, baddr, addr - baddr, 735 EX_NOWAIT)) { 736 printf("psycho_alloc_extent: " 737 "extent_alloc_region %" PRIx64 "-%" 738 PRIx64 " failed\n", baddr, addr); 739 extent_destroy(ex); 740 ex = NULL; 741 goto ret; 742 } 743 baddr = addr + size; 744 } 745 /* allocate left region if available */ 746 if (baddr < bsize) 747 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 748 printf("psycho_alloc_extent: extent_alloc_region %" 749 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 750 extent_destroy(ex); 751 ex = NULL; 752 goto ret; 753 } 754 755 #ifdef DEBUG 756 /* print extent */ 757 extent_print(ex); 758 #endif 759 760 ret: 761 /* return extent */ 762 free(pa, M_DEVBUF); 763 return ex; 764 } 765 766 /* 767 * grovel the OBP for various psycho properties 768 */ 769 static void 770 psycho_get_bus_range(node, brp) 771 int node; 772 int *brp; 773 { 774 int n; 775 776 if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, (void *)&brp)) 777 panic("could not get psycho bus-range"); 778 if (n != 2) 779 panic("broken psycho bus-range"); 780 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1])); 781 } 782 783 static void 784 psycho_get_ranges(node, rp, np) 785 int node; 786 struct psycho_ranges **rp; 787 int *np; 788 { 789 790 if (PROM_getprop(node, "ranges", sizeof(**rp), np, (void **)rp)) 791 panic("could not get psycho ranges"); 792 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 793 } 794 795 /* 796 * Interrupt handlers. 797 */ 798 799 static int 800 psycho_ue(arg) 801 void *arg; 802 { 803 struct psycho_softc *sc = (struct psycho_softc *)arg; 804 struct psychoreg *regs = sc->sc_regs; 805 long long afsr = regs->psy_ue_afsr; 806 long long afar = regs->psy_ue_afar; 807 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 808 struct iommu_state *is = sc->sc_is; 809 char bits[128]; 810 811 /* 812 * It's uncorrectable. Dump the regs and panic. 813 */ 814 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 815 sc->sc_dev.dv_xname, afar, 816 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 817 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 818 bits, sizeof(bits))); 819 820 /* Sometimes the AFAR points to an IOTSB entry */ 821 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 822 printf("IOVA %llx IOTTE %llx\n", 823 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 824 (long long)ldxa(afar, ASI_PHYS_CACHED)); 825 } 826 #ifdef DDB 827 Debugger(); 828 #endif 829 regs->psy_ue_afar = 0; 830 regs->psy_ue_afsr = 0; 831 return (1); 832 } 833 static int 834 psycho_ce(arg) 835 void *arg; 836 { 837 struct psycho_softc *sc = (struct psycho_softc *)arg; 838 struct psychoreg *regs = sc->sc_regs; 839 840 /* 841 * It's correctable. Dump the regs and continue. 842 */ 843 844 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 845 sc->sc_dev.dv_xname, 846 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 847 return (1); 848 } 849 static int 850 psycho_bus_a(arg) 851 void *arg; 852 { 853 struct psycho_softc *sc = (struct psycho_softc *)arg; 854 struct psychoreg *regs = sc->sc_regs; 855 856 /* 857 * It's uncorrectable. Dump the regs and panic. 858 */ 859 860 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 861 sc->sc_dev.dv_xname, 862 (long long)regs->psy_pcictl[0].pci_afar, 863 (long long)regs->psy_pcictl[0].pci_afsr); 864 return (1); 865 } 866 static int 867 psycho_bus_b(arg) 868 void *arg; 869 { 870 struct psycho_softc *sc = (struct psycho_softc *)arg; 871 struct psychoreg *regs = sc->sc_regs; 872 873 /* 874 * It's uncorrectable. Dump the regs and panic. 875 */ 876 877 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 878 sc->sc_dev.dv_xname, 879 (long long)regs->psy_pcictl[0].pci_afar, 880 (long long)regs->psy_pcictl[0].pci_afsr); 881 return (1); 882 } 883 884 static int 885 psycho_powerfail(arg) 886 void *arg; 887 { 888 struct psycho_softc *sc = (struct psycho_softc *)arg; 889 890 /* 891 * We lost power. Queue a callback with thread context to 892 * handle all the real work. 893 */ 894 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 895 sc->sc_powerpressed = 1; 896 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 897 } 898 return (1); 899 } 900 901 static 902 int psycho_wakeup(arg) 903 void *arg; 904 { 905 struct psycho_softc *sc = (struct psycho_softc *)arg; 906 907 /* 908 * Gee, we don't really have a framework to deal with this 909 * properly. 910 */ 911 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 912 return (1); 913 } 914 915 916 917 /* 918 * initialise the IOMMU.. 919 */ 920 void 921 psycho_iommu_init(sc, tsbsize) 922 struct psycho_softc *sc; 923 int tsbsize; 924 { 925 char *name; 926 struct iommu_state *is = sc->sc_is; 927 u_int32_t iobase = -1; 928 int *vdma = NULL; 929 int nitem; 930 931 /* punch in our copies */ 932 is->is_bustag = sc->sc_bustag; 933 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 934 offsetof(struct psychoreg, psy_iommu), 935 sizeof (struct iommureg), 936 &is->is_iommu); 937 938 /* 939 * Separate the men from the boys. Get the `virtual-dma' 940 * property for sabre and use that to make sure the damn 941 * iommu works. 942 * 943 * We could query the `#virtual-dma-size-cells' and 944 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 945 */ 946 if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 947 (void *)&vdma)) { 948 /* Damn. Gotta use these values. */ 949 iobase = vdma[0]; 950 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 951 switch (vdma[1]) { 952 TSBCASE(1); TSBCASE(2); TSBCASE(3); 953 TSBCASE(4); TSBCASE(5); TSBCASE(6); 954 default: 955 printf("bogus tsb size %x, using 7\n", vdma[1]); 956 TSBCASE(7); 957 } 958 #undef TSBCASE 959 } 960 961 /* give us a nice name.. */ 962 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 963 if (name == 0) 964 panic("couldn't malloc iommu name"); 965 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 966 967 iommu_init(name, is, tsbsize, iobase); 968 } 969 970 /* 971 * below here is bus space and bus DMA support 972 */ 973 bus_space_tag_t 974 psycho_alloc_bus_tag(pp, type) 975 struct psycho_pbm *pp; 976 int type; 977 { 978 struct psycho_softc *sc = pp->pp_sc; 979 bus_space_tag_t bt; 980 981 bt = (bus_space_tag_t) 982 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 983 if (bt == NULL) 984 panic("could not allocate psycho bus tag"); 985 986 bzero(bt, sizeof *bt); 987 bt->cookie = pp; 988 bt->parent = sc->sc_bustag; 989 bt->type = type; 990 bt->sparc_bus_map = _psycho_bus_map; 991 bt->sparc_bus_mmap = psycho_bus_mmap; 992 bt->sparc_intr_establish = psycho_intr_establish; 993 return (bt); 994 } 995 996 bus_dma_tag_t 997 psycho_alloc_dma_tag(pp) 998 struct psycho_pbm *pp; 999 { 1000 struct psycho_softc *sc = pp->pp_sc; 1001 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1002 1003 dt = (bus_dma_tag_t) 1004 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1005 if (dt == NULL) 1006 panic("could not allocate psycho DMA tag"); 1007 1008 bzero(dt, sizeof *dt); 1009 dt->_cookie = pp; 1010 dt->_parent = pdt; 1011 #define PCOPY(x) dt->x = pdt->x 1012 PCOPY(_dmamap_create); 1013 PCOPY(_dmamap_destroy); 1014 dt->_dmamap_load = psycho_dmamap_load; 1015 PCOPY(_dmamap_load_mbuf); 1016 PCOPY(_dmamap_load_uio); 1017 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1018 dt->_dmamap_unload = psycho_dmamap_unload; 1019 dt->_dmamap_sync = psycho_dmamap_sync; 1020 dt->_dmamem_alloc = psycho_dmamem_alloc; 1021 dt->_dmamem_free = psycho_dmamem_free; 1022 dt->_dmamem_map = psycho_dmamem_map; 1023 dt->_dmamem_unmap = psycho_dmamem_unmap; 1024 PCOPY(_dmamem_mmap); 1025 #undef PCOPY 1026 return (dt); 1027 } 1028 1029 /* 1030 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1031 * PCI physical addresses. 1032 */ 1033 1034 static int 1035 get_childspace(type) 1036 int type; 1037 { 1038 int ss; 1039 1040 switch (type) { 1041 case PCI_CONFIG_BUS_SPACE: 1042 ss = 0x00; 1043 break; 1044 case PCI_IO_BUS_SPACE: 1045 ss = 0x01; 1046 break; 1047 case PCI_MEMORY_BUS_SPACE: 1048 ss = 0x02; 1049 break; 1050 #if 0 1051 /* we don't do 64 bit memory space */ 1052 case PCI_MEMORY64_BUS_SPACE: 1053 ss = 0x03; 1054 break; 1055 #endif 1056 default: 1057 panic("get_childspace: unknown bus type"); 1058 } 1059 1060 return (ss); 1061 } 1062 1063 static struct psycho_ranges * 1064 get_psychorange(pp, ss) 1065 struct psycho_pbm *pp; 1066 int ss; 1067 { 1068 int i; 1069 1070 for (i = 0; i < pp->pp_nrange; i++) { 1071 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1072 return (&pp->pp_range[i]); 1073 } 1074 /* not found */ 1075 return (NULL); 1076 } 1077 1078 static int 1079 _psycho_bus_map(t, offset, size, flags, unused, hp) 1080 bus_space_tag_t t; 1081 bus_addr_t offset; 1082 bus_size_t size; 1083 int flags; 1084 vaddr_t unused; 1085 bus_space_handle_t *hp; 1086 { 1087 struct psycho_pbm *pp = t->cookie; 1088 struct psycho_softc *sc = pp->pp_sc; 1089 struct psycho_ranges *pr; 1090 bus_addr_t paddr; 1091 int ss; 1092 1093 DPRINTF(PDB_BUSMAP, 1094 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1095 t->type, (unsigned long long)offset, 1096 (unsigned long long)size, flags)); 1097 1098 ss = get_childspace(t->type); 1099 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1100 1101 pr = get_psychorange(pp, ss); 1102 if (pr != NULL) { 1103 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1104 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1105 "space %lx offset %lx paddr %qx\n", 1106 (long)ss, (long)offset, 1107 (unsigned long long)paddr)); 1108 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1109 flags, 0, hp)); 1110 } 1111 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1112 return (EINVAL); 1113 } 1114 1115 static paddr_t 1116 psycho_bus_mmap(t, paddr, off, prot, flags) 1117 bus_space_tag_t t; 1118 bus_addr_t paddr; 1119 off_t off; 1120 int prot; 1121 int flags; 1122 { 1123 bus_addr_t offset = paddr; 1124 struct psycho_pbm *pp = t->cookie; 1125 struct psycho_softc *sc = pp->pp_sc; 1126 struct psycho_ranges *pr; 1127 int ss; 1128 1129 ss = get_childspace(t->type); 1130 1131 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1132 prot, flags, (unsigned long long)paddr)); 1133 1134 pr = get_psychorange(pp, ss); 1135 if (pr != NULL) { 1136 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1137 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1138 "space %lx offset %lx paddr %qx\n", 1139 (long)ss, (long)offset, 1140 (unsigned long long)paddr)); 1141 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1142 prot, flags)); 1143 } 1144 1145 return (-1); 1146 } 1147 1148 /* 1149 * Get a PCI offset address from bus_space_handle_t. 1150 */ 1151 bus_addr_t 1152 psycho_bus_offset(t, hp) 1153 bus_space_tag_t t; 1154 bus_space_handle_t *hp; 1155 { 1156 struct psycho_pbm *pp = t->cookie; 1157 struct psycho_ranges *pr; 1158 bus_addr_t addr, offset; 1159 vaddr_t va; 1160 int ss; 1161 1162 addr = hp->_ptr; 1163 ss = get_childspace(t->type); 1164 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1165 " cspace %d", t->type, addr, ss)); 1166 1167 pr = get_psychorange(pp, ss); 1168 if (pr != NULL) { 1169 if (!PHYS_ASI(hp->_asi)) { 1170 va = trunc_page((vaddr_t)addr); 1171 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1172 DPRINTF(PDB_BUSMAP, 1173 ("\n pmap_extract FAILED\n")); 1174 return (-1); 1175 } 1176 addr += hp->_ptr & PGOFSET; 1177 } 1178 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1179 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1180 " offset %" PRIx64 "\n", addr, offset)); 1181 return (offset); 1182 } 1183 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1184 return (-1); 1185 } 1186 1187 1188 /* 1189 * install an interrupt handler for a PCI device 1190 */ 1191 void * 1192 psycho_intr_establish(t, ihandle, level, handler, arg, fastvec) 1193 bus_space_tag_t t; 1194 int ihandle; 1195 int level; 1196 int (*handler) __P((void *)); 1197 void *arg; 1198 void (*fastvec) __P((void)); /* ignored */ 1199 { 1200 struct psycho_pbm *pp = t->cookie; 1201 struct psycho_softc *sc = pp->pp_sc; 1202 struct intrhand *ih; 1203 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 1204 int64_t intrmap = 0; 1205 int ino; 1206 long vec = INTVEC(ihandle); 1207 1208 ih = (struct intrhand *) 1209 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1210 if (ih == NULL) 1211 return (NULL); 1212 1213 /* 1214 * Hunt through all the interrupt mapping regs to look for our 1215 * interrupt vector. 1216 * 1217 * XXX We only compare INOs rather than IGNs since the firmware may 1218 * not provide the IGN and the IGN is constant for all device on that 1219 * PCI controller. This could cause problems for the FFB/external 1220 * interrupt which has a full vector that can be set arbitrarily. 1221 */ 1222 1223 1224 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1225 ino = INTINO(vec); 1226 DPRINTF(PDB_INTR, (" ino %x", ino)); 1227 1228 /* If the device didn't ask for an IPL, use the one encoded. */ 1229 if (level == IPL_NONE) level = INTLEV(vec); 1230 /* If it still has no level, print a warning and assign IPL 2 */ 1231 if (level == IPL_NONE) { 1232 printf("ERROR: no IPL, setting IPL 2.\n"); 1233 level = 2; 1234 } 1235 1236 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1237 (long)ino, intrlev[ino])); 1238 1239 /* Hunt thru obio first */ 1240 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1241 intrclrptr = &sc->sc_regs->scsi_clr_int; 1242 intrmapptr < &sc->sc_regs->ffb0_int_map; 1243 intrmapptr++, intrclrptr++) { 1244 if (INTINO(*intrmapptr) == ino) 1245 goto found; 1246 } 1247 1248 /* Now do PCI interrupts */ 1249 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1250 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1251 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1252 intrmapptr++, intrclrptr += 4) { 1253 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1254 intrclrptr += vec & 0x3; 1255 goto found; 1256 } 1257 } 1258 1259 /* Finally check the two FFB slots */ 1260 intrclrptr = NULL; /* XXX? */ 1261 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1262 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1263 intrmapptr++) { 1264 if (INTVEC(*intrmapptr) == ino) 1265 goto found; 1266 } 1267 1268 printf("Cannot find interrupt vector %lx\n", vec); 1269 return (NULL); 1270 1271 found: 1272 /* Register the map and clear intr registers */ 1273 ih->ih_map = intrmapptr; 1274 ih->ih_clr = intrclrptr; 1275 1276 #ifdef NOT_DEBUG 1277 if (psycho_debug & PDB_INTR) { 1278 long i; 1279 1280 for (i = 0; i < 500000000; i++) 1281 continue; 1282 } 1283 #endif 1284 1285 ih->ih_fun = handler; 1286 ih->ih_arg = arg; 1287 ih->ih_pil = level; 1288 ih->ih_number = ino | sc->sc_ign; 1289 1290 DPRINTF(PDB_INTR, ( 1291 "; installing handler %p arg %p with ino %u pil %u\n", 1292 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1293 1294 intr_establish(ih->ih_pil, ih); 1295 1296 /* 1297 * Enable the interrupt now we have the handler installed. 1298 * Read the current value as we can't change it besides the 1299 * valid bit so so make sure only this bit is changed. 1300 * 1301 * XXXX --- we really should use bus_space for this. 1302 */ 1303 if (intrmapptr) { 1304 intrmap = *intrmapptr; 1305 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1306 (unsigned long long)intrmap)); 1307 1308 /* Enable the interrupt */ 1309 intrmap |= INTMAP_V; 1310 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1311 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1312 (unsigned long long)intrmap)); 1313 *intrmapptr = intrmap; 1314 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1315 (unsigned long long)(intrmap = *intrmapptr))); 1316 } 1317 return (ih); 1318 } 1319 1320 /* 1321 * hooks into the iommu dvma calls. 1322 */ 1323 int 1324 psycho_dmamap_load(t, map, buf, buflen, p, flags) 1325 bus_dma_tag_t t; 1326 bus_dmamap_t map; 1327 void *buf; 1328 bus_size_t buflen; 1329 struct proc *p; 1330 int flags; 1331 { 1332 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1333 1334 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1335 } 1336 1337 void 1338 psycho_dmamap_unload(t, map) 1339 bus_dma_tag_t t; 1340 bus_dmamap_t map; 1341 { 1342 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1343 1344 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1345 } 1346 1347 int 1348 psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags) 1349 bus_dma_tag_t t; 1350 bus_dmamap_t map; 1351 bus_dma_segment_t *segs; 1352 int nsegs; 1353 bus_size_t size; 1354 int flags; 1355 { 1356 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1357 1358 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1359 } 1360 1361 void 1362 psycho_dmamap_sync(t, map, offset, len, ops) 1363 bus_dma_tag_t t; 1364 bus_dmamap_t map; 1365 bus_addr_t offset; 1366 bus_size_t len; 1367 int ops; 1368 { 1369 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1370 1371 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1372 /* Flush the CPU then the IOMMU */ 1373 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1374 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1375 } 1376 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1377 /* Flush the IOMMU then the CPU */ 1378 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1379 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1380 } 1381 1382 } 1383 1384 int 1385 psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1386 bus_dma_tag_t t; 1387 bus_size_t size; 1388 bus_size_t alignment; 1389 bus_size_t boundary; 1390 bus_dma_segment_t *segs; 1391 int nsegs; 1392 int *rsegs; 1393 int flags; 1394 { 1395 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1396 1397 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1398 segs, nsegs, rsegs, flags)); 1399 } 1400 1401 void 1402 psycho_dmamem_free(t, segs, nsegs) 1403 bus_dma_tag_t t; 1404 bus_dma_segment_t *segs; 1405 int nsegs; 1406 { 1407 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1408 1409 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1410 } 1411 1412 int 1413 psycho_dmamem_map(t, segs, nsegs, size, kvap, flags) 1414 bus_dma_tag_t t; 1415 bus_dma_segment_t *segs; 1416 int nsegs; 1417 size_t size; 1418 caddr_t *kvap; 1419 int flags; 1420 { 1421 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1422 1423 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1424 } 1425 1426 void 1427 psycho_dmamem_unmap(t, kva, size) 1428 bus_dma_tag_t t; 1429 caddr_t kva; 1430 size_t size; 1431 { 1432 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1433 1434 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1435 } 1436