1 /* $NetBSD: psycho.c,v 1.64 2003/07/15 03:36:06 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.64 2003/07/15 03:36:06 lukem Exp $"); 34 35 #include "opt_ddb.h" 36 37 /* 38 * Support for `psycho' and `psycho+' UPA to PCI bridge and 39 * UltraSPARC IIi and IIe `sabre' PCI controllers. 40 */ 41 42 #ifdef DEBUG 43 #define PDB_PROM 0x01 44 #define PDB_BUSMAP 0x02 45 #define PDB_INTR 0x04 46 int psycho_debug = 0x0; 47 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 48 #else 49 #define DPRINTF(l, s) 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/extent.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 #include <sys/reboot.h> 60 61 #include <uvm/uvm.h> 62 63 #define _SPARC_BUS_DMA_PRIVATE 64 #include <machine/bus.h> 65 #include <machine/autoconf.h> 66 #include <machine/psl.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/sysmon/sysmon_taskq.h> 71 72 #include <sparc64/dev/iommureg.h> 73 #include <sparc64/dev/iommuvar.h> 74 #include <sparc64/dev/psychoreg.h> 75 #include <sparc64/dev/psychovar.h> 76 #include <sparc64/sparc64/cache.h> 77 78 #include "ioconf.h" 79 80 static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int, 81 pci_chipset_tag_t)); 82 static struct extent *psycho_alloc_extent __P((struct psycho_pbm *, int, int, 83 char *)); 84 static void psycho_get_bus_range __P((int, int *)); 85 static void psycho_get_ranges __P((int, struct psycho_ranges **, int *)); 86 static void psycho_set_intr __P((struct psycho_softc *, int, void *, 87 u_int64_t *, u_int64_t *)); 88 89 /* Interrupt handlers */ 90 static int psycho_ue __P((void *)); 91 static int psycho_ce __P((void *)); 92 static int psycho_bus_a __P((void *)); 93 static int psycho_bus_b __P((void *)); 94 static int psycho_powerfail __P((void *)); 95 static int psycho_wakeup __P((void *)); 96 97 98 /* IOMMU support */ 99 static void psycho_iommu_init __P((struct psycho_softc *, int)); 100 101 /* 102 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 103 * of the bus DMA support is provided by the iommu dvma controller. 104 */ 105 static int get_childspace __P((int)); 106 static struct psycho_ranges *get_psychorange __P((struct psycho_pbm *, int)); 107 108 static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 109 int, int)); 110 static int _psycho_bus_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, 111 vaddr_t, bus_space_handle_t *)); 112 static void *psycho_intr_establish __P((bus_space_tag_t, int, int, 113 int (*) __P((void *)), void *, void(*)__P((void)))); 114 115 static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 116 bus_size_t, struct proc *, int)); 117 static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 118 static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 119 bus_dma_segment_t *, int, bus_size_t, int)); 120 static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 121 bus_size_t, int)); 122 int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 123 bus_dma_segment_t *, int, int *, int)); 124 void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 125 int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 126 caddr_t *, int)); 127 void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 128 129 /* base pci_chipset */ 130 extern struct sparc_pci_chipset _sparc_pci_chipset; 131 132 /* power button handlers */ 133 static void psycho_register_power_button(struct psycho_softc *sc); 134 static void psycho_power_button_pressed(void *arg); 135 136 /* 137 * autoconfiguration 138 */ 139 static int psycho_match __P((struct device *, struct cfdata *, void *)); 140 static void psycho_attach __P((struct device *, struct device *, void *)); 141 static int psycho_print __P((void *aux, const char *p)); 142 143 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 144 psycho_match, psycho_attach, NULL, NULL); 145 146 /* 147 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 148 * single PCI bus and does not have a streaming buffer. It often has an APB 149 * (advanced PCI bridge) connected to it, which was designed specifically for 150 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 151 * appears as two "simba"'s underneath the sabre. 152 * 153 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 154 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 155 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 156 * will usually find a "psycho+" since I don't think the original "psycho" 157 * ever shipped, and if it did it would be in the U30. 158 * 159 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 160 * both part of the same IC, they only have a single register space. As such, 161 * they need to be configured together, even though the autoconfiguration will 162 * attach them separately. 163 * 164 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 165 * as pci1 and pci2, although they have been implemented with other PCI bus 166 * numbers on some machines. 167 * 168 * On UltraII machines, there can be any number of "psycho+" ICs, each 169 * providing two PCI buses. 170 * 171 * 172 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 173 * the values of the following interrupts in this order: 174 * 175 * PCI Bus Error (30) 176 * DMA UE (2e) 177 * DMA CE (2f) 178 * Power Fail (25) 179 * 180 * We really should attach handlers for each. 181 * 182 */ 183 184 #define ROM_PCI_NAME "pci" 185 186 struct psycho_names { 187 char *p_name; 188 int p_type; 189 } psycho_names[] = { 190 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 191 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 192 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 193 { "pci108e,a000", PSYCHO_MODE_SABRE }, 194 { "pci108e,a001", PSYCHO_MODE_SABRE }, 195 { NULL, 0 } 196 }; 197 198 static int 199 psycho_match(parent, match, aux) 200 struct device *parent; 201 struct cfdata *match; 202 void *aux; 203 { 204 struct mainbus_attach_args *ma = aux; 205 char *model = PROM_getpropstring(ma->ma_node, "model"); 206 int i; 207 208 /* match on a name of "pci" and a sabre or a psycho */ 209 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 210 for (i=0; psycho_names[i].p_name; i++) 211 if (strcmp(model, psycho_names[i].p_name) == 0) 212 return (1); 213 214 model = PROM_getpropstring(ma->ma_node, "compatible"); 215 for (i=0; psycho_names[i].p_name; i++) 216 if (strcmp(model, psycho_names[i].p_name) == 0) 217 return (1); 218 } 219 return (0); 220 } 221 222 /* 223 * SUNW,psycho initialisation .. 224 * - find the per-psycho registers 225 * - figure out the IGN. 226 * - find our partner psycho 227 * - configure ourselves 228 * - bus range, bus, 229 * - get interrupt-map and interrupt-map-mask 230 * - setup the chipsets. 231 * - if we're the first of the pair, initialise the IOMMU, otherwise 232 * just copy it's tags and addresses. 233 */ 234 static void 235 psycho_attach(parent, self, aux) 236 struct device *parent, *self; 237 void *aux; 238 { 239 struct psycho_softc *sc = (struct psycho_softc *)self; 240 struct psycho_softc *osc = NULL; 241 struct psycho_pbm *pp; 242 struct pcibus_attach_args pba; 243 struct mainbus_attach_args *ma = aux; 244 bus_space_handle_t bh; 245 u_int64_t csr; 246 int psycho_br[2], n, i; 247 bus_space_handle_t pci_ctl; 248 char *model = PROM_getpropstring(ma->ma_node, "model"); 249 250 printf("\n"); 251 252 sc->sc_node = ma->ma_node; 253 sc->sc_bustag = ma->ma_bustag; 254 sc->sc_dmatag = ma->ma_dmatag; 255 256 /* 257 * Identify the device. 258 */ 259 for (i=0; psycho_names[i].p_name; i++) 260 if (strcmp(model, psycho_names[i].p_name) == 0) { 261 sc->sc_mode = psycho_names[i].p_type; 262 goto found; 263 } 264 265 model = PROM_getpropstring(ma->ma_node, "compatible"); 266 for (i=0; psycho_names[i].p_name; i++) 267 if (strcmp(model, psycho_names[i].p_name) == 0) { 268 sc->sc_mode = psycho_names[i].p_type; 269 goto found; 270 } 271 272 panic("unknown psycho model %s", model); 273 found: 274 275 /* 276 * The psycho gets three register banks: 277 * (0) per-PBM configuration and status registers 278 * (1) per-PBM PCI configuration space, containing only the 279 * PBM 256-byte PCI header 280 * (2) the shared psycho configuration registers (struct psychoreg) 281 */ 282 283 /* Register layouts are different. stuupid. */ 284 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 285 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 286 287 if (ma->ma_naddress > 2) { 288 sparc_promaddr_to_handle(sc->sc_bustag, 289 ma->ma_address[2], &sc->sc_bh); 290 sparc_promaddr_to_handle(sc->sc_bustag, 291 ma->ma_address[0], &pci_ctl); 292 293 sc->sc_regs = (struct psychoreg *) 294 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 295 } else if (ma->ma_nreg > 2) { 296 297 /* We need to map this in ourselves. */ 298 if (bus_space_map(sc->sc_bustag, 299 ma->ma_reg[2].ur_paddr, 300 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 301 &sc->sc_bh)) 302 panic("psycho_attach: cannot map regs"); 303 sc->sc_regs = (struct psychoreg *) 304 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 305 306 if (bus_space_map(sc->sc_bustag, 307 ma->ma_reg[0].ur_paddr, 308 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 309 &pci_ctl)) 310 panic("psycho_attach: cannot map ctl"); 311 } else 312 panic("psycho_attach: %d not enough registers", 313 ma->ma_nreg); 314 } else { 315 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 316 317 if (ma->ma_naddress) { 318 sparc_promaddr_to_handle(sc->sc_bustag, 319 ma->ma_address[0], &sc->sc_bh); 320 sc->sc_regs = (struct psychoreg *) 321 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 322 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 323 offsetof(struct psychoreg, psy_pcictl), 324 sizeof(struct pci_ctl), &pci_ctl); 325 } else if (ma->ma_nreg) { 326 327 /* We need to map this in ourselves. */ 328 if (bus_space_map(sc->sc_bustag, 329 ma->ma_reg[0].ur_paddr, 330 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 331 &sc->sc_bh)) 332 panic("psycho_attach: cannot map regs"); 333 sc->sc_regs = (struct psychoreg *) 334 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 335 336 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 337 offsetof(struct psychoreg, psy_pcictl), 338 sizeof(struct pci_ctl), &pci_ctl); 339 } else 340 panic("psycho_attach: %d not enough registers", 341 ma->ma_nreg); 342 } 343 344 345 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 346 offsetof(struct psychoreg, psy_csr)); 347 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 348 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 349 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 350 351 printf("%s: impl %d, version %d: ign %x ", 352 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 353 sc->sc_ign); 354 /* 355 * Match other psycho's that are already configured against 356 * the base physical address. This will be the same for a 357 * pair of devices that share register space. 358 */ 359 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 360 361 struct psycho_softc *asc = 362 (struct psycho_softc *)psycho_cd.cd_devs[n]; 363 364 if (asc == NULL || asc == sc) 365 /* This entry is not there or it is me */ 366 continue; 367 368 if (asc->sc_basepaddr != sc->sc_basepaddr) 369 /* This is an unrelated psycho */ 370 continue; 371 372 /* Found partner */ 373 osc = asc; 374 break; 375 } 376 377 378 /* Oh, dear. OK, lets get started */ 379 380 /* 381 * Setup the PCI control register 382 */ 383 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 384 offsetof(struct pci_ctl, pci_csr)); 385 csr |= PCICTL_MRLM | 386 PCICTL_ARB_PARK | 387 PCICTL_ERRINTEN | 388 PCICTL_4ENABLE; 389 csr &= ~(PCICTL_SERR | 390 PCICTL_CPU_PRIO | 391 PCICTL_ARB_PRIO | 392 PCICTL_RTRYWAIT); 393 bus_space_write_8(sc->sc_bustag, pci_ctl, 394 offsetof(struct pci_ctl, pci_csr), csr); 395 396 397 /* 398 * Allocate our psycho_pbm 399 */ 400 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 401 M_NOWAIT | M_ZERO); 402 if (pp == NULL) 403 panic("could not allocate psycho pbm"); 404 405 pp->pp_sc = sc; 406 407 /* grab the psycho ranges */ 408 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 409 410 /* get the bus-range for the psycho */ 411 psycho_get_bus_range(sc->sc_node, psycho_br); 412 413 pba.pba_bus = psycho_br[0]; 414 pba.pba_bridgetag = NULL; 415 pp->pp_busmax = psycho_br[1]; 416 417 printf("bus range %u to %u", psycho_br[0], psycho_br[1]); 418 printf("; PCI bus %d", psycho_br[0]); 419 420 pp->pp_pcictl = pci_ctl; 421 422 /* allocate our tags */ 423 pp->pp_memt = psycho_alloc_mem_tag(pp); 424 pp->pp_iot = psycho_alloc_io_tag(pp); 425 pp->pp_dmat = psycho_alloc_dma_tag(pp); 426 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 427 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 428 429 /* allocate a chipset for this */ 430 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 431 432 /* setup the rest of the psycho pbm */ 433 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 434 435 printf("\n"); 436 437 /* allocate extents for free bus space */ 438 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 439 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 440 441 /* 442 * And finally, if we're a sabre or the first of a pair of psycho's to 443 * arrive here, start up the IOMMU and get a config space tag. 444 */ 445 if (osc == NULL) { 446 uint64_t timeo; 447 448 /* 449 * Establish handlers for interesting interrupts.... 450 * 451 * XXX We need to remember these and remove this to support 452 * hotplug on the UPA/FHC bus. 453 * 454 * XXX Not all controllers have these, but installing them 455 * is better than trying to sort through this mess. 456 */ 457 psycho_set_intr(sc, 15, psycho_ue, 458 &sc->sc_regs->ue_int_map, 459 &sc->sc_regs->ue_clr_int); 460 psycho_set_intr(sc, 1, psycho_ce, 461 &sc->sc_regs->ce_int_map, 462 &sc->sc_regs->ce_clr_int); 463 psycho_set_intr(sc, 15, psycho_bus_a, 464 &sc->sc_regs->pciaerr_int_map, 465 &sc->sc_regs->pciaerr_clr_int); 466 psycho_set_intr(sc, 15, psycho_bus_b, 467 &sc->sc_regs->pciberr_int_map, 468 &sc->sc_regs->pciberr_clr_int); 469 psycho_set_intr(sc, 15, psycho_powerfail, 470 &sc->sc_regs->power_int_map, 471 &sc->sc_regs->power_clr_int); 472 psycho_register_power_button(sc); 473 psycho_set_intr(sc, 1, psycho_wakeup, 474 &sc->sc_regs->pwrmgt_int_map, 475 &sc->sc_regs->pwrmgt_clr_int); 476 477 478 /* 479 * Apparently a number of machines with psycho and psycho+ 480 * controllers have interrupt latency issues. We'll try 481 * setting the interrupt retry timeout to 0xff which gives us 482 * a retry of 3-6 usec (which is what sysio is set to) for the 483 * moment, which seems to help alleviate this problem. 484 */ 485 timeo = sc->sc_regs->intr_retry_timer; 486 if (timeo > 0xfff) { 487 #ifdef DEBUG 488 printf("decreasing interrupt retry timeout " 489 "from %lx to 0xff\n", (long)timeo); 490 #endif 491 sc->sc_regs->intr_retry_timer = 0xff; 492 } 493 494 /* 495 * Allocate bus node, this contains a prom node per bus. 496 */ 497 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 498 M_NOWAIT | M_ZERO); 499 if (pp->pp_busnode == NULL) 500 panic("psycho_attach: malloc pp->pp_busnode"); 501 502 /* 503 * Setup IOMMU and PCI configuration if we're the first 504 * of a pair of psycho's to arrive here. 505 * 506 * We should calculate a TSB size based on amount of RAM 507 * and number of bus controllers and number an type of 508 * child devices. 509 * 510 * For the moment, 32KB should be more than enough. 511 */ 512 sc->sc_is = malloc(sizeof(struct iommu_state), 513 M_DEVBUF, M_NOWAIT); 514 if (sc->sc_is == NULL) 515 panic("psycho_attach: malloc iommu_state"); 516 517 /* Point the strbuf_ctl at the iommu_state */ 518 pp->pp_sb.sb_is = sc->sc_is; 519 520 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 521 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 522 struct strbuf_ctl *sb = &pp->pp_sb; 523 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 524 525 /* 526 * Initialize the strbuf_ctl. 527 * 528 * The flush sync buffer must be 64-byte aligned. 529 */ 530 sb->sb_flush = (void *)(va & ~0x3f); 531 532 bus_space_subregion(sc->sc_bustag, pci_ctl, 533 offsetof(struct pci_ctl, pci_strbuf), 534 sizeof (struct iommu_strbuf), &sb->sb_sb); 535 536 /* Point our iommu at the strbuf_ctl */ 537 sc->sc_is->is_sb[0] = sb; 538 } 539 540 psycho_iommu_init(sc, 2); 541 542 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 543 544 /* 545 * XXX This is a really ugly hack because PCI config space 546 * is explicitly handled with unmapped accesses. 547 */ 548 i = sc->sc_bustag->type; 549 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 550 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 551 0x01000000, 0, &bh)) 552 panic("could not map psycho PCI configuration space"); 553 sc->sc_bustag->type = i; 554 sc->sc_configaddr = bh; 555 } else { 556 /* Share bus numbers with the pair of mine */ 557 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 558 559 /* Just copy IOMMU state, config tag and address */ 560 sc->sc_is = osc->sc_is; 561 sc->sc_configtag = osc->sc_configtag; 562 sc->sc_configaddr = osc->sc_configaddr; 563 564 /* Point the strbuf_ctl at the iommu_state */ 565 pp->pp_sb.sb_is = sc->sc_is; 566 567 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 568 struct strbuf_ctl *sb = &pp->pp_sb; 569 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 570 571 /* 572 * Initialize the strbuf_ctl. 573 * 574 * The flush sync buffer must be 64-byte aligned. 575 */ 576 sb->sb_flush = (void *)(va & ~0x3f); 577 578 bus_space_subregion(sc->sc_bustag, pci_ctl, 579 offsetof(struct pci_ctl, pci_strbuf), 580 sizeof (struct iommu_strbuf), &sb->sb_sb); 581 582 /* Point our iommu at the strbuf_ctl */ 583 sc->sc_is->is_sb[1] = sb; 584 } 585 iommu_reset(sc->sc_is); 586 } 587 588 /* 589 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 590 */ 591 pba.pba_busname = "pci"; 592 pba.pba_flags = sc->sc_psycho_this->pp_flags; 593 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 594 pba.pba_dmat64 = NULL; 595 pba.pba_iot = sc->sc_psycho_this->pp_iot; 596 pba.pba_memt = sc->sc_psycho_this->pp_memt; 597 598 config_found(self, &pba, psycho_print); 599 } 600 601 static int 602 psycho_print(aux, p) 603 void *aux; 604 const char *p; 605 { 606 607 if (p == NULL) 608 return (UNCONF); 609 return (QUIET); 610 } 611 612 static void 613 psycho_set_intr(sc, ipl, handler, mapper, clearer) 614 struct psycho_softc *sc; 615 int ipl; 616 void *handler; 617 u_int64_t *mapper; 618 u_int64_t *clearer; 619 { 620 struct intrhand *ih; 621 622 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 623 M_DEVBUF, M_NOWAIT); 624 ih->ih_arg = sc; 625 ih->ih_map = mapper; 626 ih->ih_clr = clearer; 627 ih->ih_fun = handler; 628 ih->ih_pil = (1<<ipl); 629 ih->ih_number = INTVEC(*(ih->ih_map)); 630 intr_establish(ipl, ih); 631 *(ih->ih_map) |= INTMAP_V; 632 } 633 634 /* 635 * power button handlers 636 */ 637 static void 638 psycho_register_power_button(struct psycho_softc *sc) 639 { 640 sysmon_task_queue_init(); 641 642 sc->sc_powerpressed = 0; 643 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 644 if (!sc->sc_smcontext) { 645 printf("%s: could not allocate power button context\n", 646 sc->sc_dev.dv_xname); 647 return; 648 } 649 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 650 sc->sc_smcontext->smpsw_name = sc->sc_dev.dv_xname; 651 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 652 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 653 printf("%s: unable to register power button with sysmon\n", 654 sc->sc_dev.dv_xname); 655 } 656 657 static void 658 psycho_power_button_pressed(void *arg) 659 { 660 struct psycho_softc *sc = arg; 661 662 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 663 sc->sc_powerpressed = 0; 664 } 665 666 /* 667 * PCI bus support 668 */ 669 670 /* 671 * allocate a PCI chipset tag and set it's cookie. 672 */ 673 static pci_chipset_tag_t 674 psycho_alloc_chipset(pp, node, pc) 675 struct psycho_pbm *pp; 676 int node; 677 pci_chipset_tag_t pc; 678 { 679 pci_chipset_tag_t npc; 680 681 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 682 if (npc == NULL) 683 panic("could not allocate pci_chipset_tag_t"); 684 memcpy(npc, pc, sizeof *pc); 685 npc->cookie = pp; 686 npc->rootnode = node; 687 688 return (npc); 689 } 690 691 /* 692 * create extent for free bus space, then allocate assigned regions. 693 */ 694 static struct extent * 695 psycho_alloc_extent(pp, node, ss, name) 696 struct psycho_pbm *pp; 697 int node; 698 int ss; 699 char *name; 700 { 701 struct psycho_registers *pa = NULL; 702 struct psycho_ranges *pr; 703 struct extent *ex; 704 bus_addr_t baddr, addr; 705 bus_size_t bsize, size; 706 int i, num; 707 708 /* get bus space size */ 709 pr = get_psychorange(pp, ss); 710 if (pr == NULL) { 711 printf("psycho_alloc_extent: get_psychorange failed\n"); 712 return NULL; 713 } 714 baddr = 0x00000000; 715 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 716 717 /* get available lists */ 718 if (PROM_getprop(node, "available", sizeof(*pa), &num, (void *)&pa)) { 719 printf("psycho_alloc_extent: PROM_getprop failed\n"); 720 return NULL; 721 } 722 723 /* create extent */ 724 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 725 EX_NOWAIT); 726 if (ex == NULL) { 727 printf("psycho_alloc_extent: extent_create failed\n"); 728 goto ret; 729 } 730 731 /* allocate assigned regions */ 732 for (i = 0; i < num; i++) 733 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 734 /* allocate bus space */ 735 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 736 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 737 if (extent_alloc_region(ex, baddr, addr - baddr, 738 EX_NOWAIT)) { 739 printf("psycho_alloc_extent: " 740 "extent_alloc_region %" PRIx64 "-%" 741 PRIx64 " failed\n", baddr, addr); 742 extent_destroy(ex); 743 ex = NULL; 744 goto ret; 745 } 746 baddr = addr + size; 747 } 748 /* allocate left region if available */ 749 if (baddr < bsize) 750 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 751 printf("psycho_alloc_extent: extent_alloc_region %" 752 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 753 extent_destroy(ex); 754 ex = NULL; 755 goto ret; 756 } 757 758 #ifdef DEBUG 759 /* print extent */ 760 extent_print(ex); 761 #endif 762 763 ret: 764 /* return extent */ 765 free(pa, M_DEVBUF); 766 return ex; 767 } 768 769 /* 770 * grovel the OBP for various psycho properties 771 */ 772 static void 773 psycho_get_bus_range(node, brp) 774 int node; 775 int *brp; 776 { 777 int n; 778 779 if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, (void *)&brp)) 780 panic("could not get psycho bus-range"); 781 if (n != 2) 782 panic("broken psycho bus-range"); 783 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1])); 784 } 785 786 static void 787 psycho_get_ranges(node, rp, np) 788 int node; 789 struct psycho_ranges **rp; 790 int *np; 791 { 792 793 if (PROM_getprop(node, "ranges", sizeof(**rp), np, (void **)rp)) 794 panic("could not get psycho ranges"); 795 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 796 } 797 798 /* 799 * Interrupt handlers. 800 */ 801 802 static int 803 psycho_ue(arg) 804 void *arg; 805 { 806 struct psycho_softc *sc = (struct psycho_softc *)arg; 807 struct psychoreg *regs = sc->sc_regs; 808 long long afsr = regs->psy_ue_afsr; 809 long long afar = regs->psy_ue_afar; 810 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 811 struct iommu_state *is = sc->sc_is; 812 char bits[128]; 813 814 /* 815 * It's uncorrectable. Dump the regs and panic. 816 */ 817 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 818 sc->sc_dev.dv_xname, afar, 819 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 820 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 821 bits, sizeof(bits))); 822 823 /* Sometimes the AFAR points to an IOTSB entry */ 824 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 825 printf("IOVA %llx IOTTE %llx\n", 826 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 827 (long long)ldxa(afar, ASI_PHYS_CACHED)); 828 } 829 #ifdef DDB 830 Debugger(); 831 #endif 832 regs->psy_ue_afar = 0; 833 regs->psy_ue_afsr = 0; 834 return (1); 835 } 836 static int 837 psycho_ce(arg) 838 void *arg; 839 { 840 struct psycho_softc *sc = (struct psycho_softc *)arg; 841 struct psychoreg *regs = sc->sc_regs; 842 843 /* 844 * It's correctable. Dump the regs and continue. 845 */ 846 847 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 848 sc->sc_dev.dv_xname, 849 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 850 return (1); 851 } 852 static int 853 psycho_bus_a(arg) 854 void *arg; 855 { 856 struct psycho_softc *sc = (struct psycho_softc *)arg; 857 struct psychoreg *regs = sc->sc_regs; 858 859 /* 860 * It's uncorrectable. Dump the regs and panic. 861 */ 862 863 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 864 sc->sc_dev.dv_xname, 865 (long long)regs->psy_pcictl[0].pci_afar, 866 (long long)regs->psy_pcictl[0].pci_afsr); 867 return (1); 868 } 869 static int 870 psycho_bus_b(arg) 871 void *arg; 872 { 873 struct psycho_softc *sc = (struct psycho_softc *)arg; 874 struct psychoreg *regs = sc->sc_regs; 875 876 /* 877 * It's uncorrectable. Dump the regs and panic. 878 */ 879 880 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 881 sc->sc_dev.dv_xname, 882 (long long)regs->psy_pcictl[0].pci_afar, 883 (long long)regs->psy_pcictl[0].pci_afsr); 884 return (1); 885 } 886 887 static int 888 psycho_powerfail(arg) 889 void *arg; 890 { 891 struct psycho_softc *sc = (struct psycho_softc *)arg; 892 893 /* 894 * We lost power. Queue a callback with thread context to 895 * handle all the real work. 896 */ 897 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 898 sc->sc_powerpressed = 1; 899 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 900 } 901 return (1); 902 } 903 904 static 905 int psycho_wakeup(arg) 906 void *arg; 907 { 908 struct psycho_softc *sc = (struct psycho_softc *)arg; 909 910 /* 911 * Gee, we don't really have a framework to deal with this 912 * properly. 913 */ 914 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 915 return (1); 916 } 917 918 919 920 /* 921 * initialise the IOMMU.. 922 */ 923 void 924 psycho_iommu_init(sc, tsbsize) 925 struct psycho_softc *sc; 926 int tsbsize; 927 { 928 char *name; 929 struct iommu_state *is = sc->sc_is; 930 u_int32_t iobase = -1; 931 int *vdma = NULL; 932 int nitem; 933 934 /* punch in our copies */ 935 is->is_bustag = sc->sc_bustag; 936 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 937 offsetof(struct psychoreg, psy_iommu), 938 sizeof (struct iommureg), 939 &is->is_iommu); 940 941 /* 942 * Separate the men from the boys. Get the `virtual-dma' 943 * property for sabre and use that to make sure the damn 944 * iommu works. 945 * 946 * We could query the `#virtual-dma-size-cells' and 947 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 948 */ 949 if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 950 (void *)&vdma)) { 951 /* Damn. Gotta use these values. */ 952 iobase = vdma[0]; 953 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 954 switch (vdma[1]) { 955 TSBCASE(1); TSBCASE(2); TSBCASE(3); 956 TSBCASE(4); TSBCASE(5); TSBCASE(6); 957 default: 958 printf("bogus tsb size %x, using 7\n", vdma[1]); 959 TSBCASE(7); 960 } 961 #undef TSBCASE 962 } 963 964 /* give us a nice name.. */ 965 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 966 if (name == 0) 967 panic("couldn't malloc iommu name"); 968 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 969 970 iommu_init(name, is, tsbsize, iobase); 971 } 972 973 /* 974 * below here is bus space and bus DMA support 975 */ 976 bus_space_tag_t 977 psycho_alloc_bus_tag(pp, type) 978 struct psycho_pbm *pp; 979 int type; 980 { 981 struct psycho_softc *sc = pp->pp_sc; 982 bus_space_tag_t bt; 983 984 bt = (bus_space_tag_t) 985 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 986 if (bt == NULL) 987 panic("could not allocate psycho bus tag"); 988 989 bzero(bt, sizeof *bt); 990 bt->cookie = pp; 991 bt->parent = sc->sc_bustag; 992 bt->type = type; 993 bt->sparc_bus_map = _psycho_bus_map; 994 bt->sparc_bus_mmap = psycho_bus_mmap; 995 bt->sparc_intr_establish = psycho_intr_establish; 996 return (bt); 997 } 998 999 bus_dma_tag_t 1000 psycho_alloc_dma_tag(pp) 1001 struct psycho_pbm *pp; 1002 { 1003 struct psycho_softc *sc = pp->pp_sc; 1004 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1005 1006 dt = (bus_dma_tag_t) 1007 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1008 if (dt == NULL) 1009 panic("could not allocate psycho DMA tag"); 1010 1011 bzero(dt, sizeof *dt); 1012 dt->_cookie = pp; 1013 dt->_parent = pdt; 1014 #define PCOPY(x) dt->x = pdt->x 1015 PCOPY(_dmamap_create); 1016 PCOPY(_dmamap_destroy); 1017 dt->_dmamap_load = psycho_dmamap_load; 1018 PCOPY(_dmamap_load_mbuf); 1019 PCOPY(_dmamap_load_uio); 1020 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1021 dt->_dmamap_unload = psycho_dmamap_unload; 1022 dt->_dmamap_sync = psycho_dmamap_sync; 1023 dt->_dmamem_alloc = psycho_dmamem_alloc; 1024 dt->_dmamem_free = psycho_dmamem_free; 1025 dt->_dmamem_map = psycho_dmamem_map; 1026 dt->_dmamem_unmap = psycho_dmamem_unmap; 1027 PCOPY(_dmamem_mmap); 1028 #undef PCOPY 1029 return (dt); 1030 } 1031 1032 /* 1033 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1034 * PCI physical addresses. 1035 */ 1036 1037 static int 1038 get_childspace(type) 1039 int type; 1040 { 1041 int ss; 1042 1043 switch (type) { 1044 case PCI_CONFIG_BUS_SPACE: 1045 ss = 0x00; 1046 break; 1047 case PCI_IO_BUS_SPACE: 1048 ss = 0x01; 1049 break; 1050 case PCI_MEMORY_BUS_SPACE: 1051 ss = 0x02; 1052 break; 1053 #if 0 1054 /* we don't do 64 bit memory space */ 1055 case PCI_MEMORY64_BUS_SPACE: 1056 ss = 0x03; 1057 break; 1058 #endif 1059 default: 1060 panic("get_childspace: unknown bus type"); 1061 } 1062 1063 return (ss); 1064 } 1065 1066 static struct psycho_ranges * 1067 get_psychorange(pp, ss) 1068 struct psycho_pbm *pp; 1069 int ss; 1070 { 1071 int i; 1072 1073 for (i = 0; i < pp->pp_nrange; i++) { 1074 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1075 return (&pp->pp_range[i]); 1076 } 1077 /* not found */ 1078 return (NULL); 1079 } 1080 1081 static int 1082 _psycho_bus_map(t, offset, size, flags, unused, hp) 1083 bus_space_tag_t t; 1084 bus_addr_t offset; 1085 bus_size_t size; 1086 int flags; 1087 vaddr_t unused; 1088 bus_space_handle_t *hp; 1089 { 1090 struct psycho_pbm *pp = t->cookie; 1091 struct psycho_softc *sc = pp->pp_sc; 1092 struct psycho_ranges *pr; 1093 bus_addr_t paddr; 1094 int ss; 1095 1096 DPRINTF(PDB_BUSMAP, 1097 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1098 t->type, (unsigned long long)offset, 1099 (unsigned long long)size, flags)); 1100 1101 ss = get_childspace(t->type); 1102 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1103 1104 pr = get_psychorange(pp, ss); 1105 if (pr != NULL) { 1106 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1107 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1108 "space %lx offset %lx paddr %qx\n", 1109 (long)ss, (long)offset, 1110 (unsigned long long)paddr)); 1111 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1112 flags, 0, hp)); 1113 } 1114 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1115 return (EINVAL); 1116 } 1117 1118 static paddr_t 1119 psycho_bus_mmap(t, paddr, off, prot, flags) 1120 bus_space_tag_t t; 1121 bus_addr_t paddr; 1122 off_t off; 1123 int prot; 1124 int flags; 1125 { 1126 bus_addr_t offset = paddr; 1127 struct psycho_pbm *pp = t->cookie; 1128 struct psycho_softc *sc = pp->pp_sc; 1129 struct psycho_ranges *pr; 1130 int ss; 1131 1132 ss = get_childspace(t->type); 1133 1134 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1135 prot, flags, (unsigned long long)paddr)); 1136 1137 pr = get_psychorange(pp, ss); 1138 if (pr != NULL) { 1139 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1140 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1141 "space %lx offset %lx paddr %qx\n", 1142 (long)ss, (long)offset, 1143 (unsigned long long)paddr)); 1144 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1145 prot, flags)); 1146 } 1147 1148 return (-1); 1149 } 1150 1151 /* 1152 * Get a PCI offset address from bus_space_handle_t. 1153 */ 1154 bus_addr_t 1155 psycho_bus_offset(t, hp) 1156 bus_space_tag_t t; 1157 bus_space_handle_t *hp; 1158 { 1159 struct psycho_pbm *pp = t->cookie; 1160 struct psycho_ranges *pr; 1161 bus_addr_t addr, offset; 1162 vaddr_t va; 1163 int ss; 1164 1165 addr = hp->_ptr; 1166 ss = get_childspace(t->type); 1167 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1168 " cspace %d", t->type, addr, ss)); 1169 1170 pr = get_psychorange(pp, ss); 1171 if (pr != NULL) { 1172 if (!PHYS_ASI(hp->_asi)) { 1173 va = trunc_page((vaddr_t)addr); 1174 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1175 DPRINTF(PDB_BUSMAP, 1176 ("\n pmap_extract FAILED\n")); 1177 return (-1); 1178 } 1179 addr += hp->_ptr & PGOFSET; 1180 } 1181 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1182 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1183 " offset %" PRIx64 "\n", addr, offset)); 1184 return (offset); 1185 } 1186 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1187 return (-1); 1188 } 1189 1190 1191 /* 1192 * install an interrupt handler for a PCI device 1193 */ 1194 void * 1195 psycho_intr_establish(t, ihandle, level, handler, arg, fastvec) 1196 bus_space_tag_t t; 1197 int ihandle; 1198 int level; 1199 int (*handler) __P((void *)); 1200 void *arg; 1201 void (*fastvec) __P((void)); /* ignored */ 1202 { 1203 struct psycho_pbm *pp = t->cookie; 1204 struct psycho_softc *sc = pp->pp_sc; 1205 struct intrhand *ih; 1206 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 1207 int64_t intrmap = 0; 1208 int ino; 1209 long vec = INTVEC(ihandle); 1210 1211 ih = (struct intrhand *) 1212 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1213 if (ih == NULL) 1214 return (NULL); 1215 1216 /* 1217 * Hunt through all the interrupt mapping regs to look for our 1218 * interrupt vector. 1219 * 1220 * XXX We only compare INOs rather than IGNs since the firmware may 1221 * not provide the IGN and the IGN is constant for all device on that 1222 * PCI controller. This could cause problems for the FFB/external 1223 * interrupt which has a full vector that can be set arbitrarily. 1224 */ 1225 1226 1227 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1228 ino = INTINO(vec); 1229 DPRINTF(PDB_INTR, (" ino %x", ino)); 1230 1231 /* If the device didn't ask for an IPL, use the one encoded. */ 1232 if (level == IPL_NONE) level = INTLEV(vec); 1233 /* If it still has no level, print a warning and assign IPL 2 */ 1234 if (level == IPL_NONE) { 1235 printf("ERROR: no IPL, setting IPL 2.\n"); 1236 level = 2; 1237 } 1238 1239 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1240 (long)ino, intrlev[ino])); 1241 1242 /* Hunt thru obio first */ 1243 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1244 intrclrptr = &sc->sc_regs->scsi_clr_int; 1245 intrmapptr < &sc->sc_regs->ffb0_int_map; 1246 intrmapptr++, intrclrptr++) { 1247 if (INTINO(*intrmapptr) == ino) 1248 goto found; 1249 } 1250 1251 /* Now do PCI interrupts */ 1252 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1253 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1254 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1255 intrmapptr++, intrclrptr += 4) { 1256 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1257 intrclrptr += vec & 0x3; 1258 goto found; 1259 } 1260 } 1261 1262 /* Finally check the two FFB slots */ 1263 intrclrptr = NULL; /* XXX? */ 1264 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1265 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1266 intrmapptr++) { 1267 if (INTVEC(*intrmapptr) == ino) 1268 goto found; 1269 } 1270 1271 printf("Cannot find interrupt vector %lx\n", vec); 1272 return (NULL); 1273 1274 found: 1275 /* Register the map and clear intr registers */ 1276 ih->ih_map = intrmapptr; 1277 ih->ih_clr = intrclrptr; 1278 1279 #ifdef NOT_DEBUG 1280 if (psycho_debug & PDB_INTR) { 1281 long i; 1282 1283 for (i = 0; i < 500000000; i++) 1284 continue; 1285 } 1286 #endif 1287 1288 ih->ih_fun = handler; 1289 ih->ih_arg = arg; 1290 ih->ih_pil = level; 1291 ih->ih_number = ino | sc->sc_ign; 1292 1293 DPRINTF(PDB_INTR, ( 1294 "; installing handler %p arg %p with ino %u pil %u\n", 1295 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1296 1297 intr_establish(ih->ih_pil, ih); 1298 1299 /* 1300 * Enable the interrupt now we have the handler installed. 1301 * Read the current value as we can't change it besides the 1302 * valid bit so so make sure only this bit is changed. 1303 * 1304 * XXXX --- we really should use bus_space for this. 1305 */ 1306 if (intrmapptr) { 1307 intrmap = *intrmapptr; 1308 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1309 (unsigned long long)intrmap)); 1310 1311 /* Enable the interrupt */ 1312 intrmap |= INTMAP_V; 1313 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1314 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1315 (unsigned long long)intrmap)); 1316 *intrmapptr = intrmap; 1317 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1318 (unsigned long long)(intrmap = *intrmapptr))); 1319 } 1320 return (ih); 1321 } 1322 1323 /* 1324 * hooks into the iommu dvma calls. 1325 */ 1326 int 1327 psycho_dmamap_load(t, map, buf, buflen, p, flags) 1328 bus_dma_tag_t t; 1329 bus_dmamap_t map; 1330 void *buf; 1331 bus_size_t buflen; 1332 struct proc *p; 1333 int flags; 1334 { 1335 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1336 1337 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1338 } 1339 1340 void 1341 psycho_dmamap_unload(t, map) 1342 bus_dma_tag_t t; 1343 bus_dmamap_t map; 1344 { 1345 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1346 1347 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1348 } 1349 1350 int 1351 psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags) 1352 bus_dma_tag_t t; 1353 bus_dmamap_t map; 1354 bus_dma_segment_t *segs; 1355 int nsegs; 1356 bus_size_t size; 1357 int flags; 1358 { 1359 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1360 1361 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1362 } 1363 1364 void 1365 psycho_dmamap_sync(t, map, offset, len, ops) 1366 bus_dma_tag_t t; 1367 bus_dmamap_t map; 1368 bus_addr_t offset; 1369 bus_size_t len; 1370 int ops; 1371 { 1372 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1373 1374 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1375 /* Flush the CPU then the IOMMU */ 1376 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1377 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1378 } 1379 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1380 /* Flush the IOMMU then the CPU */ 1381 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1382 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1383 } 1384 1385 } 1386 1387 int 1388 psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1389 bus_dma_tag_t t; 1390 bus_size_t size; 1391 bus_size_t alignment; 1392 bus_size_t boundary; 1393 bus_dma_segment_t *segs; 1394 int nsegs; 1395 int *rsegs; 1396 int flags; 1397 { 1398 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1399 1400 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1401 segs, nsegs, rsegs, flags)); 1402 } 1403 1404 void 1405 psycho_dmamem_free(t, segs, nsegs) 1406 bus_dma_tag_t t; 1407 bus_dma_segment_t *segs; 1408 int nsegs; 1409 { 1410 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1411 1412 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1413 } 1414 1415 int 1416 psycho_dmamem_map(t, segs, nsegs, size, kvap, flags) 1417 bus_dma_tag_t t; 1418 bus_dma_segment_t *segs; 1419 int nsegs; 1420 size_t size; 1421 caddr_t *kvap; 1422 int flags; 1423 { 1424 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1425 1426 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1427 } 1428 1429 void 1430 psycho_dmamem_unmap(t, kva, size) 1431 bus_dma_tag_t t; 1432 caddr_t kva; 1433 size_t size; 1434 { 1435 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1436 1437 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1438 } 1439