1 /* $NetBSD: psycho.c,v 1.128 2019/11/10 21:16:33 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.128 2019/11/10 21:16:33 chs Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 #define PDB_STICK 0x20 74 int psycho_debug = 0x0; 75 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 76 #else 77 #define DPRINTF(l, s) 78 #endif 79 80 #include <sys/param.h> 81 #include <sys/device.h> 82 #include <sys/errno.h> 83 #include <sys/extent.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/time.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #define _SPARC_BUS_DMA_PRIVATE 92 #include <sys/bus.h> 93 #include <machine/autoconf.h> 94 #include <machine/psl.h> 95 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcireg.h> 98 #include <dev/sysmon/sysmon_taskq.h> 99 100 #include <sparc64/dev/iommureg.h> 101 #include <sparc64/dev/iommuvar.h> 102 #include <sparc64/dev/psychoreg.h> 103 #include <sparc64/dev/psychovar.h> 104 105 #include "ioconf.h" 106 107 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 108 pci_chipset_tag_t); 109 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 110 const char *); 111 static void psycho_get_bus_range(int, int *); 112 static void psycho_fixup_bus_range(int, int *); 113 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 114 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 115 uint64_t *); 116 117 /* chipset handlers */ 118 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 119 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 120 pcireg_t); 121 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 122 pci_intr_handle_t, 123 int, int (*)(void *), void *); 124 static int psycho_pci_find_ino(const struct pci_attach_args *, 125 pci_intr_handle_t *); 126 127 /* Interrupt handlers */ 128 static int psycho_ue(void *); 129 static int psycho_ce(void *); 130 static int psycho_bus_a(void *); 131 static int psycho_bus_b(void *); 132 static int psycho_powerfail(void *); 133 static int psycho_wakeup(void *); 134 135 136 /* IOMMU support */ 137 static void psycho_iommu_init(struct psycho_softc *, int); 138 139 /* 140 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 141 * of the bus DMA support is provided by the iommu dvma controller. 142 */ 143 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 144 145 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 146 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 147 vaddr_t, bus_space_handle_t *); 148 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 149 void *, void(*)(void)); 150 151 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 152 bus_size_t, int, bus_dmamap_t *); 153 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 154 bus_size_t, int); 155 156 /* base pci_chipset */ 157 extern struct sparc_pci_chipset _sparc_pci_chipset; 158 159 /* power button handlers */ 160 static void psycho_register_power_button(struct psycho_softc *sc); 161 static void psycho_power_button_pressed(void *arg); 162 163 /* 164 * autoconfiguration 165 */ 166 static int psycho_match(device_t, cfdata_t, void *); 167 static void psycho_attach(device_t, device_t, void *); 168 static int psycho_print(void *aux, const char *p); 169 170 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 171 psycho_match, psycho_attach, NULL, NULL); 172 173 /* 174 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 175 * single PCI bus and does not have a streaming buffer. It often has an APB 176 * (advanced PCI bridge) connected to it, which was designed specifically for 177 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 178 * appears as two "simba"'s underneath the sabre. 179 * 180 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 181 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 182 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 183 * will usually find a "psycho+" since I don't think the original "psycho" 184 * ever shipped, and if it did it would be in the U30. 185 * 186 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 187 * both part of the same IC, they only have a single register space. As such, 188 * they need to be configured together, even though the autoconfiguration will 189 * attach them separately. 190 * 191 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 192 * as pci1 and pci2, although they have been implemented with other PCI bus 193 * numbers on some machines. 194 * 195 * On UltraII machines, there can be any number of "psycho+" ICs, each 196 * providing two PCI buses. 197 * 198 * 199 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 200 * the values of the following interrupts in this order: 201 * 202 * PCI Bus Error (30) 203 * DMA UE (2e) 204 * DMA CE (2f) 205 * Power Fail (25) 206 * 207 * We really should attach handlers for each. 208 * 209 */ 210 211 #define ROM_PCI_NAME "pci" 212 213 struct psycho_names { 214 const char *p_name; 215 int p_type; 216 } psycho_names[] = { 217 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 218 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 219 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 220 { "pci108e,a000", PSYCHO_MODE_SABRE }, 221 { "pci108e,a001", PSYCHO_MODE_SABRE }, 222 { NULL, 0 } 223 }; 224 225 struct psycho_softc *psycho0 = NULL; 226 227 static int 228 psycho_match(device_t parent, cfdata_t match, void *aux) 229 { 230 struct mainbus_attach_args *ma = aux; 231 char *model; 232 int i; 233 234 if (ma->ma_node == 0) 235 return 0; /* no OF node, can't be us */ 236 237 model = prom_getpropstring(ma->ma_node, "model"); 238 /* match on a name of "pci" and a sabre or a psycho */ 239 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 240 for (i=0; psycho_names[i].p_name; i++) 241 if (strcmp(model, psycho_names[i].p_name) == 0) 242 return (1); 243 244 model = prom_getpropstring(ma->ma_node, "compatible"); 245 for (i=0; psycho_names[i].p_name; i++) 246 if (strcmp(model, psycho_names[i].p_name) == 0) 247 return (1); 248 } 249 return (0); 250 } 251 252 #ifdef DEBUG 253 static void psycho_dump_intmap(struct psycho_softc *sc); 254 static void 255 psycho_dump_intmap(struct psycho_softc *sc) 256 { 257 volatile uint64_t *intrmapptr = NULL; 258 259 printf("psycho_dump_intmap: OBIO\n"); 260 261 for (intrmapptr = &sc->sc_regs->scsi_int_map; 262 intrmapptr < &sc->sc_regs->ue_int_map; 263 intrmapptr++) 264 printf("%p: %llx\n", intrmapptr, 265 (unsigned long long)*intrmapptr); 266 267 printf("\tintmap:pci\n"); 268 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 269 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 270 intrmapptr++) 271 printf("%p: %llx\n", intrmapptr, 272 (unsigned long long)*intrmapptr); 273 274 printf("\tintmap:ffb\n"); 275 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 276 intrmapptr <= &sc->sc_regs->ffb1_int_map; 277 intrmapptr++) 278 printf("%p: %llx\n", intrmapptr, 279 (unsigned long long)*intrmapptr); 280 } 281 #endif 282 283 /* 284 * SUNW,psycho initialisation .. 285 * - find the per-psycho registers 286 * - figure out the IGN. 287 * - find our partner psycho 288 * - configure ourselves 289 * - bus range, bus, 290 * - get interrupt-map and interrupt-map-mask 291 * - setup the chipsets. 292 * - if we're the first of the pair, initialise the IOMMU, otherwise 293 * just copy its tags and addresses. 294 */ 295 static void 296 psycho_attach(device_t parent, device_t self, void *aux) 297 { 298 struct psycho_softc *sc = device_private(self); 299 struct psycho_softc *osc = NULL; 300 struct psycho_pbm *pp; 301 struct pcibus_attach_args pba; 302 struct mainbus_attach_args *ma = aux; 303 struct psycho_ranges *pr; 304 prop_dictionary_t dict; 305 bus_space_handle_t bh; 306 uint64_t csr, mem_base; 307 int psycho_br[2], n, i; 308 bus_space_handle_t pci_ctl; 309 char *model = prom_getpropstring(ma->ma_node, "model"); 310 311 aprint_normal("\n"); 312 313 sc->sc_dev = self; 314 sc->sc_node = ma->ma_node; 315 sc->sc_bustag = ma->ma_bustag; 316 sc->sc_dmatag = ma->ma_dmatag; 317 sc->sc_last_stick = 0; 318 319 if (psycho0 == NULL) 320 psycho0 = sc; 321 DPRINTF(PDB_STICK, ("init psycho0 %lx\n", (long)sc)); 322 /* 323 * Identify the device. 324 */ 325 for (i=0; psycho_names[i].p_name; i++) 326 if (strcmp(model, psycho_names[i].p_name) == 0) { 327 sc->sc_mode = psycho_names[i].p_type; 328 goto found; 329 } 330 331 model = prom_getpropstring(ma->ma_node, "compatible"); 332 for (i=0; psycho_names[i].p_name; i++) 333 if (strcmp(model, psycho_names[i].p_name) == 0) { 334 sc->sc_mode = psycho_names[i].p_type; 335 goto found; 336 } 337 338 panic("unknown psycho model %s", model); 339 found: 340 341 /* 342 * The psycho gets three register banks: 343 * (0) per-PBM configuration and status registers 344 * (1) per-PBM PCI configuration space, containing only the 345 * PBM 256-byte PCI header 346 * (2) the shared psycho configuration registers (struct psychoreg) 347 */ 348 349 /* Register layouts are different. stuupid. */ 350 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 351 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 352 353 if (ma->ma_naddress > 2) { 354 sparc_promaddr_to_handle(sc->sc_bustag, 355 ma->ma_address[2], &sc->sc_bh); 356 sparc_promaddr_to_handle(sc->sc_bustag, 357 ma->ma_address[0], &pci_ctl); 358 359 sc->sc_regs = (struct psychoreg *) 360 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 361 } else if (ma->ma_nreg > 2) { 362 363 /* We need to map this in ourselves. */ 364 if (bus_space_map(sc->sc_bustag, 365 ma->ma_reg[2].ur_paddr, 366 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 367 &sc->sc_bh)) 368 panic("psycho_attach: cannot map regs"); 369 sc->sc_regs = (struct psychoreg *) 370 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 371 372 if (bus_space_map(sc->sc_bustag, 373 ma->ma_reg[0].ur_paddr, 374 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 375 &pci_ctl)) 376 panic("psycho_attach: cannot map ctl"); 377 } else 378 panic("psycho_attach: %d not enough registers", 379 ma->ma_nreg); 380 381 } else { 382 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 383 384 if (ma->ma_naddress) { 385 sparc_promaddr_to_handle(sc->sc_bustag, 386 ma->ma_address[0], &sc->sc_bh); 387 sc->sc_regs = (struct psychoreg *) 388 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 389 390 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 391 offsetof(struct psychoreg, psy_pcictl), 392 sizeof(struct pci_ctl), &pci_ctl); 393 } else if (ma->ma_nreg) { 394 395 /* We need to map this in ourselves. */ 396 if (bus_space_map(sc->sc_bustag, 397 ma->ma_reg[0].ur_paddr, 398 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 399 &sc->sc_bh)) 400 panic("psycho_attach: cannot map regs"); 401 sc->sc_regs = (struct psychoreg *) 402 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 403 404 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 405 offsetof(struct psychoreg, psy_pcictl), 406 sizeof(struct pci_ctl), &pci_ctl); 407 } else 408 panic("psycho_attach: %d not enough registers", 409 ma->ma_nreg); 410 } 411 412 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 413 offsetof(struct psychoreg, psy_csr)); 414 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 415 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 416 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 417 418 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 419 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 420 sc->sc_ign); 421 /* 422 * Match other psycho's that are already configured against 423 * the base physical address. This will be the same for a 424 * pair of devices that share register space. 425 */ 426 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 427 428 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 429 430 if (asc == NULL || asc == sc) 431 /* This entry is not there or it is me */ 432 continue; 433 434 if (asc->sc_basepaddr != sc->sc_basepaddr) 435 /* This is an unrelated psycho */ 436 continue; 437 438 /* Found partner */ 439 osc = asc; 440 break; 441 } 442 443 444 /* Oh, dear. OK, lets get started */ 445 446 /* 447 * Setup the PCI control register 448 */ 449 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 450 offsetof(struct pci_ctl, pci_csr)); 451 csr |= PCICTL_MRLM | 452 PCICTL_ARB_PARK | 453 PCICTL_ERRINTEN | 454 PCICTL_4ENABLE; 455 csr &= ~(PCICTL_SERR | 456 PCICTL_CPU_PRIO | 457 PCICTL_ARB_PRIO | 458 PCICTL_RTRYWAIT); 459 bus_space_write_8(sc->sc_bustag, pci_ctl, 460 offsetof(struct pci_ctl, pci_csr), csr); 461 462 463 /* 464 * Allocate our psycho_pbm 465 */ 466 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 467 M_WAITOK | M_ZERO); 468 pp->pp_sc = sc; 469 470 /* grab the psycho ranges */ 471 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 472 473 /* get the bus-range for the psycho */ 474 psycho_get_bus_range(sc->sc_node, psycho_br); 475 476 pba.pba_bus = psycho_br[0]; 477 pba.pba_bridgetag = NULL; 478 479 /* Fix up invalid 0x00-0xff bus-range, as found on SPARCle */ 480 if (psycho_br[0] == 0 && psycho_br[1] == 0xff) 481 psycho_fixup_bus_range(sc->sc_node, psycho_br); 482 483 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 484 aprint_normal("; PCI bus %d", psycho_br[0]); 485 486 pp->pp_pcictl = pci_ctl; 487 488 /* allocate our tags */ 489 pp->pp_memt = psycho_alloc_mem_tag(pp); 490 pp->pp_iot = psycho_alloc_io_tag(pp); 491 pp->pp_dmat = psycho_alloc_dma_tag(pp); 492 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 493 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 494 495 /* allocate a chipset for this */ 496 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 497 pp->pp_pc->spc_busmax = psycho_br[1]; 498 499 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 500 case 0x2000: 501 pp->pp_id = PSYCHO_PBM_A; 502 break; 503 case 0x4000: 504 pp->pp_id = PSYCHO_PBM_B; 505 break; 506 } 507 508 aprint_normal("\n"); 509 510 /* allocate extents for free bus space */ 511 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 512 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 513 514 #ifdef DEBUG 515 if (psycho_debug & PDB_INTR) 516 psycho_dump_intmap(sc); 517 #endif 518 519 /* 520 * And finally, if we're a sabre or the first of a pair of psycho's to 521 * arrive here, start up the IOMMU and get a config space tag. 522 */ 523 if (osc == NULL) { 524 uint64_t timeo; 525 526 /* 527 * Establish handlers for interesting interrupts.... 528 * 529 * XXX We need to remember these and remove this to support 530 * hotplug on the UPA/FHC bus. 531 * 532 * XXX Not all controllers have these, but installing them 533 * is better than trying to sort through this mess. 534 */ 535 psycho_set_intr(sc, 15, psycho_ue, 536 &sc->sc_regs->ue_int_map, 537 &sc->sc_regs->ue_clr_int); 538 psycho_set_intr(sc, 1, psycho_ce, 539 &sc->sc_regs->ce_int_map, 540 &sc->sc_regs->ce_clr_int); 541 psycho_set_intr(sc, 15, psycho_bus_a, 542 &sc->sc_regs->pciaerr_int_map, 543 &sc->sc_regs->pciaerr_clr_int); 544 /* 545 * Netra X1 may hang when the powerfail interrupt is enabled. 546 */ 547 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 548 psycho_set_intr(sc, 15, psycho_powerfail, 549 &sc->sc_regs->power_int_map, 550 &sc->sc_regs->power_clr_int); 551 psycho_register_power_button(sc); 552 } 553 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 554 /* sabre doesn't have these interrupts */ 555 psycho_set_intr(sc, 15, psycho_bus_b, 556 &sc->sc_regs->pciberr_int_map, 557 &sc->sc_regs->pciberr_clr_int); 558 psycho_set_intr(sc, 1, psycho_wakeup, 559 &sc->sc_regs->pwrmgt_int_map, 560 &sc->sc_regs->pwrmgt_clr_int); 561 } 562 563 /* 564 * Apparently a number of machines with psycho and psycho+ 565 * controllers have interrupt latency issues. We'll try 566 * setting the interrupt retry timeout to 0xff which gives us 567 * a retry of 3-6 usec (which is what sysio is set to) for the 568 * moment, which seems to help alleviate this problem. 569 */ 570 timeo = sc->sc_regs->intr_retry_timer; 571 if (timeo > 0xfff) { 572 #ifdef DEBUG 573 printf("decreasing interrupt retry timeout " 574 "from %lx to 0xff\n", (long)timeo); 575 #endif 576 sc->sc_regs->intr_retry_timer = 0xff; 577 } 578 579 /* 580 * Allocate bus node, this contains a prom node per bus. 581 */ 582 pp->pp_pc->spc_busnode = 583 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 584 M_WAITOK | M_ZERO); 585 586 /* 587 * Setup IOMMU and PCI configuration if we're the first 588 * of a pair of psycho's to arrive here. 589 * 590 * We should calculate a TSB size based on amount of RAM 591 * and number of bus controllers and number an type of 592 * child devices. 593 * 594 * For the moment, 32KB should be more than enough. 595 */ 596 sc->sc_is = malloc(sizeof(struct iommu_state), 597 M_DEVBUF, M_WAITOK); 598 599 /* Point the strbuf_ctl at the iommu_state */ 600 pp->pp_sb.sb_is = sc->sc_is; 601 602 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 603 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 604 struct strbuf_ctl *sb = &pp->pp_sb; 605 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 606 607 /* 608 * Initialize the strbuf_ctl. 609 * 610 * The flush sync buffer must be 64-byte aligned. 611 */ 612 sb->sb_flush = (void *)(va & ~0x3f); 613 614 bus_space_subregion(sc->sc_bustag, pci_ctl, 615 offsetof(struct pci_ctl, pci_strbuf), 616 sizeof (struct iommu_strbuf), &sb->sb_sb); 617 618 /* Point our iommu at the strbuf_ctl */ 619 sc->sc_is->is_sb[0] = sb; 620 } 621 622 psycho_iommu_init(sc, 2); 623 624 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 625 626 /* 627 * XXX This is a really ugly hack because PCI config space 628 * is explicitly handled with unmapped accesses. 629 */ 630 i = sc->sc_bustag->type; 631 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 632 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 633 0x01000000, 0, &bh)) 634 panic("could not map psycho PCI configuration space"); 635 sc->sc_bustag->type = i; 636 sc->sc_configaddr = bh; 637 } else { 638 /* Share bus numbers with the pair of mine */ 639 pp->pp_pc->spc_busnode = 640 osc->sc_psycho_this->pp_pc->spc_busnode; 641 642 /* Just copy IOMMU state, config tag and address */ 643 sc->sc_is = osc->sc_is; 644 sc->sc_configtag = osc->sc_configtag; 645 sc->sc_configaddr = osc->sc_configaddr; 646 647 /* Point the strbuf_ctl at the iommu_state */ 648 pp->pp_sb.sb_is = sc->sc_is; 649 650 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 651 struct strbuf_ctl *sb = &pp->pp_sb; 652 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 653 654 /* 655 * Initialize the strbuf_ctl. 656 * 657 * The flush sync buffer must be 64-byte aligned. 658 */ 659 sb->sb_flush = (void *)(va & ~0x3f); 660 661 bus_space_subregion(sc->sc_bustag, pci_ctl, 662 offsetof(struct pci_ctl, pci_strbuf), 663 sizeof (struct iommu_strbuf), &sb->sb_sb); 664 665 /* Point our iommu at the strbuf_ctl */ 666 sc->sc_is->is_sb[1] = sb; 667 } 668 iommu_reset(sc->sc_is); 669 } 670 671 dict = device_properties(self); 672 pr = get_psychorange(pp, 2); /* memory range */ 673 #ifdef DEBUG 674 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 675 #endif 676 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 677 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 678 679 /* 680 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 681 */ 682 pba.pba_flags = sc->sc_psycho_this->pp_flags; 683 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 684 pba.pba_dmat64 = NULL; 685 pba.pba_iot = sc->sc_psycho_this->pp_iot; 686 pba.pba_memt = sc->sc_psycho_this->pp_memt; 687 pba.pba_pc = pp->pp_pc; 688 689 config_found_ia(self, "pcibus", &pba, psycho_print); 690 } 691 692 static int 693 psycho_print(void *aux, const char *p) 694 { 695 696 if (p == NULL) 697 return (UNCONF); 698 return (QUIET); 699 } 700 701 static void 702 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 703 uint64_t *mapper, uint64_t *clearer) 704 { 705 struct intrhand *ih; 706 707 ih = intrhand_alloc(); 708 ih->ih_arg = sc; 709 ih->ih_map = mapper; 710 ih->ih_clr = clearer; 711 ih->ih_fun = handler; 712 ih->ih_pil = ipl; 713 ih->ih_number = INTVEC(*(ih->ih_map)); 714 ih->ih_pending = 0; 715 intr_establish(ipl, ipl != IPL_VM, ih); 716 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 717 } 718 719 /* 720 * power button handlers 721 */ 722 static void 723 psycho_register_power_button(struct psycho_softc *sc) 724 { 725 sysmon_task_queue_init(); 726 727 sc->sc_powerpressed = 0; 728 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 729 if (!sc->sc_smcontext) { 730 aprint_error_dev(sc->sc_dev, "could not allocate power button context\n"); 731 return; 732 } 733 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 734 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 735 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 736 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 737 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 738 } 739 740 static void 741 psycho_power_button_pressed(void *arg) 742 { 743 struct psycho_softc *sc = arg; 744 745 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 746 sc->sc_powerpressed = 0; 747 } 748 749 /* 750 * PCI bus support 751 */ 752 753 /* 754 * allocate a PCI chipset tag and set its cookie. 755 */ 756 static pci_chipset_tag_t 757 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 758 { 759 pci_chipset_tag_t npc; 760 761 npc = malloc(sizeof *npc, M_DEVBUF, M_WAITOK); 762 memcpy(npc, pc, sizeof *pc); 763 npc->cookie = pp; 764 npc->rootnode = node; 765 npc->spc_conf_read = psycho_pci_conf_read; 766 npc->spc_conf_write = psycho_pci_conf_write; 767 npc->spc_intr_map = NULL; 768 npc->spc_intr_establish = psycho_pci_intr_establish; 769 npc->spc_find_ino = psycho_pci_find_ino; 770 771 return (npc); 772 } 773 774 /* 775 * create extent for free bus space, then allocate assigned regions. 776 */ 777 static struct extent * 778 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 779 { 780 struct psycho_registers *pa = NULL; 781 struct psycho_ranges *pr; 782 struct extent *ex; 783 bus_addr_t baddr, addr; 784 bus_size_t bsize, size; 785 int i, num; 786 787 /* get bus space size */ 788 pr = get_psychorange(pp, ss); 789 if (pr == NULL) { 790 printf("psycho_alloc_extent: get_psychorange failed\n"); 791 return NULL; 792 } 793 baddr = 0x00000000; 794 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 795 796 /* get available lists */ 797 num = 0; 798 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 799 printf("psycho_alloc_extent: no \"available\" property\n"); 800 return NULL; 801 } 802 803 /* create extent */ 804 ex = extent_create(name, baddr, bsize - baddr - 1, 0, 0, EX_NOWAIT); 805 if (ex == NULL) { 806 printf("psycho_alloc_extent: extent_create failed\n"); 807 goto ret; 808 } 809 810 /* allocate assigned regions */ 811 for (i = 0; i < num; i++) 812 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 813 /* allocate bus space */ 814 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 815 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 816 if (extent_alloc_region(ex, baddr, addr - baddr, 817 EX_NOWAIT)) { 818 printf("psycho_alloc_extent: " 819 "extent_alloc_region %" PRIx64 "-%" 820 PRIx64 " failed\n", baddr, addr); 821 extent_destroy(ex); 822 ex = NULL; 823 goto ret; 824 } 825 baddr = addr + size; 826 } 827 /* allocate left region if available */ 828 if (baddr < bsize) 829 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 830 printf("psycho_alloc_extent: extent_alloc_region %" 831 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 832 extent_destroy(ex); 833 ex = NULL; 834 goto ret; 835 } 836 837 #ifdef DEBUG 838 /* print extent */ 839 extent_print(ex); 840 #endif 841 842 ret: 843 /* return extent */ 844 free(pa, M_DEVBUF); 845 return ex; 846 } 847 848 /* 849 * grovel the OBP for various psycho properties 850 */ 851 static void 852 psycho_get_bus_range(int node, int *brp) 853 { 854 int n, error; 855 856 n = 2; 857 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 858 if (error) 859 panic("could not get psycho bus-range, error %d", error); 860 if (n != 2) 861 panic("broken psycho bus-range"); 862 DPRINTF(PDB_PROM, ("%s: got `bus-range' for node %08x: %u - %u\n", 863 __func__, node, brp[0], brp[1])); 864 } 865 866 static void 867 psycho_fixup_bus_range(int node0, int *brp0) 868 { 869 int node; 870 int len, busrange[2], *brp; 871 872 DPRINTF(PDB_PROM, 873 ("%s: fixing up `bus-range' for node %08x: %u - %u\n", 874 __func__, node0, brp0[0], brp0[1])); 875 876 /* 877 * Check all nodes under this one and increase the bus range to 878 * match. Recurse through PCI-PCI bridges. Cardbus bridges are 879 * fixed up in pccbb_attach_hook(). Assumes that "bus-range" for 880 * PCI-PCI bridges apart from this one is correct. 881 */ 882 brp0[1] = brp0[0]; 883 node = prom_firstchild(node0); 884 for (node = ((node)); node; node = prom_nextsibling(node)) { 885 len = 2; 886 brp = busrange; 887 if (prom_getprop(node, "bus-range", sizeof(*brp), 888 &len, &brp) != 0) 889 break; 890 if (len != 2) 891 break; 892 psycho_fixup_bus_range(node, busrange); 893 if (brp0[0] > busrange[0] && busrange[0] >= 0) 894 brp0[0] = busrange[0]; 895 if (brp0[1] < busrange[1] && busrange[1] < 256) 896 brp0[1] = busrange[1]; 897 } 898 899 DPRINTF(PDB_PROM, 900 ("%s: fixed up `bus-range' for node %08x: %u - %u\n", 901 __func__, node0, brp[0], brp[1])); 902 } 903 904 static void 905 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 906 { 907 908 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 909 panic("could not get psycho ranges"); 910 DPRINTF(PDB_PROM, ("%s: got `ranges' for node %08x: %d entries\n", 911 __func__, node, *np)); 912 } 913 914 /* 915 * Interrupt handlers. 916 */ 917 918 static int 919 psycho_ue(void *arg) 920 { 921 struct psycho_softc *sc = (struct psycho_softc *)arg; 922 struct psychoreg *regs = sc->sc_regs; 923 struct iommu_state *is = sc->sc_is; 924 uint64_t afsr = regs->psy_ue_afsr; 925 uint64_t afar = regs->psy_ue_afar; 926 psize_t size = PAGE_SIZE << is->is_tsbsize; 927 char bits[128]; 928 929 /* 930 * It's uncorrectable. Dump the regs and panic. 931 */ 932 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 933 aprint_error_dev(sc->sc_dev, 934 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 935 936 /* Sometimes the AFAR points to an IOTSB entry */ 937 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 938 aprint_error_dev(sc->sc_dev, 939 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 940 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 941 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 942 } 943 #ifdef DDB 944 Debugger(); 945 #endif 946 regs->psy_ue_afar = 0; 947 regs->psy_ue_afsr = 0; 948 return (1); 949 } 950 951 static int 952 psycho_ce(void *arg) 953 { 954 struct psycho_softc *sc = (struct psycho_softc *)arg; 955 struct psychoreg *regs = sc->sc_regs; 956 957 /* 958 * It's correctable. Dump the regs and continue. 959 */ 960 aprint_error_dev(sc->sc_dev, 961 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 962 regs->psy_ce_afar, regs->psy_ce_afsr); 963 return (1); 964 } 965 966 static int 967 psycho_bus_a(void *arg) 968 { 969 struct psycho_softc *sc = (struct psycho_softc *)arg; 970 struct psychoreg *regs = sc->sc_regs; 971 972 /* 973 * It's uncorrectable. Dump the regs and panic. 974 */ 975 976 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 977 device_xname(sc->sc_dev), 978 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 979 return (1); 980 } 981 982 static int 983 psycho_bus_b(void *arg) 984 { 985 struct psycho_softc *sc = (struct psycho_softc *)arg; 986 struct psychoreg *regs = sc->sc_regs; 987 988 /* 989 * It's uncorrectable. Dump the regs and panic. 990 */ 991 992 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 993 device_xname(sc->sc_dev), 994 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 995 return (1); 996 } 997 998 static int 999 psycho_powerfail(void *arg) 1000 { 1001 struct psycho_softc *sc = (struct psycho_softc *)arg; 1002 1003 /* 1004 * We lost power. Queue a callback with thread context to 1005 * handle all the real work. 1006 */ 1007 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 1008 sc->sc_powerpressed = 1; 1009 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 1010 } 1011 return (1); 1012 } 1013 1014 static 1015 int psycho_wakeup(void *arg) 1016 { 1017 struct psycho_softc *sc = (struct psycho_softc *)arg; 1018 1019 /* 1020 * Gee, we don't really have a framework to deal with this 1021 * properly. 1022 */ 1023 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 1024 return (1); 1025 } 1026 1027 1028 /* 1029 * initialise the IOMMU.. 1030 */ 1031 void 1032 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 1033 { 1034 char *name; 1035 struct iommu_state *is = sc->sc_is; 1036 uint32_t iobase = -1; 1037 int *vdma = NULL; 1038 int nitem; 1039 1040 /* punch in our copies */ 1041 is->is_bustag = sc->sc_bustag; 1042 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1043 offsetof(struct psychoreg, psy_iommu), 1044 sizeof (struct iommureg), 1045 &is->is_iommu); 1046 1047 /* 1048 * Separate the men from the boys. Get the `virtual-dma' 1049 * property for sabre and use that to make sure the damn 1050 * iommu works. 1051 * 1052 * We could query the `#virtual-dma-size-cells' and 1053 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1054 */ 1055 nitem = 0; 1056 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1057 &vdma)) { 1058 /* Damn. Gotta use these values. */ 1059 iobase = vdma[0]; 1060 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1061 switch (vdma[1]) { 1062 TSBCASE(1); 1063 TSBCASE(2); 1064 TSBCASE(3); 1065 TSBCASE(4); 1066 TSBCASE(5); 1067 TSBCASE(6); 1068 TSBCASE(7); 1069 default: 1070 printf("bogus tsb size %x, using 7\n", vdma[1]); 1071 tsbsize = 7; 1072 } 1073 #undef TSBCASE 1074 } 1075 1076 /* give us a nice name.. */ 1077 name = malloc(32, M_DEVBUF, M_WAITOK); 1078 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 1079 1080 iommu_init(name, is, tsbsize, iobase); 1081 } 1082 1083 /* 1084 * below here is bus space and bus DMA support 1085 */ 1086 bus_space_tag_t 1087 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1088 { 1089 struct psycho_softc *sc = pp->pp_sc; 1090 bus_space_tag_t bt; 1091 1092 bt = malloc(sizeof(struct sparc_bus_space_tag), 1093 M_DEVBUF, M_WAITOK | M_ZERO); 1094 bt->cookie = pp; 1095 bt->parent = sc->sc_bustag; 1096 bt->type = type; 1097 bt->sparc_bus_map = _psycho_bus_map; 1098 bt->sparc_bus_mmap = psycho_bus_mmap; 1099 bt->sparc_intr_establish = psycho_intr_establish; 1100 return (bt); 1101 } 1102 1103 bus_dma_tag_t 1104 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1105 { 1106 struct psycho_softc *sc = pp->pp_sc; 1107 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1108 1109 dt = malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_WAITOK | M_ZERO); 1110 dt->_cookie = pp; 1111 dt->_parent = pdt; 1112 #define PCOPY(x) dt->x = pdt->x 1113 dt->_dmamap_create = psycho_dmamap_create; 1114 PCOPY(_dmamap_destroy); 1115 dt->_dmamap_load = iommu_dvmamap_load; 1116 PCOPY(_dmamap_load_mbuf); 1117 PCOPY(_dmamap_load_uio); 1118 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1119 dt->_dmamap_unload = iommu_dvmamap_unload; 1120 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1121 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1122 else 1123 dt->_dmamap_sync = iommu_dvmamap_sync; 1124 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1125 dt->_dmamem_free = iommu_dvmamem_free; 1126 dt->_dmamem_map = iommu_dvmamem_map; 1127 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1128 PCOPY(_dmamem_mmap); 1129 #undef PCOPY 1130 return (dt); 1131 } 1132 1133 /* 1134 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1135 * PCI physical addresses. 1136 */ 1137 1138 static struct psycho_ranges * 1139 get_psychorange(struct psycho_pbm *pp, int ss) 1140 { 1141 int i; 1142 1143 for (i = 0; i < pp->pp_nrange; i++) { 1144 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1145 return (&pp->pp_range[i]); 1146 } 1147 /* not found */ 1148 return (NULL); 1149 } 1150 1151 static int 1152 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1153 int flags, vaddr_t unused, bus_space_handle_t *hp) 1154 { 1155 struct psycho_pbm *pp = t->cookie; 1156 struct psycho_softc *sc = pp->pp_sc; 1157 struct psycho_ranges *pr; 1158 bus_addr_t paddr; 1159 int ss; 1160 1161 DPRINTF(PDB_BUSMAP, 1162 ("%s: type %d off %qx sz %qx flags %d", 1163 __func__, t->type, (unsigned long long)offset, 1164 (unsigned long long)size, flags)); 1165 1166 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1167 1168 ss = sparc_pci_childspace(t->type); 1169 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1170 1171 pr = get_psychorange(pp, ss); 1172 if (pr != NULL) { 1173 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1174 DPRINTF(PDB_BUSMAP, ("\n%s: mapping paddr " 1175 "space %lx offset %lx paddr %qx\n", 1176 __func__, (long)ss, (long)offset, 1177 (unsigned long long)paddr)); 1178 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1179 flags, 0, hp)); 1180 } 1181 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1182 return (EINVAL); 1183 } 1184 1185 static paddr_t 1186 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1187 int flags) 1188 { 1189 bus_addr_t offset = paddr; 1190 struct psycho_pbm *pp = t->cookie; 1191 struct psycho_softc *sc = pp->pp_sc; 1192 struct psycho_ranges *pr; 1193 int ss; 1194 1195 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1196 1197 ss = sparc_pci_childspace(t->type); 1198 1199 DPRINTF(PDB_BUSMAP, ("%s: prot %x flags %d busaddr %qx\n", 1200 __func__, prot, flags, (unsigned long long)paddr)); 1201 1202 pr = get_psychorange(pp, ss); 1203 if (pr != NULL) { 1204 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1205 DPRINTF(PDB_BUSMAP, ("%s: mapping paddr " 1206 "space %lx offset %lx paddr %qx\n", 1207 __func__, (long)ss, (long)offset, 1208 (unsigned long long)paddr)); 1209 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1210 prot, flags)); 1211 } 1212 1213 return (-1); 1214 } 1215 1216 /* 1217 * Get a PCI offset address from bus_space_handle_t. 1218 */ 1219 bus_addr_t 1220 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1221 { 1222 struct psycho_pbm *pp = t->cookie; 1223 struct psycho_ranges *pr; 1224 bus_addr_t addr, offset; 1225 vaddr_t va; 1226 int ss; 1227 1228 addr = hp->_ptr; 1229 ss = sparc_pci_childspace(t->type); 1230 DPRINTF(PDB_BUSMAP, ("%s: type %d addr %" PRIx64" cspace %d", 1231 __func__, t->type, addr, ss)); 1232 1233 pr = get_psychorange(pp, ss); 1234 if (pr != NULL) { 1235 if (!PHYS_ASI(hp->_asi)) { 1236 va = trunc_page((vaddr_t)addr); 1237 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1238 DPRINTF(PDB_BUSMAP, 1239 ("- pmap_extract FAILED\n")); 1240 return (-1); 1241 } 1242 addr += hp->_ptr & PGOFSET; 1243 } 1244 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1245 DPRINTF(PDB_BUSMAP, ("- paddr %" PRIx64" offset %" PRIx64 "\n", 1246 addr, offset)); 1247 return (offset); 1248 } 1249 DPRINTF(PDB_BUSMAP, ("- FAILED\n")); 1250 return (-1); 1251 } 1252 1253 1254 /* 1255 * install an interrupt handler for a PCI device 1256 */ 1257 void * 1258 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1259 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1260 { 1261 struct psycho_pbm *pp = t->cookie; 1262 struct psycho_softc *sc = pp->pp_sc; 1263 struct intrhand *ih; 1264 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1265 int64_t imap = 0; 1266 int ino; 1267 long vec = INTVEC(ihandle); 1268 1269 ih = intrhand_alloc(); 1270 1271 ih->ih_ivec = ihandle; 1272 1273 /* 1274 * Hunt through all the interrupt mapping regs to look for our 1275 * interrupt vector. 1276 * 1277 * XXX We only compare INOs rather than IGNs since the firmware may 1278 * not provide the IGN and the IGN is constant for all device on that 1279 * PCI controller. This could cause problems for the FFB/external 1280 * interrupt which has a full vector that can be set arbitrarily. 1281 */ 1282 1283 DPRINTF(PDB_INTR, ("%s: ihandle %x vec %lx", __func__, ihandle, vec)); 1284 ino = INTINO(vec); 1285 DPRINTF(PDB_INTR, (" ino %x\n", ino)); 1286 1287 /* If the device didn't ask for an IPL, use the one encoded. */ 1288 if (level == IPL_NONE) level = INTLEV(vec); 1289 /* If it still has no level, print a warning and assign IPL 2 */ 1290 if (level == IPL_NONE) { 1291 printf("ERROR: no IPL, setting IPL 2.\n"); 1292 level = 2; 1293 } 1294 1295 DPRINTF(PDB_INTR, ("%s: intr %lx: %p\nHunting for IRQ...\n", 1296 __func__, (long)ino, intrlev[ino])); 1297 1298 /* 1299 * First look for PCI interrupts, otherwise the PCI A slot 0 1300 * INTA# interrupt might match an unused non-PCI (obio) 1301 * interrupt. 1302 */ 1303 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1304 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1305 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1306 intrmapptr++, intrclrptr += 4) { 1307 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1308 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1309 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1310 continue; 1311 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1312 intrclrptr += vec & 0x3; 1313 goto found; 1314 } 1315 } 1316 1317 /* Now hunt thru obio. */ 1318 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1319 intrclrptr = &sc->sc_regs->scsi_clr_int; 1320 intrmapptr < &sc->sc_regs->ue_int_map; 1321 intrmapptr++, intrclrptr++) { 1322 if (INTINO(*intrmapptr) == ino) 1323 goto found; 1324 } 1325 1326 /* Finally check the two FFB slots */ 1327 intrclrptr = NULL; /* XXX? */ 1328 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1329 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1330 intrmapptr++) { 1331 if (INTVEC(*intrmapptr) == ino) 1332 goto found; 1333 } 1334 1335 printf("Cannot find interrupt vector %lx\n", vec); 1336 free(ih, M_DEVBUF); 1337 return (NULL); 1338 1339 found: 1340 /* Register the map and clear intr registers */ 1341 ih->ih_map = intrmapptr; 1342 ih->ih_clr = intrclrptr; 1343 1344 ih->ih_fun = handler; 1345 ih->ih_arg = arg; 1346 ih->ih_pil = level; 1347 ih->ih_number = ino | sc->sc_ign; 1348 ih->ih_pending = 0; 1349 1350 DPRINTF(PDB_INTR, ( 1351 "%s: installing handler %p arg %p with ino %u pil %u\n", 1352 __func__, handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1353 1354 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1355 1356 /* 1357 * Enable the interrupt now we have the handler installed. 1358 * Read the current value as we can't change it besides the 1359 * valid bit so so make sure only this bit is changed. 1360 * 1361 * XXXX --- we really should use bus_space for this. 1362 */ 1363 if (intrmapptr) { 1364 imap = *intrmapptr; 1365 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", 1366 __func__, (unsigned long long)imap)); 1367 1368 /* Enable the interrupt */ 1369 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1370 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1371 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1372 (unsigned long long)imap)); 1373 *intrmapptr = imap; 1374 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx\n", 1375 (unsigned long long)(imap = *intrmapptr))); 1376 } 1377 if (intrclrptr) { 1378 /* set state to IDLE */ 1379 *intrclrptr = 0; 1380 } 1381 return (ih); 1382 } 1383 1384 /* 1385 * per-controller driver calls 1386 */ 1387 1388 /* assume we are mapped little-endian/side-effect */ 1389 static pcireg_t 1390 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1391 { 1392 struct psycho_pbm *pp = pc->cookie; 1393 struct psycho_softc *sc = pp->pp_sc; 1394 struct cpu_info *ci = curcpu(); 1395 pcireg_t val = (pcireg_t)~0; 1396 int s; 1397 1398 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1399 (long)tag, reg)); 1400 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 1401 1402 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1403 sc->sc_configaddr._asi, 1404 (long long)(sc->sc_configaddr._ptr + 1405 PCITAG_OFFSET(tag) + reg), 1406 (int)PCITAG_OFFSET(tag) + reg)); 1407 1408 s = splhigh(); 1409 ci->ci_pci_probe = true; 1410 membar_Sync(); 1411 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1412 PCITAG_OFFSET(tag) + reg); 1413 membar_Sync(); 1414 if (ci->ci_pci_fault) 1415 val = (pcireg_t)~0; 1416 ci->ci_pci_probe = ci->ci_pci_fault = false; 1417 splx(s); 1418 } 1419 #ifdef DEBUG 1420 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x -", __func__, 1421 (int)PCITAG_OFFSET(tag))); 1422 #endif 1423 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1424 1425 return (val); 1426 } 1427 1428 static void 1429 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1430 { 1431 struct psycho_pbm *pp = pc->cookie; 1432 struct psycho_softc *sc = pp->pp_sc; 1433 1434 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1435 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1436 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1437 sc->sc_configaddr._asi, 1438 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1439 (int)PCITAG_OFFSET(tag) + reg)); 1440 1441 /* If we don't know it, just punt it. */ 1442 if (PCITAG_NODE(tag) == -1) { 1443 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1444 return; 1445 } 1446 1447 if ((unsigned int)reg >= PCI_CONF_SIZE) 1448 return; 1449 1450 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1451 PCITAG_OFFSET(tag) + reg, data); 1452 } 1453 1454 static void * 1455 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1456 int (*func)(void *), void *arg) 1457 { 1458 void *cookie; 1459 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1460 1461 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1462 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1463 1464 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1465 return (cookie); 1466 } 1467 1468 static int 1469 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1470 { 1471 struct psycho_pbm *pp = pa->pa_pc->cookie; 1472 struct psycho_softc *sc = pp->pp_sc; 1473 u_int bus; 1474 u_int dev; 1475 u_int pin; 1476 1477 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1478 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1479 (int)PCITAG_DEV(pa->pa_tag), 1480 (int)PCITAG_FUN(pa->pa_tag))); 1481 DPRINTF(PDB_INTMAP, 1482 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1483 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1484 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1485 PCITAG_NODE(pa->pa_intrtag), 1486 (int)PCITAG_BUS(pa->pa_intrtag), 1487 (int)PCITAG_DEV(pa->pa_intrtag), 1488 (int)PCITAG_FUN(pa->pa_intrtag))); 1489 1490 bus = (pp->pp_id == PSYCHO_PBM_B); 1491 /* 1492 * If we are on a ppb, use the devno on the underlying bus when forming 1493 * the ivec. 1494 */ 1495 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1496 dev = PCITAG_DEV(pa->pa_intrtag); 1497 else 1498 dev = pa->pa_device; 1499 dev--; 1500 1501 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1502 pp->pp_id == PSYCHO_PBM_B) 1503 dev--; 1504 1505 pin = pa->pa_intrpin - 1; 1506 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1507 sc->sc_mode, pp->pp_id, dev, pin)); 1508 1509 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1510 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1511 1512 return (0); 1513 } 1514 1515 /* 1516 * hooks into the iommu dvma calls. 1517 */ 1518 static int 1519 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1520 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1521 bus_dmamap_t *dmamp) 1522 { 1523 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1524 int error; 1525 1526 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1527 boundary, flags, dmamp); 1528 if (error == 0) 1529 (*dmamp)->_dm_cookie = &pp->pp_sb; 1530 return error; 1531 } 1532 1533 /* 1534 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1535 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1536 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1537 */ 1538 static void 1539 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1540 bus_size_t len, int ops) 1541 { 1542 struct psycho_pbm *pp; 1543 struct psycho_softc *sc; 1544 1545 /* If len is 0, then there is nothing to do. */ 1546 if (len == 0) 1547 return; 1548 1549 if (ops & BUS_DMASYNC_POSTREAD) { 1550 pp = (struct psycho_pbm *)t->_cookie; 1551 sc = pp->pp_sc; 1552 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1553 offsetof(struct psychoreg, pci_dma_write_sync)); 1554 } 1555 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1556 } 1557 1558 /* US-IIe STICK support */ 1559 1560 uint64_t 1561 psycho_getstick(void) 1562 { 1563 uint64_t stick; 1564 1565 stick = bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1566 STICK_CNT_LOW) | 1567 (bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1568 STICK_CNT_HIGH) & 0x7fffffff) << 32; 1569 return stick; 1570 } 1571 1572 uint32_t 1573 psycho_getstick32(void) 1574 { 1575 1576 return bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1577 STICK_CNT_LOW); 1578 } 1579 1580 void 1581 psycho_setstick(long cnt) 1582 { 1583 1584 /* 1585 * looks like we can't actually write the STICK counter, so instead we 1586 * prepare sc_last_stick for the coming interrupt setup 1587 */ 1588 #if 0 1589 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1590 STICK_CNT_HIGH, (cnt >> 32)); 1591 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1592 STICK_CNT_LOW, (uint32_t)(cnt & 0xffffffff)); 1593 #endif 1594 1595 if (cnt == 0) { 1596 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1597 STICK_CMP_HIGH, 0); 1598 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1599 STICK_CMP_LOW, 0); 1600 psycho0->sc_last_stick = 0; 1601 } 1602 1603 psycho0->sc_last_stick = psycho_getstick(); 1604 DPRINTF(PDB_STICK, ("%s: %ld\n", __func__, psycho0->sc_last_stick)); 1605 } 1606 1607 void 1608 psycho_nextstick(long diff) 1609 { 1610 uint64_t cmp, now; 1611 1612 /* 1613 * there is no way we'll ever overflow 1614 * the counter is 63 bits wide, at 12MHz that's >24000 years 1615 */ 1616 now = psycho_getstick() + 1000; 1617 cmp = psycho0->sc_last_stick; 1618 1619 while (cmp < now) 1620 cmp += diff; 1621 1622 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1623 STICK_CMP_HIGH, (cmp >> 32) & 0x7fffffff); 1624 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1625 STICK_CMP_LOW, (cmp & 0xffffffff)); 1626 1627 psycho0->sc_last_stick = cmp; 1628 } 1629