1 /* $NetBSD: pci_machdep.c,v 1.37 2003/05/05 07:51:26 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #ifdef DEBUG 36 #define SPDB_CONF 0x01 37 #define SPDB_INTR 0x04 38 #define SPDB_INTMAP 0x08 39 #define SPDB_INTFIX 0x10 40 #define SPDB_PROBE 0x20 41 int sparc_pci_debug = 0x0; 42 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 43 #else 44 #define DPRINTF(l, s) 45 #endif 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/time.h> 50 #include <sys/systm.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #define _SPARC_BUS_DMA_PRIVATE 56 #include <machine/bus.h> 57 #include <machine/autoconf.h> 58 #include <machine/openfirm.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 62 #include <dev/ofw/ofw_pci.h> 63 64 #include <sparc64/dev/iommureg.h> 65 #include <sparc64/dev/iommuvar.h> 66 #include <sparc64/dev/psychoreg.h> 67 #include <sparc64/dev/psychovar.h> 68 #include <sparc64/sparc64/cache.h> 69 70 /* this is a base to be copied */ 71 struct sparc_pci_chipset _sparc_pci_chipset = { 72 NULL, 73 }; 74 75 static int pci_bus_frequency(int node); 76 77 static pcitag_t 78 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 79 { 80 pcitag_t tag; 81 82 tag = PCITAG_CREATE(node, b, d, f); 83 84 /* Enable all the different spaces for this device */ 85 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 86 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 87 PCI_COMMAND_IO_ENABLE); 88 return (tag); 89 } 90 91 /* 92 * functions provided to the MI code. 93 */ 94 95 void 96 pci_attach_hook(parent, self, pba) 97 struct device *parent; 98 struct device *self; 99 struct pcibus_attach_args *pba; 100 { 101 } 102 103 int 104 pci_bus_maxdevs(pc, busno) 105 pci_chipset_tag_t pc; 106 int busno; 107 { 108 109 return 32; 110 } 111 112 pcitag_t 113 pci_make_tag(pc, b, d, f) 114 pci_chipset_tag_t pc; 115 int b; 116 int d; 117 int f; 118 { 119 struct psycho_pbm *pp = pc->cookie; 120 struct ofw_pci_register reg; 121 pcitag_t tag; 122 int (*valid) __P((void *)); 123 int busrange[2]; 124 int node, len; 125 #ifdef DEBUG 126 char name[80]; 127 bzero(name, sizeof(name)); 128 #endif 129 130 /* 131 * Refer to the PCI/CardBus bus node first. 132 * It returns a tag if node is present and bus is valid. 133 */ 134 if (0 <= b && b < 256) { 135 node = (*pp->pp_busnode)[b].node; 136 valid = (*pp->pp_busnode)[b].valid; 137 if (node != 0 && d == 0 && 138 (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg))) 139 return ofpci_make_tag(pc, node, b, d, f); 140 } 141 142 /* 143 * Hunt for the node that corresponds to this device 144 * 145 * We could cache this info in an array in the parent 146 * device... except then we have problems with devices 147 * attached below pci-pci bridges, and we would need to 148 * add special code to the pci-pci bridge to cache this 149 * info. 150 */ 151 152 tag = PCITAG_CREATE(-1, b, d, f); 153 node = pc->rootnode; 154 /* 155 * First make sure we're on the right bus. If our parent 156 * has a bus-range property and we're not in the range, 157 * then we're obviously on the wrong bus. So go up one 158 * level. 159 */ 160 #ifdef DEBUG 161 if (sparc_pci_debug & SPDB_PROBE) { 162 OF_getprop(node, "name", &name, sizeof(name)); 163 printf("curnode %x %s\n", node, name); 164 } 165 #endif 166 #if 0 167 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 168 sizeof(busrange)) == sizeof(busrange)) && 169 (b < busrange[0] || b > busrange[1])) { 170 /* Out of range, go up one */ 171 node = OF_parent(node); 172 #ifdef DEBUG 173 if (sparc_pci_debug & SPDB_PROBE) { 174 OF_getprop(node, "name", &name, sizeof(name)); 175 printf("going up to node %x %s\n", node, name); 176 } 177 #endif 178 } 179 #endif 180 /* 181 * Now traverse all peers until we find the node or we find 182 * the right bridge. 183 * 184 * XXX We go up one and down one to make sure nobody's missed. 185 * but this should not be necessary. 186 */ 187 for (node = ((node)); node; node = OF_peer(node)) { 188 189 #ifdef DEBUG 190 if (sparc_pci_debug & SPDB_PROBE) { 191 OF_getprop(node, "name", &name, sizeof(name)); 192 printf("checking node %x %s\n", node, name); 193 } 194 #endif 195 196 #if 1 197 /* 198 * Check for PCI-PCI bridges. If the device we want is 199 * in the bus-range for that bridge, work our way down. 200 */ 201 while ((OF_getprop(node, "bus-range", (void *)&busrange, 202 sizeof(busrange)) == sizeof(busrange)) && 203 (b >= busrange[0] && b <= busrange[1])) { 204 /* Go down 1 level */ 205 node = OF_child(node); 206 #ifdef DEBUG 207 if (sparc_pci_debug & SPDB_PROBE) { 208 OF_getprop(node, "name", &name, sizeof(name)); 209 printf("going down to node %x %s\n", 210 node, name); 211 } 212 #endif 213 } 214 #endif 215 /* 216 * We only really need the first `reg' property. 217 * 218 * For simplicity, we'll query the `reg' when we 219 * need it. Otherwise we could malloc() it, but 220 * that gets more complicated. 221 */ 222 len = OF_getproplen(node, "reg"); 223 if (len < sizeof(reg)) 224 continue; 225 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 226 panic("pci_probe_bus: OF_getprop len botch"); 227 228 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 229 continue; 230 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 231 continue; 232 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 233 continue; 234 235 /* Got a match */ 236 tag = ofpci_make_tag(pc, node, b, d, f); 237 238 return (tag); 239 } 240 /* No device found -- return a dead tag */ 241 return (tag); 242 } 243 244 void 245 pci_decompose_tag(pc, tag, bp, dp, fp) 246 pci_chipset_tag_t pc; 247 pcitag_t tag; 248 int *bp, *dp, *fp; 249 { 250 251 if (bp != NULL) 252 *bp = PCITAG_BUS(tag); 253 if (dp != NULL) 254 *dp = PCITAG_DEV(tag); 255 if (fp != NULL) 256 *fp = PCITAG_FUN(tag); 257 } 258 259 static int 260 pci_bus_frequency(int node) 261 { 262 int len, bus_frequency; 263 264 len = OF_getproplen(node, "clock-frequency"); 265 if (len < sizeof(bus_frequency)) { 266 DPRINTF(SPDB_PROBE, 267 ("pci_bus_frequency: clock-frequency len %d too small\n", 268 len)); 269 return 33; 270 } 271 if (OF_getprop(node, "clock-frequency", &bus_frequency, 272 sizeof(bus_frequency)) != len) { 273 DPRINTF(SPDB_PROBE, 274 ("pci_bus_frequency: could not read clock-frequency\n")); 275 return 33; 276 } 277 return bus_frequency / 1000000; 278 } 279 280 int 281 pci_enumerate_bus(struct pci_softc *sc, 282 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 283 { 284 struct ofw_pci_register reg; 285 pci_chipset_tag_t pc = sc->sc_pc; 286 pcitag_t tag; 287 pcireg_t class, csr, bhlc, ic; 288 int node, b, d, f, ret; 289 int bus_frequency, lt, cl, cacheline; 290 char name[30]; 291 extern int pci_config_dump; 292 293 if (sc->sc_bridgetag) 294 node = PCITAG_NODE(*sc->sc_bridgetag); 295 else 296 node = pc->rootnode; 297 298 bus_frequency = pci_bus_frequency(node); 299 300 /* 301 * Make sure the cache line size is at least as big as the 302 * ecache line and the streaming cache (64 byte). 303 */ 304 cacheline = max(cacheinfo.ec_linesize, 64); 305 KASSERT((cacheline/64)*64 == cacheline && 306 (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline && 307 (cacheline/4)*4 == cacheline); 308 309 /* Turn on parity for the bus. */ 310 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 311 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 312 csr |= PCI_COMMAND_PARITY_ENABLE; 313 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 314 315 /* 316 * Initialize the latency timer register. 317 * The value 0x40 is from Solaris. 318 */ 319 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 320 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 321 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 322 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 323 324 if (pci_config_dump) pci_conf_print(pc, tag, NULL); 325 326 for (node = OF_child(node); node != 0 && node != -1; 327 node = OF_peer(node)) { 328 name[0] = name[29] = 0; 329 OF_getprop(node, "name", name, sizeof(name)); 330 331 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 332 sizeof(class)) 333 continue; 334 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 335 panic("pci_enumerate_bus: \"%s\" regs too small", name); 336 337 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 338 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 339 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 340 341 if (sc->sc_bus != b) { 342 printf("%s: WARNING: incorrect bus # for \"%s\" " 343 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f); 344 continue; 345 } 346 347 tag = ofpci_make_tag(pc, node, b, d, f); 348 349 /* 350 * Turn on parity and fast-back-to-back for the device. 351 */ 352 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 353 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 354 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 355 csr |= PCI_COMMAND_PARITY_ENABLE; 356 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 357 358 /* 359 * Initialize the latency timer register for busmaster 360 * devices to work properly. 361 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 362 * Also initialize the cache line size register. 363 * Solaris anytime sets this register to the value 0x10. 364 */ 365 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 366 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 367 368 lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 369 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 370 lt = PCI_LATTIMER(bhlc); 371 372 cl = PCI_CACHELINE(bhlc); 373 if (cl == 0) 374 cl = cacheline; 375 376 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 377 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 378 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 379 (cl << PCI_CACHELINE_SHIFT); 380 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 381 382 ret = pci_probe_device(sc, tag, match, pap); 383 if (match != NULL && ret != 0) 384 return (ret); 385 } 386 return (0); 387 } 388 389 /* assume we are mapped little-endian/side-effect */ 390 pcireg_t 391 pci_conf_read(pc, tag, reg) 392 pci_chipset_tag_t pc; 393 pcitag_t tag; 394 int reg; 395 { 396 struct psycho_pbm *pp = pc->cookie; 397 struct psycho_softc *sc = pp->pp_sc; 398 pcireg_t val = (pcireg_t)~0; 399 400 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ", 401 (long)tag, reg)); 402 if (PCITAG_NODE(tag) != -1) { 403 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 404 sc->sc_configaddr._asi, 405 (long long)(sc->sc_configaddr._ptr + 406 PCITAG_OFFSET(tag) + reg), 407 (int)PCITAG_OFFSET(tag) + reg)); 408 409 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 410 PCITAG_OFFSET(tag) + reg); 411 } 412 #ifdef DEBUG 413 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 414 (int)PCITAG_OFFSET(tag))); 415 #endif 416 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 417 418 return (val); 419 } 420 421 void 422 pci_conf_write(pc, tag, reg, data) 423 pci_chipset_tag_t pc; 424 pcitag_t tag; 425 int reg; 426 pcireg_t data; 427 { 428 struct psycho_pbm *pp = pc->cookie; 429 struct psycho_softc *sc = pp->pp_sc; 430 431 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 432 (long)PCITAG_OFFSET(tag), reg, (int)data)); 433 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 434 sc->sc_configaddr._asi, 435 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 436 (int)PCITAG_OFFSET(tag) + reg)); 437 438 /* If we don't know it, just punt it. */ 439 if (PCITAG_NODE(tag) == -1) { 440 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr")); 441 return; 442 } 443 444 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 445 PCITAG_OFFSET(tag) + reg, data); 446 } 447 448 /* 449 * interrupt mapping foo. 450 * XXX: how does this deal with multiple interrupts for a device? 451 */ 452 int 453 pci_intr_map(pa, ihp) 454 struct pci_attach_args *pa; 455 pci_intr_handle_t *ihp; 456 { 457 pcitag_t tag = pa->pa_tag; 458 int interrupts; 459 int len, node = PCITAG_NODE(tag); 460 char devtype[30]; 461 462 len = OF_getproplen(node, "interrupts"); 463 if (len < sizeof(interrupts)) { 464 DPRINTF(SPDB_INTMAP, 465 ("pci_intr_map: interrupts len %d too small\n", len)); 466 return (ENODEV); 467 } 468 if (OF_getprop(node, "interrupts", (void *)&interrupts, 469 sizeof(interrupts)) != len) { 470 DPRINTF(SPDB_INTMAP, 471 ("pci_intr_map: could not read interrupts\n")); 472 return (ENODEV); 473 } 474 475 if (OF_mapintr(node, &interrupts, sizeof(interrupts), 476 sizeof(interrupts)) < 0) { 477 printf("OF_mapintr failed\n"); 478 } 479 /* Try to find an IPL for this type of device. */ 480 if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) { 481 for (len = 0; intrmap[len].in_class; len++) 482 if (strcmp(intrmap[len].in_class, devtype) == 0) { 483 interrupts |= INTLEVENCODE(intrmap[len].in_lev); 484 break; 485 } 486 } 487 488 /* XXXX -- we use the ino. What if there is a valid IGN? */ 489 *ihp = interrupts; 490 return (0); 491 } 492 493 const char * 494 pci_intr_string(pc, ih) 495 pci_chipset_tag_t pc; 496 pci_intr_handle_t ih; 497 { 498 static char str[16]; 499 500 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 501 sprintf(str, "ivec %x", ih); 502 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 503 504 return (str); 505 } 506 507 const struct evcnt * 508 pci_intr_evcnt(pc, ih) 509 pci_chipset_tag_t pc; 510 pci_intr_handle_t ih; 511 { 512 513 /* XXX for now, no evcnt parent reported */ 514 return NULL; 515 } 516 517 void * 518 pci_intr_establish(pc, ih, level, func, arg) 519 pci_chipset_tag_t pc; 520 pci_intr_handle_t ih; 521 int level; 522 int (*func) __P((void *)); 523 void *arg; 524 { 525 void *cookie; 526 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 527 528 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 529 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 530 531 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 532 return (cookie); 533 } 534 535 void 536 pci_intr_disestablish(pc, cookie) 537 pci_chipset_tag_t pc; 538 void *cookie; 539 { 540 541 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 542 543 /* XXX */ 544 panic("can't disestablish PCI interrupts yet"); 545 } 546