1 /* $NetBSD: ffb.c,v 1.57 2016/07/07 06:55:38 msaitoh Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.57 2016/07/07 06:55:38 msaitoh Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 237 ? strtoul(buf, NULL, 10) 238 : 34; 239 240 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 241 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 242 dac = DAC_READ(sc, FFB_DAC_VALUE); 243 sc->sc_dacrev = (dac >> 28) & 0xf; 244 245 if (sc->sc_type == FFB_AFB) { 246 sc->sc_dacrev = 10; 247 sc->sc_needredraw = 0; 248 } else { 249 /* see what kind of DAC we have */ 250 int pnum = (dac & 0x0ffff000) >> 12; 251 if (pnum == 0x236e) { 252 sc->sc_needredraw = 0; 253 } else { 254 sc->sc_needredraw = 1; 255 } 256 } 257 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 258 if (sc->sc_needredraw) 259 printf("%s: found old DAC, enabling redraw on unblank\n", 260 device_xname(sc->sc_dev)); 261 262 /* Check if a console resolution "<device>:r<res>" is set. */ 263 if (sc->sc_console) { 264 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 265 if (out_dev != NULL && strlen(out_dev) != 0 && 266 strstr(out_dev, ":r") != NULL) 267 try_edid = 0; 268 else 269 try_edid = 1; 270 } else 271 try_edid = 1; 272 273 #if FFB_DEBUG > 0 274 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 275 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 277 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 #endif 279 ffb_attach_i2c(sc); 280 281 /* Need to set asynchronous blank during DDC write/read */ 282 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 283 dac = DAC_READ(sc, FFB_DAC_VALUE); 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 286 287 /* Some monitors don't respond first time */ 288 i = 0; 289 while (sc->sc_edid_data[1] == 0 && i++ < 3) 290 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 291 292 /* Remove asynchronous blank */ 293 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 294 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 295 296 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 297 sort_modes(sc->sc_edid_info.edid_modes, 298 &sc->sc_edid_info.edid_preferred_mode, 299 sc->sc_edid_info.edid_nmodes); 300 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 301 for (i = 0; i < EDID_DATA_LEN; i++) { 302 if (i && !(i % 32)) 303 DPRINTF(("\n ")); 304 if (i && !(i % 4)) 305 DPRINTF((" ")); 306 DPRINTF(("%02x", sc->sc_edid_data[i])); 307 } 308 DPRINTF(("\n")); 309 if (ffb_debug) 310 edid_print(&sc->sc_edid_info); 311 312 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 313 prop_dictionary_set(device_properties(self), "EDID", data); 314 prop_object_release(data); 315 316 if (try_edid) 317 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 318 if (ffb_set_vmode(sc, 319 &(sc->sc_edid_info.edid_modes[i]), btype, 320 &(sc->sc_width), &(sc->sc_height))) 321 break; 322 } 323 } else { 324 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 325 } 326 327 ffb_ras_init(sc); 328 329 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 330 331 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 332 FFB_CFFLAG_NOACCEL) == 0); 333 334 wsfont_init(); 335 336 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 337 sc->vd.init_screen = ffb_init_screen; 338 ri = &ffb_console_screen.scr_ri; 339 340 /* we mess with ffb_console_screen only once */ 341 if (sc->sc_console) { 342 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 343 SCREEN_VISIBLE((&ffb_console_screen)); 344 /* 345 * XXX we shouldn't use a global variable for the console 346 * screen 347 */ 348 sc->vd.active = &ffb_console_screen; 349 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 350 } else { 351 if (ffb_console_screen.scr_ri.ri_rows == 0) { 352 /* do some minimal setup to avoid weirdnesses later */ 353 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 354 } else 355 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 356 } 357 358 ffb_stdscreen.nrows = ri->ri_rows; 359 ffb_stdscreen.ncols = ri->ri_cols; 360 ffb_stdscreen.textops = &ri->ri_ops; 361 ffb_stdscreen.capabilities = ri->ri_caps; 362 363 sc->sc_fb.fb_driver = &ffb_fbdriver; 364 sc->sc_fb.fb_type.fb_cmsize = 0; 365 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 366 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 367 sc->sc_fb.fb_type.fb_width = sc->sc_width; 368 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 369 sc->sc_fb.fb_type.fb_height = sc->sc_height; 370 sc->sc_fb.fb_device = sc->sc_dev; 371 fb_attach(&sc->sc_fb, sc->sc_console); 372 373 ffb_clearscreen(sc); 374 375 if (sc->sc_console) { 376 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 377 vcons_replay_msgbuf(&ffb_console_screen); 378 } 379 380 waa.console = sc->sc_console; 381 waa.scrdata = &ffb_screenlist; 382 waa.accessops = &ffb_accessops; 383 waa.accesscookie = &sc->vd; 384 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 385 } 386 387 void 388 ffb_attach_i2c(struct ffb_softc *sc) 389 { 390 391 /* Fill in the i2c tag */ 392 sc->sc_i2c.ic_cookie = sc; 393 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 394 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 395 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 396 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 397 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 398 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 399 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 400 sc->sc_i2c.ic_exec = NULL; 401 } 402 403 int 404 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 405 { 406 struct vcons_data *vd = v; 407 struct ffb_softc *sc = vd->cookie; 408 struct wsdisplay_fbinfo *wdf; 409 struct vcons_screen *ms = vd->active; 410 411 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 412 device_xname(sc->sc_dev), 413 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 414 (char)IOCGROUP(cmd), cmd & 0xff)); 415 416 switch (cmd) { 417 case FBIOGTYPE: 418 *(struct fbtype *)data = sc->sc_fb.fb_type; 419 break; 420 case FBIOGATTR: 421 #define fba ((struct fbgattr *)data) 422 fba->real_type = sc->sc_fb.fb_type.fb_type; 423 fba->owner = 0; /* XXX ??? */ 424 fba->fbtype = sc->sc_fb.fb_type; 425 fba->sattr.flags = 0; 426 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 427 fba->sattr.dev_specific[0] = -1; 428 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 429 fba->emu_types[1] = -1; 430 #undef fba 431 break; 432 433 case FBIOGETCMAP: 434 case FBIOPUTCMAP: 435 return EIO; 436 437 case FBIOGVIDEO: 438 case FBIOSVIDEO: 439 return ffb_blank(sc, cmd == FBIOGVIDEO? 440 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 441 (u_int *)data); 442 break; 443 case FBIOGCURSOR: 444 case FBIOSCURSOR: 445 /* the console driver is not using the hardware cursor */ 446 break; 447 case FBIOGCURPOS: 448 printf("%s: FBIOGCURPOS not implemented\n", 449 device_xname(sc->sc_dev)); 450 return EIO; 451 case FBIOSCURPOS: 452 printf("%s: FBIOSCURPOS not implemented\n", 453 device_xname(sc->sc_dev)); 454 return EIO; 455 case FBIOGCURMAX: 456 printf("%s: FBIOGCURMAX not implemented\n", 457 device_xname(sc->sc_dev)); 458 return EIO; 459 460 case WSDISPLAYIO_GTYPE: 461 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 462 break; 463 case WSDISPLAYIO_SMODE: 464 { 465 if (sc->sc_mode != *(u_int *)data) { 466 sc->sc_mode = *(u_int *)data; 467 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 468 (sc->sc_locked == 0)) { 469 ffb_ras_init(sc); 470 vcons_redraw_screen(ms); 471 } 472 } 473 } 474 break; 475 case WSDISPLAYIO_GINFO: 476 wdf = (void *)data; 477 wdf->height = sc->sc_height; 478 wdf->width = sc->sc_width; 479 wdf->depth = 32; 480 wdf->cmsize = 256; /* XXX */ 481 break; 482 #ifdef WSDISPLAYIO_LINEBYTES 483 case WSDISPLAYIO_LINEBYTES: 484 *(u_int *)data = sc->sc_linebytes; 485 break; 486 #endif 487 case WSDISPLAYIO_GETCMAP: 488 break;/* XXX */ 489 490 case WSDISPLAYIO_PUTCMAP: 491 break;/* XXX */ 492 493 case WSDISPLAYIO_SVIDEO: 494 case WSDISPLAYIO_GVIDEO: 495 return(ffb_blank(sc, cmd, (u_int *)data)); 496 break; 497 498 case WSDISPLAYIO_GCURPOS: 499 case WSDISPLAYIO_SCURPOS: 500 case WSDISPLAYIO_GCURMAX: 501 case WSDISPLAYIO_GCURSOR: 502 case WSDISPLAYIO_SCURSOR: 503 return EIO; /* not supported yet */ 504 break; 505 506 case WSDISPLAYIO_GET_EDID: { 507 struct wsdisplayio_edid_info *d = data; 508 return wsdisplayio_get_edid(sc->sc_dev, d); 509 } 510 511 case WSDISPLAYIO_GET_FBINFO: { 512 struct wsdisplayio_fbinfo *fbi = data; 513 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 514 } 515 516 default: 517 return EPASSTHROUGH; 518 } 519 520 return (0); 521 } 522 523 /* blank/unblank the screen */ 524 static int 525 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 526 { 527 struct vcons_screen *ms = sc->vd.active; 528 u_int val; 529 530 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 531 val = DAC_READ(sc, FFB_DAC_VALUE); 532 533 switch (cmd) { 534 case WSDISPLAYIO_GVIDEO: 535 *data = val & 1; 536 return(0); 537 break; 538 case WSDISPLAYIO_SVIDEO: 539 if (*data == WSDISPLAYIO_VIDEO_OFF) 540 val &= ~1; 541 else if (*data == WSDISPLAYIO_VIDEO_ON) 542 val |= 1; 543 else 544 return(EINVAL); 545 break; 546 default: 547 return(EINVAL); 548 } 549 550 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 551 DAC_WRITE(sc, FFB_DAC_VALUE, val); 552 553 if ((val & 1) && sc->sc_needredraw) { 554 if (ms != NULL) { 555 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 556 (sc->sc_locked == 0)) { 557 ffb_ras_init(sc); 558 vcons_redraw_screen(ms); 559 } 560 } 561 } 562 563 return(0); 564 } 565 566 paddr_t 567 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 568 { 569 struct vcons_data *vd = vsc; 570 struct ffb_softc *sc = vd->cookie; 571 int i; 572 573 switch (sc->sc_mode) { 574 case WSDISPLAYIO_MODE_MAPPED: 575 for (i = 0; i < sc->sc_nreg; i++) { 576 /* Before this set? */ 577 if (off < sc->sc_addrs[i]) 578 continue; 579 /* After this set? */ 580 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 581 continue; 582 583 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 584 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 585 } 586 break; 587 #ifdef WSDISPLAYIO_MODE_DUMBFB 588 case WSDISPLAYIO_MODE_DUMBFB: 589 if (sc->sc_nreg < FFB_REG_DFB24) 590 break; 591 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 592 return (bus_space_mmap(sc->sc_bt, 593 sc->sc_addrs[FFB_REG_DFB24], off, prot, 594 BUS_SPACE_MAP_LINEAR)); 595 break; 596 #endif 597 } 598 return (-1); 599 } 600 601 void 602 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 603 { 604 int32_t cache = sc->sc_fifo_cache; 605 606 if (cache < n) { 607 do { 608 cache = FBC_READ(sc, FFB_FBC_UCSR); 609 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 610 } while (cache < n); 611 } 612 sc->sc_fifo_cache = cache - n; 613 } 614 615 void 616 ffb_ras_wait(struct ffb_softc *sc) 617 { 618 uint32_t ucsr, r; 619 620 while (1) { 621 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 622 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 623 break; 624 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 625 if (r != 0) 626 FBC_WRITE(sc, FFB_FBC_UCSR, r); 627 } 628 } 629 630 void 631 ffb_ras_init(struct ffb_softc *sc) 632 { 633 uint32_t fbc; 634 635 if (sc->sc_width > 1280) { 636 DPRINTF(("ffb_ras_init: high resolution.\n")); 637 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 638 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 639 } else { 640 DPRINTF(("ffb_ras_init: standard resolution.\n")); 641 fbc = FFB_FBC_XE_OFF; 642 } 643 ffb_ras_fifo_wait(sc, 7); 644 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 645 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 646 FBC_WRITE(sc, FFB_FBC_PPC, 647 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 648 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 649 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 650 651 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 652 FFB_FBC_RGBE_MASK; 653 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 654 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 655 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 656 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 657 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 658 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 659 ffb_ras_fifo_wait(sc, 5); 660 sc->sc_fg_cache = 0; 661 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 662 sc->sc_bg_cache = 0; 663 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache); 664 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 665 FFB_BLENDC_DF_ONE_M_A | 666 FFB_BLENDC_SF_A); 667 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 668 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 669 ffb_ras_wait(sc); 670 } 671 672 void 673 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 674 { 675 struct rasops_info *ri = cookie; 676 struct vcons_screen *scr = ri->ri_hw; 677 struct ffb_softc *sc = scr->scr_cookie; 678 679 if (row < 0) { 680 n += row; 681 row = 0; 682 } 683 if (row + n > ri->ri_rows) 684 n = ri->ri_rows - row; 685 if (n <= 0) 686 return; 687 688 ffb_ras_fill(sc); 689 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 690 ffb_ras_fifo_wait(sc, 4); 691 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 692 FBC_WRITE(sc, FFB_FBC_BY, 0); 693 FBC_WRITE(sc, FFB_FBC_BX, 0); 694 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 695 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 696 } else { 697 row *= ri->ri_font->fontheight; 698 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 699 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 700 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 701 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 702 } 703 SYNC; 704 } 705 706 void 707 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 708 { 709 struct rasops_info *ri = cookie; 710 struct vcons_screen *scr = ri->ri_hw; 711 struct ffb_softc *sc = scr->scr_cookie; 712 713 if ((row < 0) || (row >= ri->ri_rows)) 714 return; 715 if (col < 0) { 716 n += col; 717 col = 0; 718 } 719 if (col + n > ri->ri_cols) 720 n = ri->ri_cols - col; 721 if (n <= 0) 722 return; 723 n *= ri->ri_font->fontwidth; 724 col *= ri->ri_font->fontwidth; 725 row *= ri->ri_font->fontheight; 726 727 ffb_ras_fill(sc); 728 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 729 ffb_ras_fifo_wait(sc, 4); 730 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 731 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 732 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 733 FBC_WRITE(sc, FFB_FBC_BW, n); 734 SYNC; 735 } 736 737 void 738 ffb_ras_fill(struct ffb_softc *sc) 739 { 740 ffb_ras_fifo_wait(sc, 3); 741 FBC_WRITE(sc, FFB_FBC_PPC, 742 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 743 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 744 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 745 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 746 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 747 SYNC; 748 } 749 750 void 751 ffb_ras_invert(struct ffb_softc *sc) 752 { 753 ffb_ras_fifo_wait(sc, 3); 754 FBC_WRITE(sc, FFB_FBC_PPC, 755 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 756 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 757 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 758 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 759 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 760 SYNC; 761 } 762 763 void 764 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 765 { 766 struct rasops_info *ri = cookie; 767 struct vcons_screen *scr = ri->ri_hw; 768 struct ffb_softc *sc = scr->scr_cookie; 769 770 if (dst == src) 771 return; 772 if (src < 0) { 773 n += src; 774 src = 0; 775 } 776 if ((src + n) > ri->ri_rows) 777 n = ri->ri_rows - src; 778 if (dst < 0) { 779 n += dst; 780 dst = 0; 781 } 782 if ((dst + n) > ri->ri_rows) 783 n = ri->ri_rows - dst; 784 if (n <= 0) 785 return; 786 n *= ri->ri_font->fontheight; 787 src *= ri->ri_font->fontheight; 788 dst *= ri->ri_font->fontheight; 789 790 ffb_ras_fifo_wait(sc, 9); 791 FBC_WRITE(sc, FFB_FBC_PPC, 792 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 793 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 794 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 795 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 796 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 797 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 798 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 799 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 800 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 801 FBC_WRITE(sc, FFB_FBC_BH, n); 802 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 803 SYNC; 804 } 805 806 static void 807 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 808 { 809 ffb_ras_fifo_wait(sc, 1); 810 if (fg == sc->sc_fg_cache) 811 return; 812 sc->sc_fg_cache = fg; 813 FBC_WRITE(sc, FFB_FBC_FG, fg); 814 SYNC; 815 } 816 817 static void 818 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 819 { 820 ffb_ras_fifo_wait(sc, 1); 821 if (bg == sc->sc_bg_cache) 822 return; 823 sc->sc_bg_cache = bg; 824 FBC_WRITE(sc, FFB_FBC_BG, bg); 825 SYNC; 826 } 827 828 /* frame buffer generic driver support functions */ 829 static void 830 ffbfb_unblank(device_t dev) 831 { 832 struct ffb_softc *sc = device_private(dev); 833 struct vcons_screen *ms = sc->vd.active; 834 u_int on = 1; 835 int redraw = 0; 836 837 ffb_ras_init(sc); 838 if (sc->sc_locked) { 839 sc->sc_locked = 0; 840 redraw = 1; 841 } 842 843 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 844 #if 0 845 if ((sc->vd.active != &ffb_console_screen) && 846 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 847 /* 848 * force-switch to the console screen. 849 * Caveat: the higher layer will think we're still on the 850 * other screen 851 */ 852 853 SCREEN_INVISIBLE(sc->vd.active); 854 sc->vd.active = &ffb_console_screen; 855 SCREEN_VISIBLE(sc->vd.active); 856 ms = sc->vd.active; 857 redraw = 1; 858 } 859 #endif 860 if (redraw) { 861 vcons_redraw_screen(ms); 862 } 863 } 864 865 int 866 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 867 { 868 struct ffb_softc *sc; 869 870 sc = device_lookup_private(&ffb_cd, minor(dev)); 871 if (sc == NULL) 872 return ENXIO; 873 874 sc->sc_locked = 1; 875 return 0; 876 } 877 878 int 879 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 880 { 881 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 882 struct vcons_screen *ms = sc->vd.active; 883 884 sc->sc_locked = 0; 885 if (ms != NULL) { 886 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 887 (sc->sc_locked == 0)) { 888 ffb_ras_init(sc); 889 vcons_redraw_screen(ms); 890 } 891 } 892 return 0; 893 } 894 895 int 896 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 897 { 898 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 899 900 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 901 } 902 903 paddr_t 904 ffbfb_mmap(dev_t dev, off_t off, int prot) 905 { 906 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 907 uint64_t size; 908 int i, reg; 909 off_t o; 910 911 /* 912 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 913 * which we map to an index into the "reg" property, and use 914 * our copy of the firmware data as arguments for the real 915 * mapping. 916 */ 917 static struct { unsigned long voff; int reg; } map[] = { 918 { 0x00000000, FFB_REG_SFB8R }, 919 { 0x00400000, FFB_REG_SFB8G }, 920 { 0x00800000, FFB_REG_SFB8B }, 921 { 0x00c00000, FFB_REG_SFB8X }, 922 { 0x01000000, FFB_REG_SFB32 }, 923 { 0x02000000, FFB_REG_SFB64 }, 924 { 0x04000000, FFB_REG_FBC }, 925 { 0x04004000, FFB_REG_DFB8R }, 926 { 0x04404000, FFB_REG_DFB8G }, 927 { 0x04804000, FFB_REG_DFB8B }, 928 { 0x04c04000, FFB_REG_DFB8X }, 929 { 0x05004000, FFB_REG_DFB24 }, 930 { 0x06004000, FFB_REG_DFB32 }, 931 { 0x07004000, FFB_REG_DFB422A }, 932 { 0x0bc06000, FFB_REG_DAC }, 933 { 0x0bc08000, FFB_REG_PROM }, 934 { 0x0bc18000, 0 } 935 }; 936 937 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 938 if (off == 0x0bc18000) 939 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 940 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 941 942 /* 943 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 944 * probably mmap them only on afb boards 945 */ 946 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 947 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 948 0x00610000 + (off - 0x0bc04000), prot, 949 BUS_SPACE_MAP_LINEAR); 950 951 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 952 953 /* the map is ordered by voff */ 954 for (i = 0; i < NELEMS(map)-1; i++) { 955 reg = map[i].reg; 956 /* the number of entries in reg seems to vary */ 957 if (reg < sc->sc_nreg) { 958 size = min((map[i + 1].voff - map[i].voff), 959 sc->sc_sizes[reg]); 960 if ((off >= map[i].voff) && 961 (off < (map[i].voff + size))) { 962 o = off - map[i].voff; 963 return bus_space_mmap(sc->sc_bt, 964 sc->sc_addrs[reg], o, prot, 965 BUS_SPACE_MAP_LINEAR); 966 } 967 } 968 } 969 970 return -1; 971 } 972 973 void 974 ffb_clearscreen(struct ffb_softc *sc) 975 { 976 struct rasops_info *ri = &ffb_console_screen.scr_ri; 977 ffb_ras_fill(sc); 978 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 979 ffb_ras_fifo_wait(sc, 4); 980 FBC_WRITE(sc, FFB_FBC_BY, 0); 981 FBC_WRITE(sc, FFB_FBC_BX, 0); 982 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 983 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 984 } 985 986 void 987 ffb_cursor(void *cookie, int on, int row, int col) 988 { 989 struct rasops_info *ri = cookie; 990 struct vcons_screen *scr; 991 struct ffb_softc *sc; 992 int x, y, wi, he; 993 994 if (cookie != NULL) { 995 scr = ri->ri_hw; 996 sc = scr->scr_cookie; 997 998 wi = ri->ri_font->fontwidth; 999 he = ri->ri_font->fontheight; 1000 1001 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1002 1003 if (ri->ri_flg & RI_CURSOR) { 1004 1005 /* remove cursor */ 1006 x = ri->ri_ccol * wi + ri->ri_xorigin; 1007 y = ri->ri_crow * he + ri->ri_yorigin; 1008 1009 ffb_ras_invert(sc); 1010 ffb_ras_fifo_wait(sc, 4); 1011 FBC_WRITE(sc, FFB_FBC_BY, y); 1012 FBC_WRITE(sc, FFB_FBC_BX, x); 1013 FBC_WRITE(sc, FFB_FBC_BH, he); 1014 FBC_WRITE(sc, FFB_FBC_BW, wi); 1015 1016 ri->ri_flg &= ~RI_CURSOR; 1017 } 1018 ri->ri_crow = row; 1019 ri->ri_ccol = col; 1020 if (on) 1021 { 1022 x = ri->ri_ccol * wi + ri->ri_xorigin; 1023 y = ri->ri_crow * he + ri->ri_yorigin; 1024 1025 ffb_ras_invert(sc); 1026 ffb_ras_fifo_wait(sc, 4); 1027 FBC_WRITE(sc, FFB_FBC_BY, y); 1028 FBC_WRITE(sc, FFB_FBC_BX, x); 1029 FBC_WRITE(sc, FFB_FBC_BH, he); 1030 FBC_WRITE(sc, FFB_FBC_BW, wi); 1031 1032 ri->ri_flg |= RI_CURSOR; 1033 } 1034 } else { 1035 ri->ri_crow = row; 1036 ri->ri_ccol = col; 1037 ri->ri_flg &= ~RI_CURSOR; 1038 } 1039 } 1040 } 1041 1042 /* mono bitmap font */ 1043 void 1044 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1045 { 1046 struct rasops_info *ri = cookie; 1047 struct vcons_screen *scr = ri->ri_hw; 1048 struct wsdisplay_font *font = PICK_FONT(ri, c); 1049 struct ffb_softc *sc = scr->scr_cookie; 1050 void *data; 1051 uint32_t fg, bg; 1052 int i; 1053 int x, y, wi, he; 1054 1055 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1056 return; 1057 1058 wi = font->fontwidth; 1059 he = font->fontheight; 1060 1061 if (!CHAR_IN_FONT(c, font)) 1062 return; 1063 1064 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1065 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1066 x = ri->ri_xorigin + col * wi; 1067 y = ri->ri_yorigin + row * he; 1068 1069 data = WSFONT_GLYPH(c, font); 1070 1071 ffb_ras_setbg(sc, bg); 1072 ffb_ras_setfg(sc, fg); 1073 ffb_ras_fifo_wait(sc, 4); 1074 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1075 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1076 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1077 FBC_WRITE(sc, FFB_FBC_PPC, 1078 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1079 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1080 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1081 1082 switch (font->stride) { 1083 case 1: { 1084 uint8_t *data8 = data; 1085 uint32_t reg; 1086 for (i = 0; i < he; i++) { 1087 reg = *data8; 1088 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1089 data8++; 1090 } 1091 break; 1092 } 1093 case 2: { 1094 uint16_t *data16 = data; 1095 uint32_t reg; 1096 for (i = 0; i < he; i++) { 1097 reg = *data16; 1098 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1099 data16++; 1100 } 1101 break; 1102 } 1103 } 1104 } 1105 1106 /* alpha font */ 1107 void 1108 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1109 { 1110 struct rasops_info *ri = cookie; 1111 struct vcons_screen *scr = ri->ri_hw; 1112 struct wsdisplay_font *font = PICK_FONT(ri, c); 1113 struct ffb_softc *sc = scr->scr_cookie; 1114 volatile uint32_t *dest, *ddest; 1115 uint8_t *data8; 1116 uint32_t fg, bg; 1117 int i; 1118 int x, y, wi, he; 1119 uint32_t alpha = 0x80; 1120 int j; 1121 1122 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1123 return; 1124 1125 wi = font->fontwidth; 1126 he = font->fontheight; 1127 1128 if (!CHAR_IN_FONT(c, font)) 1129 return; 1130 1131 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1132 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1133 x = ri->ri_xorigin + col * wi; 1134 y = ri->ri_yorigin + row * he; 1135 1136 data8 = WSFONT_GLYPH(c, font); 1137 1138 /* first we erase the background */ 1139 ffb_ras_fill(sc); 1140 ffb_ras_setfg(sc, bg); 1141 ffb_ras_fifo_wait(sc, 4); 1142 FBC_WRITE(sc, FFB_FBC_BY, y); 1143 FBC_WRITE(sc, FFB_FBC_BX, x); 1144 FBC_WRITE(sc, FFB_FBC_BH, he); 1145 FBC_WRITE(sc, FFB_FBC_BW, wi); 1146 1147 /* if we draw a space we're done */ 1148 if (c == ' ') return; 1149 1150 /* now enable alpha blending */ 1151 ffb_ras_setfg(sc, fg); 1152 ffb_ras_fifo_wait(sc, 2); 1153 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1154 1155 FBC_WRITE(sc, FFB_FBC_PPC, 1156 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1157 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1158 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1159 /* 1160 * we have to wait for both the rectangle drawing op above and the 1161 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1162 */ 1163 ffb_ras_wait(sc); 1164 1165 /* ... and draw the character */ 1166 dest = sc->sc_sfb32 + (y << 11) + x; 1167 for (i = 0; i < he; i++) { 1168 ddest = dest; 1169 for (j = 0; j < wi; j++) { 1170 alpha = *data8; 1171 /* 1172 * We set the colour source to constant above so we only 1173 * have to write the alpha channel here and the colour 1174 * comes from the FG register. It would be nice if we 1175 * could just use the SFB8X aperture and memcpy() the 1176 * alpha map line by line but for some strange reason 1177 * that will take colour info from the framebuffer even 1178 * if we set the FBC_PPC_CS_CONST bit above. 1179 */ 1180 *ddest = alpha << 24; 1181 data8++; 1182 ddest++; 1183 } 1184 dest += 2048; 1185 } 1186 } 1187 1188 int 1189 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1190 { 1191 if ((fg == 0) && (bg == 0)) 1192 { 1193 fg = WS_DEFAULT_FG; 1194 bg = WS_DEFAULT_BG; 1195 } 1196 if (flags & WSATTR_REVERSE) { 1197 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1198 (flags & 0xff); 1199 } else 1200 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1201 (flags & 0xff); 1202 return 0; 1203 } 1204 1205 void 1206 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1207 int existing, long *defattr) 1208 { 1209 struct ffb_softc *sc = cookie; 1210 struct rasops_info *ri = &scr->scr_ri; 1211 1212 ri->ri_depth = 32; 1213 ri->ri_width = sc->sc_width; 1214 ri->ri_height = sc->sc_height; 1215 ri->ri_stride = sc->sc_linebytes; 1216 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1217 1218 /* 1219 * we can't accelerate copycols() so instead of falling back to 1220 * software use vcons' putchar() based implementation 1221 */ 1222 scr->scr_flags |= VCONS_NO_COPYCOLS; 1223 #ifdef VCONS_DRAW_INTR 1224 scr->scr_flags |= VCONS_DONT_READ; 1225 #endif 1226 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1227 1228 /* explicitly request BGR in case the default changes */ 1229 ri->ri_rnum = 8; 1230 ri->ri_gnum = 8; 1231 ri->ri_bnum = 8; 1232 ri->ri_rpos = 0; 1233 ri->ri_gpos = 8; 1234 ri->ri_bpos = 16; 1235 1236 rasops_init(ri, 0, 0); 1237 ri->ri_caps = WSSCREEN_WSCOLORS; 1238 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1239 sc->sc_width / ri->ri_font->fontwidth); 1240 1241 /* enable acceleration */ 1242 ri->ri_ops.copyrows = ffb_ras_copyrows; 1243 ri->ri_ops.eraserows = ffb_ras_eraserows; 1244 ri->ri_ops.erasecols = ffb_ras_erasecols; 1245 ri->ri_ops.cursor = ffb_cursor; 1246 ri->ri_ops.allocattr = ffb_allocattr; 1247 if (FONT_IS_ALPHA(ri->ri_font)) { 1248 ri->ri_ops.putchar = ffb_putchar_aa; 1249 } else 1250 ri->ri_ops.putchar = ffb_putchar_mono; 1251 } 1252 1253 /* I2C bitbanging */ 1254 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1255 { 1256 struct ffb_softc *sc = cookie; 1257 1258 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1259 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1260 } 1261 1262 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1263 { 1264 /* Nothing to do */ 1265 } 1266 1267 static uint32_t ffb_i2cbb_read(void *cookie) 1268 { 1269 struct ffb_softc *sc = cookie; 1270 uint32_t bits; 1271 1272 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1273 bits = DAC_READ(sc, FFB_DAC_VALUE); 1274 1275 return bits; 1276 } 1277 1278 /* higher level I2C stuff */ 1279 static int 1280 ffb_i2c_acquire_bus(void *cookie, int flags) 1281 { 1282 /* private bus */ 1283 return (0); 1284 } 1285 1286 static void 1287 ffb_i2c_release_bus(void *cookie, int flags) 1288 { 1289 /* private bus */ 1290 } 1291 1292 static int 1293 ffb_i2c_send_start(void *cookie, int flags) 1294 { 1295 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1296 } 1297 1298 static int 1299 ffb_i2c_send_stop(void *cookie, int flags) 1300 { 1301 1302 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1303 } 1304 1305 static int 1306 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1307 { 1308 /* 1309 * for some reason i2c_bitbang_initiate_xfer left-shifts 1310 * the I2C-address and then sets the direction bit 1311 */ 1312 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1313 &ffb_i2cbb_ops)); 1314 } 1315 1316 static int 1317 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1318 { 1319 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1320 } 1321 1322 static int 1323 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1324 { 1325 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1326 } 1327 1328 1329 #define TVC_READ_LIMIT 100000 1330 int 1331 ffb_tgc_disable(struct ffb_softc *sc) 1332 { 1333 int i; 1334 1335 /* Is the timing generator disabled? */ 1336 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1337 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1338 return 1; 1339 1340 /* If not, disable it when the vertical counter reaches 0 */ 1341 for (i = 0; i < TVC_READ_LIMIT; i++) { 1342 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1343 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1344 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1345 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1346 return 1; 1347 } 1348 } 1349 return 0; 1350 } 1351 1352 /* 1353 * PLL Control Register values: 1354 * M)ultiplier = bits 0:6 + 1 1355 * D)ivisor = bits 7:10 + 1 1356 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1357 * Frequency = 13.5 * M / D / P 1358 */ 1359 #define FFB_PLL_FREQ 13500000 1360 void 1361 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1362 { 1363 int m, d, p, f, hex = 0, curdiff; 1364 1365 *diff = 100000000; 1366 1367 for (m = 32; m <= 80; m++) { 1368 for (d = 4; d <= 11; d++) { 1369 for (p = 1; p <= 8; p = p << 1) { 1370 switch (p) { 1371 case 1: 1372 hex = 0x4000 + (d << 7) + m; 1373 break; 1374 case 2: 1375 hex = 0x4800 + (d << 7) + m; 1376 break; 1377 case 4: 1378 hex = 0x5000 + (d << 7) + m; 1379 break; 1380 case 8: 1381 hex = 0x6000 + (d << 7) + m; 1382 break; 1383 } 1384 f = 13500000 * m / d / p; 1385 if (f == request) { 1386 *diff = 0; 1387 *pll = hex; 1388 return; 1389 } else { 1390 curdiff = abs(request - f); 1391 if (curdiff < *diff) { 1392 *diff = curdiff; 1393 *pll = hex; 1394 } 1395 } 1396 } 1397 } 1398 } 1399 } 1400 1401 /* 1402 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1403 * and in the Connexant BT497A/498A documentation. 1404 * 1405 * VESA timings to FFB register conversion: 1406 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1407 * VBE = VBS - vres = (sync pulse - 1) + back porch 1408 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1409 * VSE = sync pulse - 1 1410 * VSS = (sync pulse - 1) + back porch + vres + front porch 1411 * HRE = HSS - HSE - 1 1412 * HBE = (sync pulse + back porch) / x - 1 1413 * HBS = (sync pulse + back porch + hres) / x - 1 1414 * HSE = sync pulse / x - 1 1415 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1416 * HCE = HBS - 4 1417 * HCS = HBE - 4 1418 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1419 * 1420 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1421 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1422 * 1423 * Note, that the timing generator should be disabled and re-enabled when the 1424 * the timing parameter registers are being programmed. Stopping the timing 1425 * generator should only be done when the vertical counter is zero. 1426 */ 1427 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1428 int 1429 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1430 int *hres, int *vres) 1431 { 1432 int diff; 1433 uint32_t fp, sp, bp, x; 1434 uint32_t pll, pfc, ucl, dcl, tgc; 1435 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1436 uint32_t epe, eie, eis; 1437 uint32_t fbcfg0; 1438 1439 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1440 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1441 mode->htotal), mode->vtotal))); 1442 DPRINTF((" (%d %d %d %d %d %d %d", 1443 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1444 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1445 DPRINTF((" %s%sH %s%sV)\n", 1446 mode->flags & VID_PHSYNC ? "+" : "", 1447 mode->flags & VID_NHSYNC ? "-" : "", 1448 mode->flags & VID_PVSYNC ? "+" : "", 1449 mode->flags & VID_NVSYNC ? "-" : "")); 1450 1451 /* We don't handle interlaced or doublescan (yet) */ 1452 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1453 return 0; 1454 1455 /* Only Creator3D can be set to > 1280x1024 */ 1456 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1457 sc->sc_type == FFB_AFB) 1458 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1459 return 0; 1460 /* Creator3D can be set to <= 1920x1360 */ 1461 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1462 return 0; 1463 1464 /* 1465 * Look for a matching pixel clock and set PLL Control. 1466 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1467 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1468 * does not work. So, use the PROM value instead. 1469 */ 1470 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1471 mode->dot_clock == 25175) { 1472 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1473 mode->dot_clock = 25125; 1474 } 1475 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1476 if (diff > 250000) 1477 return 0; 1478 1479 /* Pixel Format Control, User Control and FBC Configuration. */ 1480 if (mode->hdisplay > 1280) { 1481 pfc = FFB_DAC_PIX_FMT_821; 1482 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1483 x = 4; 1484 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1485 } else { 1486 pfc = FFB_DAC_PIX_FMT_421; 1487 /* Only Creator3D and Elite3D can have double-buffer */ 1488 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1489 ucl = 0; 1490 else 1491 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1492 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1493 x = 2; 1494 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1495 } 1496 1497 /* DAC Control and Timing Generator Control */ 1498 if (mode->flags & VID_PVSYNC) 1499 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1500 else 1501 dcl = 0; 1502 tgc = 0; 1503 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1504 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1505 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1506 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1507 } else { 1508 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1509 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1510 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1511 else 1512 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1513 } 1514 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1515 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1516 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1517 FFB_DAC_TGC_MASTER_ENABLE); 1518 1519 /* Vertical timing */ 1520 fp = mode->vsync_start - mode->vdisplay; 1521 sp = mode->vsync_end - mode->vsync_start; 1522 bp = mode->vtotal - mode->vsync_end; 1523 1524 vbe = sp - 1 + bp; 1525 vbs = sp - 1 + bp + mode->vdisplay; 1526 vse = sp - 1; 1527 vss = sp - 1 + bp + mode->vdisplay + fp; 1528 1529 /* Horizontal timing */ 1530 fp = mode->hsync_start - mode->hdisplay; 1531 sp = mode->hsync_end - mode->hsync_start; 1532 bp = mode->htotal - mode->hsync_end; 1533 1534 hbe = (sp + bp) / x - 1; 1535 hbs = (sp + bp + mode->hdisplay) / x - 1; 1536 hse = sp / x - 1; 1537 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1538 hre = hss - hse - 1; 1539 hce = hbs - 4; 1540 hcs = hbe - 4; 1541 1542 /* Equalisation (interlaced modes) */ 1543 epe = 0; 1544 eie = 0; 1545 eis = 0; 1546 1547 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1548 pll, pfc, ucl, dcl, tgc)); 1549 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1550 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1551 hre, hbe, hbs, hse, hss, hce, hcs)); 1552 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1553 1554 if (!ffb_tgc_disable(sc)) { 1555 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1556 return 0; 1557 } 1558 1559 /* 1560 * Program the mode registers. 1561 * Program the timing generator last, as that re-enables output. 1562 * Note, that a read to/write from a register increments the 1563 * register address to the next register automatically. 1564 */ 1565 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1566 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1567 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1568 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1569 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1570 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1571 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1572 1573 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1575 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1576 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1577 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1578 1579 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1580 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1581 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1582 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1583 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1584 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1585 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1586 1587 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1588 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1589 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1590 1591 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1592 1593 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1594 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1595 DPRINTF(("new tgc: %08x\n", tgc)); 1596 1597 *hres = mode->hdisplay; 1598 *vres = mode->vdisplay; 1599 1600 printf("%s: video mode set to %d x %d @ %dHz\n", 1601 device_xname(sc->sc_dev), 1602 mode->hdisplay, mode->vdisplay, 1603 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1604 mode->htotal), mode->vtotal)); 1605 1606 return 1; 1607 } 1608