1 /* $NetBSD: ffb.c,v 1.48 2011/10/31 08:28:46 jdc Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.48 2011/10/31 08:28:46 jdc Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 131 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 132 133 void ffb_clearscreen(struct ffb_softc *); 134 int ffb_load_font(void *, void *, struct wsdisplay_font *); 135 void ffb_init_screen(void *, struct vcons_screen *, int, 136 long *); 137 int ffb_allocattr(void *, int, int, int, long *); 138 void ffb_putchar(void *, int, int, u_int, long); 139 void ffb_cursor(void *, int, int, int); 140 141 /* frame buffer generic driver */ 142 static void ffbfb_unblank(device_t); 143 dev_type_open(ffbfb_open); 144 dev_type_close(ffbfb_close); 145 dev_type_ioctl(ffbfb_ioctl); 146 dev_type_mmap(ffbfb_mmap); 147 148 static struct fbdriver ffb_fbdriver = { 149 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 150 ffbfb_mmap, nokqfilter 151 }; 152 153 struct wsdisplay_accessops ffb_accessops = { 154 .ioctl = ffb_ioctl, 155 .mmap = ffb_mmap, 156 }; 157 158 /* I2C glue */ 159 static int ffb_i2c_acquire_bus(void *, int); 160 static void ffb_i2c_release_bus(void *, int); 161 static int ffb_i2c_send_start(void *, int); 162 static int ffb_i2c_send_stop(void *, int); 163 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 164 static int ffb_i2c_read_byte(void *, uint8_t *, int); 165 static int ffb_i2c_write_byte(void *, uint8_t, int); 166 167 /* I2C bitbang glue */ 168 static void ffb_i2cbb_set_bits(void *, uint32_t); 169 static void ffb_i2cbb_set_dir(void *, uint32_t); 170 static uint32_t ffb_i2cbb_read(void *); 171 172 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 173 ffb_i2cbb_set_bits, 174 ffb_i2cbb_set_dir, 175 ffb_i2cbb_read, 176 { 177 FFB_DAC_CFG_MPDATA_SDA, 178 FFB_DAC_CFG_MPDATA_SCL, 179 0, 180 0 181 } 182 }; 183 184 void ffb_attach_i2c(struct ffb_softc *); 185 186 /* Video mode setting */ 187 int ffb_tgc_disable(struct ffb_softc *); 188 void ffb_get_pclk(int, uint32_t *, int *); 189 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 190 191 192 void 193 ffb_attach(device_t self) 194 { 195 struct ffb_softc *sc = device_private(self); 196 struct wsemuldisplaydev_attach_args waa; 197 struct rasops_info *ri; 198 long defattr; 199 const char *model, *out_dev; 200 int btype; 201 uint32_t dac; 202 int maxrow, maxcol; 203 u_int blank = WSDISPLAYIO_VIDEO_ON; 204 char buf[6+1]; 205 int i, try_edid; 206 prop_data_t data; 207 208 printf(":"); 209 210 if (sc->sc_type == FFB_CREATOR) { 211 btype = prom_getpropint(sc->sc_node, "board_type", 0); 212 if ((btype & 7) == 3) 213 printf(" Creator3D"); 214 else 215 printf(" Creator"); 216 } else { 217 printf(" Elite3D"); 218 btype = 0; 219 } 220 221 model = prom_getpropstring(sc->sc_node, "model"); 222 if (model == NULL || strlen(model) == 0) 223 model = "unknown"; 224 225 sc->sc_depth = 24; 226 sc->sc_linebytes = 8192; 227 /* We might alter these during EDID mode setting */ 228 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 229 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 230 231 sc->sc_locked = 0; 232 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 233 234 maxcol = (prom_getoption("screen-#columns", buf, sizeof buf) == 0) 235 ? strtoul(buf, NULL, 10) 236 : 80; 237 238 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 239 ? strtoul(buf, NULL, 10) 240 : 34; 241 242 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 243 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 244 dac = DAC_READ(sc, FFB_DAC_VALUE); 245 sc->sc_dacrev = (dac >> 28) & 0xf; 246 247 if (sc->sc_type == FFB_AFB) { 248 sc->sc_dacrev = 10; 249 sc->sc_needredraw = 0; 250 } else { 251 /* see what kind of DAC we have */ 252 int pnum = (dac & 0x0ffff000) >> 12; 253 if (pnum == 0x236e) { 254 sc->sc_needredraw = 0; 255 } else { 256 sc->sc_needredraw = 1; 257 } 258 } 259 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 260 if (sc->sc_needredraw) 261 printf("%s: found old DAC, enabling redraw on unblank\n", 262 device_xname(sc->sc_dev)); 263 264 /* Check if a console resolution "<device>:r<res>" is set. */ 265 if (sc->sc_console) { 266 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 267 if (out_dev != NULL && strlen(out_dev) != 0 && 268 strstr(out_dev, ":r") != NULL) 269 try_edid = 0; 270 else 271 try_edid = 1; 272 } else 273 try_edid = 1; 274 275 #if FFB_DEBUG > 0 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 277 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 279 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 280 #endif 281 ffb_attach_i2c(sc); 282 283 /* Need to set asynchronous blank during DDC write/read */ 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 dac = DAC_READ(sc, FFB_DAC_VALUE); 286 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 287 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 288 289 /* Some monitors don't respond first time */ 290 i = 0; 291 while (sc->sc_edid_data[1] == 0 && i++ < 3) 292 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 293 294 /* Remove asynchronous blank */ 295 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 296 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 297 298 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 299 sort_modes(sc->sc_edid_info.edid_modes, 300 &sc->sc_edid_info.edid_preferred_mode, 301 sc->sc_edid_info.edid_nmodes); 302 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 303 for (i = 0; i < EDID_DATA_LEN; i++) { 304 if (i && !(i % 32)) 305 DPRINTF(("\n ")); 306 if (i && !(i % 4)) 307 DPRINTF((" ")); 308 DPRINTF(("%02x", sc->sc_edid_data[i])); 309 } 310 DPRINTF(("\n")); 311 if (ffb_debug) 312 edid_print(&sc->sc_edid_info); 313 314 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 315 prop_dictionary_set(device_properties(self), "EDID", data); 316 prop_object_release(data); 317 318 if (try_edid) 319 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 320 if (ffb_set_vmode(sc, 321 &(sc->sc_edid_info.edid_modes[i]), btype, 322 &(sc->sc_width), &(sc->sc_height))) 323 break; 324 } 325 } else { 326 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 327 } 328 329 ffb_ras_init(sc); 330 331 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 332 333 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 334 FFB_CFFLAG_NOACCEL) == 0); 335 336 wsfont_init(); 337 338 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 339 sc->vd.init_screen = ffb_init_screen; 340 341 /* we mess with ffb_console_screen only once */ 342 if (sc->sc_console) { 343 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 344 SCREEN_VISIBLE((&ffb_console_screen)); 345 /* 346 * XXX we shouldn't use a global variable for the console 347 * screen 348 */ 349 sc->vd.active = &ffb_console_screen; 350 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 351 } else { 352 if (ffb_console_screen.scr_ri.ri_rows == 0) { 353 /* do some minimal setup to avoid weirdnesses later */ 354 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 355 } 356 } 357 ri = &ffb_console_screen.scr_ri; 358 359 ffb_stdscreen.nrows = ri->ri_rows; 360 ffb_stdscreen.ncols = ri->ri_cols; 361 ffb_stdscreen.textops = &ri->ri_ops; 362 ffb_stdscreen.capabilities = ri->ri_caps; 363 364 sc->sc_fb.fb_driver = &ffb_fbdriver; 365 sc->sc_fb.fb_type.fb_cmsize = 0; 366 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 367 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 368 sc->sc_fb.fb_type.fb_width = sc->sc_width; 369 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 370 sc->sc_fb.fb_type.fb_height = sc->sc_height; 371 sc->sc_fb.fb_device = sc->sc_dev; 372 fb_attach(&sc->sc_fb, sc->sc_console); 373 374 ffb_clearscreen(sc); 375 376 if (sc->sc_console) { 377 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 378 vcons_replay_msgbuf(&ffb_console_screen); 379 } 380 381 waa.console = sc->sc_console; 382 waa.scrdata = &ffb_screenlist; 383 waa.accessops = &ffb_accessops; 384 waa.accesscookie = &sc->vd; 385 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 386 } 387 388 void 389 ffb_attach_i2c(struct ffb_softc *sc) 390 { 391 392 /* Fill in the i2c tag */ 393 sc->sc_i2c.ic_cookie = sc; 394 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 395 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 396 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 397 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 398 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 399 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 400 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 401 sc->sc_i2c.ic_exec = NULL; 402 } 403 404 int 405 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 406 { 407 struct vcons_data *vd = v; 408 struct ffb_softc *sc = vd->cookie; 409 struct wsdisplay_fbinfo *wdf; 410 struct vcons_screen *ms = vd->active; 411 412 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 413 device_xname(sc->sc_dev), 414 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 415 (char)IOCGROUP(cmd), cmd & 0xff)); 416 417 switch (cmd) { 418 case FBIOGTYPE: 419 *(struct fbtype *)data = sc->sc_fb.fb_type; 420 break; 421 case FBIOGATTR: 422 #define fba ((struct fbgattr *)data) 423 fba->real_type = sc->sc_fb.fb_type.fb_type; 424 fba->owner = 0; /* XXX ??? */ 425 fba->fbtype = sc->sc_fb.fb_type; 426 fba->sattr.flags = 0; 427 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 428 fba->sattr.dev_specific[0] = -1; 429 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 430 fba->emu_types[1] = -1; 431 #undef fba 432 break; 433 434 case FBIOGETCMAP: 435 case FBIOPUTCMAP: 436 return EIO; 437 438 case FBIOGVIDEO: 439 case FBIOSVIDEO: 440 return ffb_blank(sc, cmd == FBIOGVIDEO? 441 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 442 (u_int *)data); 443 break; 444 case FBIOGCURSOR: 445 case FBIOSCURSOR: 446 /* the console driver is not using the hardware cursor */ 447 break; 448 case FBIOGCURPOS: 449 printf("%s: FBIOGCURPOS not implemented\n", 450 device_xname(sc->sc_dev)); 451 return EIO; 452 case FBIOSCURPOS: 453 printf("%s: FBIOSCURPOS not implemented\n", 454 device_xname(sc->sc_dev)); 455 return EIO; 456 case FBIOGCURMAX: 457 printf("%s: FBIOGCURMAX not implemented\n", 458 device_xname(sc->sc_dev)); 459 return EIO; 460 461 case WSDISPLAYIO_GTYPE: 462 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 463 break; 464 case WSDISPLAYIO_SMODE: 465 { 466 if (sc->sc_mode != *(u_int *)data) { 467 sc->sc_mode = *(u_int *)data; 468 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 469 (sc->sc_locked == 0)) { 470 ffb_ras_init(sc); 471 vcons_redraw_screen(ms); 472 } 473 } 474 } 475 break; 476 case WSDISPLAYIO_GINFO: 477 wdf = (void *)data; 478 wdf->height = sc->sc_height; 479 wdf->width = sc->sc_width; 480 wdf->depth = 32; 481 wdf->cmsize = 256; /* XXX */ 482 break; 483 #ifdef WSDISPLAYIO_LINEBYTES 484 case WSDISPLAYIO_LINEBYTES: 485 *(u_int *)data = sc->sc_linebytes; 486 break; 487 #endif 488 case WSDISPLAYIO_GETCMAP: 489 break;/* XXX */ 490 491 case WSDISPLAYIO_PUTCMAP: 492 break;/* XXX */ 493 494 case WSDISPLAYIO_SVIDEO: 495 case WSDISPLAYIO_GVIDEO: 496 return(ffb_blank(sc, cmd, (u_int *)data)); 497 break; 498 case WSDISPLAYIO_GCURPOS: 499 case WSDISPLAYIO_SCURPOS: 500 case WSDISPLAYIO_GCURMAX: 501 case WSDISPLAYIO_GCURSOR: 502 case WSDISPLAYIO_SCURSOR: 503 return EIO; /* not supported yet */ 504 break; 505 case WSDISPLAYIO_GET_EDID: { 506 struct wsdisplayio_edid_info *d = data; 507 return wsdisplayio_get_edid(sc->sc_dev, d); 508 } 509 default: 510 return EPASSTHROUGH; 511 } 512 513 return (0); 514 } 515 516 /* blank/unblank the screen */ 517 static int 518 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 519 { 520 struct vcons_screen *ms = sc->vd.active; 521 u_int val; 522 523 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 524 val = DAC_READ(sc, FFB_DAC_VALUE); 525 526 switch (cmd) { 527 case WSDISPLAYIO_GVIDEO: 528 *data = val & 1; 529 return(0); 530 break; 531 case WSDISPLAYIO_SVIDEO: 532 if (*data == WSDISPLAYIO_VIDEO_OFF) 533 val &= ~1; 534 else if (*data == WSDISPLAYIO_VIDEO_ON) 535 val |= 1; 536 else 537 return(EINVAL); 538 break; 539 default: 540 return(EINVAL); 541 } 542 543 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 544 DAC_WRITE(sc, FFB_DAC_VALUE, val); 545 546 if ((val & 1) && sc->sc_needredraw) { 547 if (ms != NULL) { 548 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 549 (sc->sc_locked == 0)) { 550 ffb_ras_init(sc); 551 vcons_redraw_screen(ms); 552 } 553 } 554 } 555 556 return(0); 557 } 558 559 paddr_t 560 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 561 { 562 struct vcons_data *vd = vsc; 563 struct ffb_softc *sc = vd->cookie; 564 int i; 565 566 switch (sc->sc_mode) { 567 case WSDISPLAYIO_MODE_MAPPED: 568 for (i = 0; i < sc->sc_nreg; i++) { 569 /* Before this set? */ 570 if (off < sc->sc_addrs[i]) 571 continue; 572 /* After this set? */ 573 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 574 continue; 575 576 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 577 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 578 } 579 break; 580 #ifdef WSDISPLAYIO_MODE_DUMBFB 581 case WSDISPLAYIO_MODE_DUMBFB: 582 if (sc->sc_nreg < FFB_REG_DFB24) 583 break; 584 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 585 return (bus_space_mmap(sc->sc_bt, 586 sc->sc_addrs[FFB_REG_DFB24], off, prot, 587 BUS_SPACE_MAP_LINEAR)); 588 break; 589 #endif 590 } 591 return (-1); 592 } 593 594 void 595 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 596 { 597 int32_t cache = sc->sc_fifo_cache; 598 599 if (cache < n) { 600 do { 601 cache = FBC_READ(sc, FFB_FBC_UCSR); 602 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 603 } while (cache < n); 604 } 605 sc->sc_fifo_cache = cache - n; 606 } 607 608 void 609 ffb_ras_wait(struct ffb_softc *sc) 610 { 611 uint32_t ucsr, r; 612 613 while (1) { 614 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 615 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 616 break; 617 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 618 if (r != 0) 619 FBC_WRITE(sc, FFB_FBC_UCSR, r); 620 } 621 } 622 623 void 624 ffb_ras_init(struct ffb_softc *sc) 625 { 626 uint32_t fbc; 627 628 if (sc->sc_width > 1280) { 629 DPRINTF(("ffb_ras_init: high resolution.\n")); 630 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 631 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 632 } else { 633 DPRINTF(("ffb_ras_init: standard resolution.\n")); 634 fbc = FFB_FBC_XE_OFF; 635 } 636 ffb_ras_fifo_wait(sc, 8); 637 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 638 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 639 FBC_WRITE(sc, FFB_FBC_PPC, 640 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 641 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 642 FBC_PPC_XS_WID); 643 644 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 645 FFB_FBC_RGBE_MASK; 646 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 647 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 648 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 649 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 650 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 651 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 652 sc->sc_fg_cache = 0; 653 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 654 ffb_ras_wait(sc); 655 } 656 657 void 658 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 659 { 660 struct rasops_info *ri = cookie; 661 struct vcons_screen *scr = ri->ri_hw; 662 struct ffb_softc *sc = scr->scr_cookie; 663 664 if (row < 0) { 665 n += row; 666 row = 0; 667 } 668 if (row + n > ri->ri_rows) 669 n = ri->ri_rows - row; 670 if (n <= 0) 671 return; 672 673 ffb_ras_fill(sc); 674 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 675 ffb_ras_fifo_wait(sc, 4); 676 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 677 FBC_WRITE(sc, FFB_FBC_BY, 0); 678 FBC_WRITE(sc, FFB_FBC_BX, 0); 679 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 680 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 681 } else { 682 row *= ri->ri_font->fontheight; 683 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 684 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 685 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 686 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 687 } 688 SYNC; 689 } 690 691 void 692 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 693 { 694 struct rasops_info *ri = cookie; 695 struct vcons_screen *scr = ri->ri_hw; 696 struct ffb_softc *sc = scr->scr_cookie; 697 698 if ((row < 0) || (row >= ri->ri_rows)) 699 return; 700 if (col < 0) { 701 n += col; 702 col = 0; 703 } 704 if (col + n > ri->ri_cols) 705 n = ri->ri_cols - col; 706 if (n <= 0) 707 return; 708 n *= ri->ri_font->fontwidth; 709 col *= ri->ri_font->fontwidth; 710 row *= ri->ri_font->fontheight; 711 712 ffb_ras_fill(sc); 713 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 714 ffb_ras_fifo_wait(sc, 4); 715 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 716 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 717 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 718 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 719 SYNC; 720 } 721 722 void 723 ffb_ras_fill(struct ffb_softc *sc) 724 { 725 ffb_ras_fifo_wait(sc, 2); 726 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 727 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 728 SYNC; 729 } 730 731 void 732 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 733 { 734 struct rasops_info *ri = cookie; 735 struct vcons_screen *scr = ri->ri_hw; 736 struct ffb_softc *sc = scr->scr_cookie; 737 738 if (dst == src) 739 return; 740 if (src < 0) { 741 n += src; 742 src = 0; 743 } 744 if ((src + n) > ri->ri_rows) 745 n = ri->ri_rows - src; 746 if (dst < 0) { 747 n += dst; 748 dst = 0; 749 } 750 if ((dst + n) > ri->ri_rows) 751 n = ri->ri_rows - dst; 752 if (n <= 0) 753 return; 754 n *= ri->ri_font->fontheight; 755 src *= ri->ri_font->fontheight; 756 dst *= ri->ri_font->fontheight; 757 758 ffb_ras_fifo_wait(sc, 8); 759 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 760 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 761 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 762 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 763 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 764 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 765 FBC_WRITE(sc, FFB_FBC_BH, n); 766 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 767 SYNC; 768 } 769 770 static void 771 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 772 { 773 ffb_ras_fifo_wait(sc, 1); 774 if (fg == sc->sc_fg_cache) 775 return; 776 sc->sc_fg_cache = fg; 777 FBC_WRITE(sc, FFB_FBC_FG, fg); 778 SYNC; 779 } 780 781 static void 782 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 783 { 784 ffb_ras_fifo_wait(sc, 1); 785 if (bg == sc->sc_bg_cache) 786 return; 787 sc->sc_bg_cache = bg; 788 FBC_WRITE(sc, FFB_FBC_BG, bg); 789 SYNC; 790 } 791 792 /* frame buffer generic driver support functions */ 793 static void 794 ffbfb_unblank(device_t dev) 795 { 796 struct ffb_softc *sc = device_private(dev); 797 struct vcons_screen *ms = sc->vd.active; 798 u_int on = 1; 799 int redraw = 0; 800 801 ffb_ras_init(sc); 802 if (sc->sc_locked) { 803 sc->sc_locked = 0; 804 redraw = 1; 805 } 806 807 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 808 #if 0 809 if ((sc->vd.active != &ffb_console_screen) && 810 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 811 /* 812 * force-switch to the console screen. 813 * Caveat: the higher layer will think we're still on the 814 * other screen 815 */ 816 817 SCREEN_INVISIBLE(sc->vd.active); 818 sc->vd.active = &ffb_console_screen; 819 SCREEN_VISIBLE(sc->vd.active); 820 ms = sc->vd.active; 821 redraw = 1; 822 } 823 #endif 824 if (redraw) { 825 vcons_redraw_screen(ms); 826 } 827 } 828 829 int 830 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 831 { 832 struct ffb_softc *sc; 833 834 sc = device_lookup_private(&ffb_cd, minor(dev)); 835 if (sc == NULL) 836 return ENXIO; 837 838 sc->sc_locked = 1; 839 return 0; 840 } 841 842 int 843 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 844 { 845 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 846 struct vcons_screen *ms = sc->vd.active; 847 848 sc->sc_locked = 0; 849 if (ms != NULL) { 850 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 851 (sc->sc_locked == 0)) { 852 ffb_ras_init(sc); 853 vcons_redraw_screen(ms); 854 } 855 } 856 return 0; 857 } 858 859 int 860 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 861 { 862 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 863 864 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 865 } 866 867 paddr_t 868 ffbfb_mmap(dev_t dev, off_t off, int prot) 869 { 870 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 871 uint64_t size; 872 int i, reg; 873 off_t o; 874 875 /* 876 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 877 * which we map to an index into the "reg" property, and use 878 * our copy of the firmware data as arguments for the real 879 * mapping. 880 */ 881 static struct { unsigned long voff; int reg; } map[] = { 882 { 0x00000000, FFB_REG_SFB8R }, 883 { 0x00400000, FFB_REG_SFB8G }, 884 { 0x00800000, FFB_REG_SFB8B }, 885 { 0x00c00000, FFB_REG_SFB8X }, 886 { 0x01000000, FFB_REG_SFB32 }, 887 { 0x02000000, FFB_REG_SFB64 }, 888 { 0x04000000, FFB_REG_FBC }, 889 { 0x04004000, FFB_REG_DFB8R }, 890 { 0x04404000, FFB_REG_DFB8G }, 891 { 0x04804000, FFB_REG_DFB8B }, 892 { 0x04c04000, FFB_REG_DFB8X }, 893 { 0x05004000, FFB_REG_DFB24 }, 894 { 0x06004000, FFB_REG_DFB32 }, 895 { 0x07004000, FFB_REG_DFB422A }, 896 { 0x0bc06000, FFB_REG_DAC }, 897 { 0x0bc08000, FFB_REG_PROM }, 898 { 0x0bc18000, 0 } 899 }; 900 901 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 902 if (off == 0x0bc18000) 903 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 904 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 905 906 /* 907 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 908 * probably mmap them only on afb boards 909 */ 910 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 911 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 912 0x00610000 + (off - 0x0bc04000), prot, 913 BUS_SPACE_MAP_LINEAR); 914 915 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 916 917 /* the map is ordered by voff */ 918 for (i = 0; i < NELEMS(map)-1; i++) { 919 reg = map[i].reg; 920 /* the number of entries in reg seems to vary */ 921 if (reg < sc->sc_nreg) { 922 size = min((map[i + 1].voff - map[i].voff), 923 sc->sc_sizes[reg]); 924 if ((off >= map[i].voff) && 925 (off < (map[i].voff + size))) { 926 o = off - map[i].voff; 927 return bus_space_mmap(sc->sc_bt, 928 sc->sc_addrs[reg], o, prot, 929 BUS_SPACE_MAP_LINEAR); 930 } 931 } 932 } 933 934 return -1; 935 } 936 937 void 938 ffb_clearscreen(struct ffb_softc *sc) 939 { 940 struct rasops_info *ri = &ffb_console_screen.scr_ri; 941 ffb_ras_fill(sc); 942 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 943 ffb_ras_fifo_wait(sc, 4); 944 FBC_WRITE(sc, FFB_FBC_BY, 0); 945 FBC_WRITE(sc, FFB_FBC_BX, 0); 946 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 947 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 948 } 949 950 void 951 ffb_cursor(void *cookie, int on, int row, int col) 952 { 953 struct rasops_info *ri = cookie; 954 struct vcons_screen *scr; 955 struct ffb_softc *sc; 956 int x, y, wi, he, coffset; 957 958 if (cookie != NULL) { 959 scr = ri->ri_hw; 960 sc = scr->scr_cookie; 961 962 wi = ri->ri_font->fontwidth; 963 he = ri->ri_font->fontheight; 964 965 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 966 x = ri->ri_ccol * wi + ri->ri_xorigin; 967 y = ri->ri_crow * he + ri->ri_yorigin; 968 969 if (ri->ri_flg & RI_CURSOR) { 970 /* remove cursor */ 971 coffset = ri->ri_ccol + (ri->ri_crow * 972 ri->ri_cols); 973 #ifdef WSDISPLAY_SCROLLSUPPORT 974 coffset += scr->scr_offset_to_zero; 975 #endif 976 ffb_ras_wait(sc); 977 ffb_putchar(cookie, ri->ri_crow, 978 ri->ri_ccol, scr->scr_chars[coffset], 979 scr->scr_attrs[coffset]); 980 ri->ri_flg &= ~RI_CURSOR; 981 } 982 ri->ri_crow = row; 983 ri->ri_ccol = col; 984 if (on) 985 { 986 long attr, revattr; 987 x = ri->ri_ccol * wi + ri->ri_xorigin; 988 y = ri->ri_crow * he + ri->ri_yorigin; 989 coffset = col + (row * ri->ri_cols); 990 #ifdef WSDISPLAY_SCROLLSUPPORT 991 coffset += scr->scr_offset_to_zero; 992 #endif 993 attr = scr->scr_attrs[coffset]; 994 #ifdef FFB_CURSOR_SWAP_COLOURS 995 revattr=((attr >> 8 ) & 0x000f0000) | ((attr & 996 0x000f0000)<<8) | (attr & 0x0000ffff); 997 #else 998 revattr = attr ^ 0xffff0000; 999 #endif 1000 ffb_ras_wait(sc); 1001 ffb_putchar(cookie, ri->ri_crow, ri->ri_ccol, 1002 scr->scr_chars[coffset], revattr); 1003 ri->ri_flg |= RI_CURSOR; 1004 } 1005 } else { 1006 ri->ri_crow = row; 1007 ri->ri_ccol = col; 1008 ri->ri_flg &= ~RI_CURSOR; 1009 } 1010 } 1011 } 1012 1013 void 1014 ffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1015 { 1016 struct rasops_info *ri = cookie; 1017 struct vcons_screen *scr = ri->ri_hw; 1018 struct wsdisplay_font *font = PICK_FONT(ri, c); 1019 struct ffb_softc *sc = scr->scr_cookie; 1020 1021 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1022 void *data; 1023 uint32_t fg, bg; 1024 int uc, i; 1025 int x, y, wi, he; 1026 1027 wi = font->fontwidth; 1028 he = font->fontheight; 1029 1030 if (!CHAR_IN_FONT(c, font)) 1031 return; 1032 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1033 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1034 x = ri->ri_xorigin + col * wi; 1035 y = ri->ri_yorigin + row * he; 1036 1037 uc = c - font->firstchar; 1038 data = (uint8_t *)font->data + uc * ri->ri_fontscale; 1039 1040 ffb_ras_setbg(sc, bg); 1041 ffb_ras_setfg(sc, fg); 1042 ffb_ras_fifo_wait(sc, 3); 1043 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1044 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1045 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1046 1047 switch (ri->ri_font->stride) { 1048 case 1: { 1049 uint8_t *data8 = data; 1050 uint32_t reg; 1051 for (i = 0; i < he; i++) { 1052 reg = *data8; 1053 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1054 data8++; 1055 } 1056 break; 1057 } 1058 case 2: { 1059 uint16_t *data16 = data; 1060 uint32_t reg; 1061 for (i = 0; i < he; i++) { 1062 reg = *data16; 1063 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1064 data16++; 1065 } 1066 break; 1067 } 1068 } 1069 } 1070 } 1071 1072 int 1073 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1074 { 1075 if ((fg == 0) && (bg == 0)) 1076 { 1077 fg = WS_DEFAULT_FG; 1078 bg = WS_DEFAULT_BG; 1079 } 1080 if (flags & WSATTR_REVERSE) { 1081 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1082 (flags & 0xff); 1083 } else 1084 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1085 (flags & 0xff); 1086 return 0; 1087 } 1088 1089 void 1090 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1091 int existing, long *defattr) 1092 { 1093 struct ffb_softc *sc = cookie; 1094 struct rasops_info *ri = &scr->scr_ri; 1095 1096 ri->ri_depth = 32; 1097 ri->ri_width = sc->sc_width; 1098 ri->ri_height = sc->sc_height; 1099 ri->ri_stride = sc->sc_linebytes; 1100 ri->ri_flg = RI_CENTER; 1101 1102 /* 1103 * we can't accelerate copycols() so instead of falling back to 1104 * software use vcons' putchar() based implementation 1105 */ 1106 scr->scr_flags |= VCONS_NO_COPYCOLS; 1107 #ifdef VCONS_DRAW_INTR 1108 scr->scr_flags |= VCONS_DONT_READ; 1109 #endif 1110 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1111 1112 rasops_init(ri, sc->sc_height/8, sc->sc_width/8); 1113 ri->ri_caps = WSSCREEN_WSCOLORS; 1114 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1115 sc->sc_width / ri->ri_font->fontwidth); 1116 1117 /* enable acceleration */ 1118 ri->ri_ops.copyrows = ffb_ras_copyrows; 1119 ri->ri_ops.eraserows = ffb_ras_eraserows; 1120 ri->ri_ops.erasecols = ffb_ras_erasecols; 1121 ri->ri_ops.cursor = ffb_cursor; 1122 ri->ri_ops.allocattr = ffb_allocattr; 1123 ri->ri_ops.putchar = ffb_putchar; 1124 } 1125 1126 /* I2C bitbanging */ 1127 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1128 { 1129 struct ffb_softc *sc = cookie; 1130 1131 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1132 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1133 } 1134 1135 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1136 { 1137 /* Nothing to do */ 1138 } 1139 1140 static uint32_t ffb_i2cbb_read(void *cookie) 1141 { 1142 struct ffb_softc *sc = cookie; 1143 uint32_t bits; 1144 1145 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1146 bits = DAC_READ(sc, FFB_DAC_VALUE); 1147 1148 return bits; 1149 } 1150 1151 /* higher level I2C stuff */ 1152 static int 1153 ffb_i2c_acquire_bus(void *cookie, int flags) 1154 { 1155 /* private bus */ 1156 return (0); 1157 } 1158 1159 static void 1160 ffb_i2c_release_bus(void *cookie, int flags) 1161 { 1162 /* private bus */ 1163 } 1164 1165 static int 1166 ffb_i2c_send_start(void *cookie, int flags) 1167 { 1168 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1169 } 1170 1171 static int 1172 ffb_i2c_send_stop(void *cookie, int flags) 1173 { 1174 1175 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1176 } 1177 1178 static int 1179 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1180 { 1181 /* 1182 * for some reason i2c_bitbang_initiate_xfer left-shifts 1183 * the I2C-address and then sets the direction bit 1184 */ 1185 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1186 &ffb_i2cbb_ops)); 1187 } 1188 1189 static int 1190 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1191 { 1192 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1193 } 1194 1195 static int 1196 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1197 { 1198 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1199 } 1200 1201 1202 #define TVC_READ_LIMIT 100000 1203 int 1204 ffb_tgc_disable(struct ffb_softc *sc) 1205 { 1206 int i; 1207 1208 /* Is the timing generator disabled? */ 1209 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1210 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1211 return 1; 1212 1213 /* If not, disable it when the vertical counter reaches 0 */ 1214 for (i = 0; i < TVC_READ_LIMIT; i++) { 1215 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1216 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1217 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1218 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1219 return 1; 1220 } 1221 } 1222 return 0; 1223 } 1224 1225 /* 1226 * PLL Control Register values: 1227 * M)ultiplier = bits 0:6 + 1 1228 * D)ivisor = bits 7:10 + 1 1229 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1230 * Frequency = 13.5 * M / D / P 1231 */ 1232 #define FFB_PLL_FREQ 13500000 1233 void 1234 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1235 { 1236 int m, d, p, f, hex = 0, curdiff; 1237 1238 *diff = 100000000; 1239 1240 for (m = 32; m <= 80; m++) { 1241 for (d = 4; d <= 11; d++) { 1242 for (p = 1; p <= 8; p = p << 1) { 1243 switch (p) { 1244 case 1: 1245 hex = 0x4000 + (d << 7) + m; 1246 break; 1247 case 2: 1248 hex = 0x4800 + (d << 7) + m; 1249 break; 1250 case 4: 1251 hex = 0x5000 + (d << 7) + m; 1252 break; 1253 case 8: 1254 hex = 0x6000 + (d << 7) + m; 1255 break; 1256 } 1257 f = 13500000 * m / d / p; 1258 if (f == request) { 1259 *diff = 0; 1260 *pll = hex; 1261 return; 1262 } else { 1263 curdiff = abs(request - f); 1264 if (curdiff < *diff) { 1265 *diff = curdiff; 1266 *pll = hex; 1267 } 1268 } 1269 } 1270 } 1271 } 1272 } 1273 1274 /* 1275 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1276 * and in the Connexant BT497A/498A documentation. 1277 * 1278 * VESA timings to FFB register conversion: 1279 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1280 * VBE = VBS - vres = (sync pulse - 1) + back porch 1281 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1282 * VSE = sync pulse - 1 1283 * VSS = (sync pulse - 1) + back porch + vres + front porch 1284 * HRE = HSS - HSE - 1 1285 * HBE = (sync pulse + back porch) / x - 1 1286 * HBS = (sync pulse + back porch + hres) / x - 1 1287 * HSE = sync pulse / x - 1 1288 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1289 * HCE = HBS - 4 1290 * HCS = HBE - 4 1291 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1292 * 1293 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1294 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1295 * 1296 * Note, that the timing generator should be disabled and re-enabled when the 1297 * the timing parameter registers are being programmed. Stopping the timing 1298 * generator should only be done when the vertical counter is zero. 1299 */ 1300 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1301 int 1302 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1303 int *hres, int *vres) 1304 { 1305 int diff; 1306 uint32_t fp, sp, bp, x; 1307 uint32_t pll, pfc, ucl, dcl, tgc; 1308 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1309 uint32_t epe, eie, eis; 1310 uint32_t fbcfg0; 1311 1312 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1313 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1314 mode->htotal), mode->vtotal))); 1315 DPRINTF((" (%d %d %d %d %d %d %d", 1316 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1317 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1318 DPRINTF((" %s%sH %s%sV)\n", 1319 mode->flags & VID_PHSYNC ? "+" : "", 1320 mode->flags & VID_NHSYNC ? "-" : "", 1321 mode->flags & VID_PVSYNC ? "+" : "", 1322 mode->flags & VID_NVSYNC ? "-" : "")); 1323 1324 /* We don't handle interlaced or doublescan (yet) */ 1325 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1326 return 0; 1327 1328 /* Only Creator3D can be set to > 1280x1024 */ 1329 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1330 sc->sc_type == FFB_AFB) 1331 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1332 return 0; 1333 /* Creator3D can be set to <= 1920x1360 */ 1334 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1335 return 0; 1336 1337 /* 1338 * Look for a matching pixel clock and set PLL Control. 1339 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1340 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1341 * does not work. So, use the PROM value instead. 1342 */ 1343 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1344 mode->dot_clock == 25175) { 1345 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1346 mode->dot_clock = 25125; 1347 } 1348 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1349 if (diff > 250000) 1350 return 0; 1351 1352 /* Pixel Format Control, User Control and FBC Configuration. */ 1353 if (mode->hdisplay > 1280) { 1354 pfc = FFB_DAC_PIX_FMT_821; 1355 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1356 x = 4; 1357 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1358 } else { 1359 pfc = FFB_DAC_PIX_FMT_421; 1360 /* Only Creator3D and Elite3D can have double-buffer */ 1361 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1362 ucl = 0; 1363 else 1364 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1365 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1366 x = 2; 1367 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1368 } 1369 1370 /* DAC Control and Timing Generator Control */ 1371 if (mode->flags & VID_PVSYNC) 1372 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1373 else 1374 dcl = 0; 1375 tgc = 0; 1376 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1377 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1378 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1379 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1380 } else { 1381 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1382 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1383 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1384 else 1385 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1386 } 1387 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1388 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1389 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1390 FFB_DAC_TGC_MASTER_ENABLE); 1391 1392 /* Vertical timing */ 1393 fp = mode->vsync_start - mode->vdisplay; 1394 sp = mode->vsync_end - mode->vsync_start; 1395 bp = mode->vtotal - mode->vsync_end; 1396 1397 vbe = sp - 1 + bp; 1398 vbs = sp - 1 + bp + mode->vdisplay; 1399 vse = sp - 1; 1400 vss = sp - 1 + bp + mode->vdisplay + fp; 1401 1402 /* Horizontal timing */ 1403 fp = mode->hsync_start - mode->hdisplay; 1404 sp = mode->hsync_end - mode->hsync_start; 1405 bp = mode->htotal - mode->hsync_end; 1406 1407 hbe = (sp + bp) / x - 1; 1408 hbs = (sp + bp + mode->hdisplay) / x - 1; 1409 hse = sp / x - 1; 1410 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1411 hre = hss - hse - 1; 1412 hce = hbs - 4; 1413 hcs = hbe - 4; 1414 1415 /* Equalisation (interlaced modes) */ 1416 epe = 0; 1417 eie = 0; 1418 eis = 0; 1419 1420 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1421 pll, pfc, ucl, dcl, tgc)); 1422 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1423 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1424 hre, hbe, hbs, hse, hss, hce, hcs)); 1425 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1426 1427 if (!ffb_tgc_disable(sc)) { 1428 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1429 return 0; 1430 } 1431 1432 /* 1433 * Program the mode registers. 1434 * Program the timing generator last, as that re-enables output. 1435 * Note, that a read to/write from a register increments the 1436 * register address to the next register automatically. 1437 */ 1438 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1439 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1440 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1441 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1442 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1443 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1444 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1445 1446 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1447 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1448 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1449 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1450 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1451 1452 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1453 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1454 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1455 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1456 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1457 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1458 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1459 1460 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1461 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1462 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1463 1464 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1465 1466 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1467 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1468 DPRINTF(("new tgc: %08x\n", tgc)); 1469 1470 *hres = mode->hdisplay; 1471 *vres = mode->vdisplay; 1472 1473 printf("%s: video mode set to %d x %d @ %dHz\n", 1474 device_xname(sc->sc_dev), 1475 mode->hdisplay, mode->vdisplay, 1476 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1477 mode->htotal), mode->vtotal)); 1478 1479 return 1; 1480 } 1481