1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)vaddrs.h 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: vaddrs.h,v 1.3 92/11/26 03:05:11 torek Exp 45 * $Id: vaddrs.h,v 1.1 1993/10/02 10:24:31 deraadt Exp $ 46 */ 47 48 /* 49 * Special (fixed) virtual addresses on the SPARC. 50 * 51 * IO virtual space begins at 0xfe000000 (a segment boundary) and 52 * continues up to the DMVA edge at 0xff000000. (The upper all-1s 53 * byte is special since some of the hardware supplies this to pad 54 * a 24-bit address space out to 32 bits. This is a legacy of the 55 * IBM PC AT bus, actually, just so you know who to blame.) 56 * 57 * We reserve several pages at the base of our IO virtual space 58 * for `oft-used' devices which must be present anyway in order to 59 * configure. In particular, we want the counter-timer register and 60 * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 61 * microtime() and the zs hardware interrupt handlers faster. 62 * 63 * Ideally, we should map the interrupt enable register here as well, 64 * but that would require allocating pmegs in locore.s, so instead we 65 * use one of the two `wasted' pages at KERNBASE+2*NBPG (see locore.s). 66 */ 67 68 #ifndef IODEV_0 69 #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 70 71 #define TIMERREG_VA (IODEV_0 + 0*NBPG) 72 #define ZS0_VA (IODEV_0 + 1*NBPG) 73 #define ZS1_VA (IODEV_0 + 2*NBPG) 74 #define AUXREG_VA (IODEV_0 + 3*NBPG) 75 #define IODEV_BASE (IODEV_0 + 4*NBPG) 76 #define IODEV_END 0xff000000 /* 16 MB of iospace */ 77 78 #define DVMA_BASE 0xfff00000 79 #define DVMA_END 0xfffc0000 80 81 #endif /* IODEV_0 */ 82