1 /* $NetBSD: intreg.h,v 1.5 1996/03/31 23:03:39 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)intreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sparc/sparc/vaddrs.h> 48 49 /* 50 * sun4c interrupt enable register. 51 * 52 * The register is a single byte. C code must use the ienab_bis and 53 * ienab_bic functions found in locore.s. 54 * 55 * The register's physical address is defined here as the register 56 * must be mapped early in the boot process (otherwise NMI handling 57 * will fail). 58 */ 59 #define INT_ENABLE_REG_PHYSADR 0xf5000000 /* phys addr in IOspace */ 60 61 /* 62 * Bits in interrupt enable register. Software interrupt requests must 63 * be cleared in software. This is done in locore.s. The ALLIE bit must 64 * be cleared to clear asynchronous memory error (level 15) interrupts. 65 */ 66 #define IE_L14 0x80 /* enable level 14 (counter 1) interrupts */ 67 #define IE_L10 0x20 /* enable level 10 (counter 0) interrupts */ 68 #define IE_L8 0x10 /* enable level 8 interrupts */ 69 #define IE_L6 0x08 /* request software level 6 interrupt */ 70 #define IE_L4 0x04 /* request software level 4 interrupt */ 71 #define IE_L1 0x02 /* request software level 1 interrupt */ 72 #define IE_ALLIE 0x01 /* enable interrupts */ 73 74 #ifndef _LOCORE 75 void ienab_bis __P((int bis)); /* set given bits */ 76 void ienab_bic __P((int bic)); /* clear given bits */ 77 #endif 78 79 #if defined(SUN4M) 80 #ifdef notyet 81 #define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc) 82 #define IENAB_P0 0x0008 83 #define IENAB_P1 0x1008 84 #define IENAB_P2 0x2008 85 #define IENAB_P3 0x3008 86 #endif /* notyet */ 87 #endif 88 89 #if defined(SUN4M) 90 /* 91 * Interrupt Control Registers, located in IO space. 92 * (mapped to `locore' for now..) 93 * There are two sets of interrupt registers called `Processor Interrupts' 94 * and `System Interrupts'. The `Processor' set corresponds to the 15 95 * interrupt levels as seen by the CPU. The `System' set corresponds to 96 * a set of devices supported by the implementing chip-set. 97 * 98 * Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are 99 * system-wide interrupts, and the ICR_ITR selects the processor to get 100 * the system's interrupts. 101 */ 102 #define ICR_PI_PEND (PI_INTR_VA + 0x0) 103 #define ICR_PI_CLR (PI_INTR_VA + 0x4) 104 #define ICR_PI_SET (PI_INTR_VA + 0x8) 105 #define ICR_SI_PEND (SI_INTR_VA) 106 #define ICR_SI_MASK (SI_INTR_VA + 0x4) 107 #define ICR_SI_CLR (SI_INTR_VA + 0x8) 108 #define ICR_SI_SET (SI_INTR_VA + 0xc) 109 #define ICR_ITR (SI_INTR_VA + 0x10) 110 111 /* 112 * Bits in interrupt registers. Software interrupt requests must 113 * be cleared in software. This is done in locore.s. 114 * There are separate registers for reading pending interrupts and 115 * setting/clearing (software) interrupts. 116 */ 117 #define PINTR_SINTRLEV(n) (1 << (16 + (n))) 118 #define PINTR_IC 0x8000 /* Level 15 clear */ 119 120 #define SINTR_MA 0x80000000 /* Mask All interrupts */ 121 #define SINTR_ME 0x40000000 /* Module Error (async) */ 122 #define SINTR_I 0x20000000 /* MSI (MBus-SBus) */ 123 #define SINTR_M 0x10000000 /* ECC Memory controller */ 124 #define SINTR_RSVD2 0x0f800000 125 #define SINTR_F 0x00400000 /* Floppy */ 126 #define SINTR_RSVD3 0x00200000 127 #define SINTR_V 0x00100000 /* Video (Supersparc only) */ 128 #define SINTR_T 0x00080000 /* Level 10 counter */ 129 #define SINTR_SC 0x00040000 /* SCSI */ 130 #define SINTR_RSVD4 0x00020000 131 #define SINTR_E 0x00010000 /* Ethernet */ 132 #define SINTR_S 0x00008000 /* Serial port */ 133 #define SINTR_K 0x00004000 /* Keyboard/mouse */ 134 #define SINTR_SBUSMASK 0x00003f80 /* SBus */ 135 #define SINTR_SBUS(n) (((n) << 7) & 0x00003f80) 136 #define SINTR_RSVD5 0x0000007f 137 138 #endif 139